Lines Matching +full:spi +full:- +full:cs +full:- +full:high
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm016-dc2 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
35 stdout-path = "serial0:115200n8";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_can0_default>;
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_can1_default>;
90 phy-handle = <&phy0>;
91 phy-mode = "rgmii-id";
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_gem2_default>;
94 phy0: ethernet-phy@5 {
96 ti,rx-internal-delay = <0x8>;
97 ti,tx-internal-delay = <0xa>;
98 ti,fifo-depth = <0x1>;
99 ti,dp83867-rxctrl-strap-quirk;
109 clock-frequency = <400000>;
110 pinctrl-names = "default", "gpio";
111 pinctrl-0 = <&pinctrl_i2c0_default>;
112 pinctrl-1 = <&pinctrl_i2c0_gpio>;
113 scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
114 sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
119 gpio-controller;
120 #gpio-cells = <2>;
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_nand0_default>;
134 arasan,has-mdma;
138 #address-cells = <0x2>;
139 #size-cells = <0x1>;
140 nand-ecc-mode = "soft";
141 nand-ecc-algo = "bch";
142 nand-rb = <0>;
143 label = "main-storage-0";
147 #address-cells = <0x2>;
148 #size-cells = <0x1>;
149 nand-ecc-mode = "soft";
150 nand-ecc-algo = "bch";
151 nand-rb = <0>;
152 label = "main-storage-1";
158 pinctrl_can0_default: can0-default {
166 slew-rate = <SLEW_RATE_SLOW>;
167 power-source = <IO_STANDARD_LVCMOS18>;
170 conf-rx {
172 bias-high-impedance;
175 conf-tx {
177 bias-disable;
181 pinctrl_can1_default: can1-default {
189 slew-rate = <SLEW_RATE_SLOW>;
190 power-source = <IO_STANDARD_LVCMOS18>;
193 conf-rx {
195 bias-high-impedance;
198 conf-tx {
200 bias-disable;
204 pinctrl_i2c0_default: i2c0-default {
212 bias-pull-up;
213 slew-rate = <SLEW_RATE_SLOW>;
214 power-source = <IO_STANDARD_LVCMOS18>;
218 pinctrl_i2c0_gpio: i2c0-gpio {
226 slew-rate = <SLEW_RATE_SLOW>;
227 power-source = <IO_STANDARD_LVCMOS18>;
231 pinctrl_uart0_default: uart0-default {
239 slew-rate = <SLEW_RATE_SLOW>;
240 power-source = <IO_STANDARD_LVCMOS18>;
243 conf-rx {
245 bias-high-impedance;
248 conf-tx {
250 bias-disable;
254 pinctrl_uart1_default: uart1-default {
262 slew-rate = <SLEW_RATE_SLOW>;
263 power-source = <IO_STANDARD_LVCMOS18>;
266 conf-rx {
268 bias-high-impedance;
271 conf-tx {
273 bias-disable;
277 pinctrl_usb1_default: usb1-default {
285 power-source = <IO_STANDARD_LVCMOS18>;
288 conf-rx {
290 bias-high-impedance;
291 drive-strength = <12>;
292 slew-rate = <SLEW_RATE_FAST>;
295 conf-tx {
298 bias-disable;
299 drive-strength = <4>;
300 slew-rate = <SLEW_RATE_SLOW>;
304 pinctrl_gem2_default: gem2-default {
312 slew-rate = <SLEW_RATE_SLOW>;
313 power-source = <IO_STANDARD_LVCMOS18>;
316 conf-rx {
319 bias-high-impedance;
320 low-power-disable;
323 conf-tx {
326 bias-disable;
327 low-power-enable;
330 mux-mdio {
335 conf-mdio {
337 slew-rate = <SLEW_RATE_SLOW>;
338 power-source = <IO_STANDARD_LVCMOS18>;
339 bias-disable;
343 pinctrl_nand0_default: nand0-default {
351 bias-pull-up;
354 mux-ce {
359 conf-ce {
361 bias-pull-up;
364 mux-rb {
369 conf-rb {
371 bias-pull-up;
374 mux-dqs {
379 conf-dqs {
381 bias-pull-up;
385 pinctrl_spi0_default: spi0-default {
393 bias-disable;
394 slew-rate = <SLEW_RATE_SLOW>;
395 power-source = <IO_STANDARD_LVCMOS18>;
398 mux-cs {
404 conf-cs {
407 bias-disable;
411 pinctrl_spi1_default: spi1-default {
419 bias-disable;
420 slew-rate = <SLEW_RATE_SLOW>;
421 power-source = <IO_STANDARD_LVCMOS18>;
424 mux-cs {
430 conf-cs {
433 bias-disable;
444 num-cs = <1>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_spi0_default>;
449 #address-cells = <1>;
450 #size-cells = <1>;
451 compatible = "sst,sst25wf080", "jedec,spi-nor";
452 spi-max-frequency = <50000000>;
456 label = "spi0-data";
464 num-cs = <1>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_spi1_default>;
469 #address-cells = <1>;
470 #size-cells = <1>;
472 spi-max-frequency = <20000000>;
476 label = "spi1-data";
485 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_usb1_default>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_uart0_default>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_uart1_default>;