dts/xilinx/zynqmp-zc1751-xm015-dc1.dts

1 // SPDX-License-Identifier: GPL-2.0+
3  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5  * (C) Copyright 2015 - 2022, Xilinx, Inc.
6  * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 	model = "ZynqMP zc1751-xm015-dc1 RevA";
21 	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
36 		stdout-path = "serial0:115200n8";
44 	clock_si5338_0: clk27 {	/* u55 SI5338-GM */
45 		compatible = "fixed-clock";
46 		#clock-cells = <0>;
47 		clock-frequency = <27000000>;
51 		compatible = "fixed-clock";
52 		#clock-cells = <0>;
53 		clock-frequency = <26000000>;
57 		compatible = "fixed-clock";
58 		#clock-cells = <0>;
59 		clock-frequency = <150000000>;
97 	phy-handle = <&phy0>;
98 	phy-mode = "rgmii-id";
99 	pinctrl-names = "default";
100 	pinctrl-0 = <&pinctrl_gem3_default>;
101 	phy0: ethernet-phy@0 {
108 	pinctrl-names = "default";
109 	pinctrl-0 = <&pinctrl_gpio_default>;
118 	clock-frequency = <400000>;
119 	pinctrl-names = "default", "gpio";
120 	pinctrl-0 = <&pinctrl_i2c1_default>;
121 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
122 	scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
123 	sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
133 	pinctrl_i2c1_default: i2c1-default {
141 			bias-pull-up;
142 			slew-rate = <SLEW_RATE_SLOW>;
143 			power-source = <IO_STANDARD_LVCMOS18>;
147 	pinctrl_i2c1_gpio: i2c1-gpio {
155 			slew-rate = <SLEW_RATE_SLOW>;
156 			power-source = <IO_STANDARD_LVCMOS18>;
160 	pinctrl_uart0_default: uart0-default {
168 			slew-rate = <SLEW_RATE_SLOW>;
169 			power-source = <IO_STANDARD_LVCMOS18>;
172 		conf-rx {
174 			bias-high-impedance;
177 		conf-tx {
179 			bias-disable;
183 	pinctrl_usb0_default: usb0-default {
191 			power-source = <IO_STANDARD_LVCMOS18>;
194 		conf-rx {
196 			bias-high-impedance;
197 			drive-strength = <12>;
198 			slew-rate = <SLEW_RATE_FAST>;
201 		conf-tx {
204 			bias-disable;
205 			drive-strength = <4>;
206 			slew-rate = <SLEW_RATE_SLOW>;
210 	pinctrl_gem3_default: gem3-default {
218 			slew-rate = <SLEW_RATE_SLOW>;
219 			power-source = <IO_STANDARD_LVCMOS18>;
222 		conf-rx {
225 			bias-high-impedance;
226 			low-power-disable;
229 		conf-tx {
232 			bias-disable;
233 			low-power-enable;
236 		mux-mdio {
241 		conf-mdio {
243 			slew-rate = <SLEW_RATE_SLOW>;
244 			power-source = <IO_STANDARD_LVCMOS18>;
245 			bias-disable;
249 	pinctrl_sdhci0_default: sdhci0-default {
257 			slew-rate = <SLEW_RATE_SLOW>;
258 			power-source = <IO_STANDARD_LVCMOS18>;
259 			bias-disable;
262 		mux-cd {
267 		conf-cd {
269 			bias-high-impedance;
270 			bias-pull-up;
271 			slew-rate = <SLEW_RATE_SLOW>;
272 			power-source = <IO_STANDARD_LVCMOS18>;
275 		mux-wp {
280 		conf-wp {
282 			bias-high-impedance;
283 			bias-pull-up;
284 			slew-rate = <SLEW_RATE_SLOW>;
285 			power-source = <IO_STANDARD_LVCMOS18>;
289 	pinctrl_sdhci1_default: sdhci1-default {
297 			slew-rate = <SLEW_RATE_SLOW>;
298 			power-source = <IO_STANDARD_LVCMOS18>;
299 			bias-disable;
302 		mux-cd {
307 		conf-cd {
309 			bias-high-impedance;
310 			bias-pull-up;
311 			slew-rate = <SLEW_RATE_SLOW>;
312 			power-source = <IO_STANDARD_LVCMOS18>;
315 		mux-wp {
320 		conf-wp {
322 			bias-high-impedance;
323 			bias-pull-up;
324 			slew-rate = <SLEW_RATE_SLOW>;
325 			power-source = <IO_STANDARD_LVCMOS18>;
329 	pinctrl_gpio_default: gpio-default {
337 			bias-disable;
338 			slew-rate = <SLEW_RATE_SLOW>;
339 			power-source = <IO_STANDARD_LVCMOS18>;
348 	clock-names = "ref1", "ref2", "ref3";
354 		compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
355 		#address-cells = <1>;
356 		#size-cells = <1>;
358 		spi-tx-bus-width = <4>;
359 		spi-rx-bus-width = <4>;
360 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
371 	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
372 	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
373 	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
374 	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
375 	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
376 	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
377 	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
378 	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
379 	phy-names = "sata-phy";
386 	pinctrl-names = "default";
387 	pinctrl-0 = <&pinctrl_sdhci0_default>;
388 	bus-width = <8>;
389 	xlnx,mio-bank = <0>;
398 	no-1-8-v;
399 	pinctrl-names = "default";
400 	pinctrl-0 = <&pinctrl_sdhci1_default>;
401 	xlnx,mio-bank = <1>;
406 	pinctrl-names = "default";
407 	pinctrl-0 = <&pinctrl_uart0_default>;
413 	pinctrl-names = "default";
414 	pinctrl-0 = <&pinctrl_usb0_default>;
415 	phy-names = "usb3-phy";
423 	maximum-speed = "super-speed";
432 	phy-names = "dp-phy0", "dp-phy1";