Lines Matching refs:zynqmp_clk

50 	zynqmp_clk: clock-controller {  label
62 	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
66 	clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
70 	clocks = <&zynqmp_clk ACPU>;
74 	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
78 	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
82 	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
86 	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
90 	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
94 	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
98 	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
102 	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
106 	clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
110 	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
114 	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
118 	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
122 	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
126 	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
130 	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
134 	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
138 	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
142 	clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
146 	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
147 		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
148 		 <&zynqmp_clk GEM_TSU>;
149 	assigned-clocks = <&zynqmp_clk GEM_TSU>;
153 	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
154 		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
155 		 <&zynqmp_clk GEM_TSU>;
156 	assigned-clocks = <&zynqmp_clk GEM_TSU>;
160 	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
161 		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
162 		 <&zynqmp_clk GEM_TSU>;
163 	assigned-clocks = <&zynqmp_clk GEM_TSU>;
167 	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
168 		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
169 		 <&zynqmp_clk GEM_TSU>;
170 	assigned-clocks = <&zynqmp_clk GEM_TSU>;
174 	clocks = <&zynqmp_clk LPD_LSBUS>;
178 	clocks = <&zynqmp_clk I2C0_REF>;
182 	clocks = <&zynqmp_clk I2C1_REF>;
186 	clocks = <&zynqmp_clk PCIE_REF>;
190 	clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
194 	clocks = <&zynqmp_clk SATA_REF>;
198 	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
199 	assigned-clocks = <&zynqmp_clk SDIO0_REF>;
203 	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
204 	assigned-clocks = <&zynqmp_clk SDIO1_REF>;
208 	clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
212 	clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
216 	clocks = <&zynqmp_clk LPD_LSBUS>;
220 	clocks = <&zynqmp_clk LPD_LSBUS>;
224 	clocks = <&zynqmp_clk LPD_LSBUS>;
228 	clocks = <&zynqmp_clk LPD_LSBUS>;
232 	clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
236 	clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
240 	clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
244 	clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
248 	clocks = <&zynqmp_clk WDT>;
252 	clocks = <&zynqmp_clk LPD_WDT>;
256 	clocks = <&zynqmp_clk AMS_REF>;
260 	clocks = <&zynqmp_clk DPDMA_REF>;
261 	assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
265 	clocks = <&zynqmp_clk TOPSW_LSBUS>,
266 		 <&zynqmp_clk DP_AUDIO_REF>,
267 		 <&zynqmp_clk DP_VIDEO_REF>;
268 	assigned-clocks = <&zynqmp_clk DP_STC_REF>,
269 			  <&zynqmp_clk DP_AUDIO_REF>,
270 			  <&zynqmp_clk DP_VIDEO_REF>;  /* rpll, rpll, vpll */