Lines Matching +full:k2g +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 bootph-all;
11 compatible = "ti,k2g-sci";
12 ti,host-id = <12>;
14 mbox-names = "rx", "tx";
19 reg-names = "debug_messages";
22 k3_pds: power-controller {
23 bootph-all;
24 compatible = "ti,sci-pm-domain";
25 #power-domain-cells = <2>;
28 k3_clks: clock-controller {
29 bootph-all;
30 compatible = "ti,k2g-sci-clk";
31 #clock-cells = <2>;
34 k3_reset: reset-controller {
35 bootph-all;
36 compatible = "ti,sci-reset";
37 #reset-cells = <2>;
42 bootph-all;
43 compatible = "ti,am654-chipid";
48 compatible = "ti,am654-secure-proxy";
49 #mbox-cells = <1>;
50 reg-names = "target_data", "rt", "scfg";
57 * firmware on non-MPU processors
63 compatible = "mmio-sram";
66 #address-cells = <1>;
67 #size-cells = <1>;
71 compatible = "pinctrl-single";
74 #pinctrl-cells = <1>;
75 pinctrl-single,register-width = <32>;
76 pinctrl-single,function-mask = <0xffffffff>;
80 compatible = "pinctrl-single";
83 #pinctrl-cells = <1>;
84 pinctrl-single,register-width = <32>;
85 pinctrl-single,function-mask = <0xffffffff>;
89 compatible = "pinctrl-single";
92 #pinctrl-cells = <1>;
93 pinctrl-single,register-width = <32>;
94 pinctrl-single,function-mask = <0xffffffff>;
98 compatible = "pinctrl-single";
101 #pinctrl-cells = <1>;
102 pinctrl-single,register-width = <32>;
103 pinctrl-single,function-mask = <0xffffffff>;
106 wkup_gpio_intr: interrupt-controller@42200000 {
107 compatible = "ti,sci-intr";
109 ti,intr-trigger-type = <1>;
110 interrupt-controller;
111 interrupt-parent = <&gic500>;
112 #interrupt-cells = <1>;
114 ti,sci-dev-id = <177>;
115 ti,interrupt-ranges = <16 960 16>;
120 compatible = "pinctrl-single";
122 #pinctrl-cells = <1>;
123 pinctrl-single,register-width = <32>;
124 pinctrl-single,function-mask = <0x0000000f>;
125 /* Non-MPU Firmware usage */
131 compatible = "pinctrl-single";
133 #pinctrl-cells = <1>;
134 pinctrl-single,register-width = <32>;
135 pinctrl-single,function-mask = <0x0000000f>;
136 /* Non-MPU Firmware usage */
141 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
143 #address-cells = <1>;
144 #size-cells = <1>;
148 compatible = "ti,am654-phy-gmii-sel";
150 #phy-cells = <1>;
155 compatible = "ti,am654-timer";
159 clock-names = "fck";
160 assigned-clocks = <&k3_clks 35 2>;
161 assigned-clock-parents = <&k3_clks 35 3>;
162 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
163 ti,timer-pwm;
164 /* Non-MPU Firmware usage */
169 bootph-all;
170 compatible = "ti,am654-timer";
174 clock-names = "fck";
175 assigned-clocks = <&k3_clks 117 2>;
176 assigned-clock-parents = <&k3_clks 117 3>;
177 power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
178 ti,timer-pwm;
179 /* Non-MPU Firmware usage */
184 compatible = "ti,am654-timer";
188 clock-names = "fck";
189 assigned-clocks = <&k3_clks 118 2>;
190 assigned-clock-parents = <&k3_clks 118 3>;
191 power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>;
192 ti,timer-pwm;
193 /* Non-MPU Firmware usage */
198 compatible = "ti,am654-timer";
202 clock-names = "fck";
203 assigned-clocks = <&k3_clks 119 2>;
204 assigned-clock-parents = <&k3_clks 119 3>;
205 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
206 ti,timer-pwm;
207 /* Non-MPU Firmware usage */
212 compatible = "ti,am654-timer";
216 clock-names = "fck";
217 assigned-clocks = <&k3_clks 120 2>;
218 assigned-clock-parents = <&k3_clks 120 3>;
219 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
220 ti,timer-pwm;
221 /* Non-MPU Firmware usage */
226 compatible = "ti,am654-timer";
230 clock-names = "fck";
231 assigned-clocks = <&k3_clks 121 2>;
232 assigned-clock-parents = <&k3_clks 121 3>;
233 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
234 ti,timer-pwm;
235 /* Non-MPU Firmware usage */
240 compatible = "ti,am654-timer";
244 clock-names = "fck";
245 assigned-clocks = <&k3_clks 122 2>;
246 assigned-clock-parents = <&k3_clks 122 3>;
247 power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>;
248 ti,timer-pwm;
249 /* Non-MPU Firmware usage */
254 compatible = "ti,am654-timer";
258 clock-names = "fck";
259 assigned-clocks = <&k3_clks 123 2>;
260 assigned-clock-parents = <&k3_clks 123 3>;
261 power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>;
262 ti,timer-pwm;
263 /* Non-MPU Firmware usage */
268 compatible = "ti,am654-timer";
272 clock-names = "fck";
273 assigned-clocks = <&k3_clks 124 2>;
274 assigned-clock-parents = <&k3_clks 124 3>;
275 power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>;
276 ti,timer-pwm;
277 /* Non-MPU Firmware usage */
282 compatible = "ti,am654-timer";
286 clock-names = "fck";
287 assigned-clocks = <&k3_clks 125 2>;
288 assigned-clock-parents = <&k3_clks 125 3>;
289 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
290 ti,timer-pwm;
291 /* Non-MPU Firmware usage */
296 compatible = "ti,j721e-uart", "ti,am654-uart";
299 current-speed = <115200>;
301 clock-names = "fclk";
302 power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
307 compatible = "ti,j721e-uart", "ti,am654-uart";
310 current-speed = <115200>;
312 clock-names = "fclk";
313 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
317 wkup_gpio0: gpio@42110000 {
318 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-parent = <&wkup_gpio_intr>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
327 ti,davinci-gpio-unbanked = <0>;
328 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
330 clock-names = "gpio";
334 wkup_gpio1: gpio@42100000 {
335 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
337 gpio-controller;
338 #gpio-cells = <2>;
339 interrupt-parent = <&wkup_gpio_intr>;
341 interrupt-controller;
342 #interrupt-cells = <2>;
344 ti,davinci-gpio-unbanked = <0>;
345 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
347 clock-names = "gpio";
352 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
355 #address-cells = <1>;
356 #size-cells = <0>;
358 clock-names = "fck";
359 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
364 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
367 #address-cells = <1>;
368 #size-cells = <0>;
370 clock-names = "fck";
371 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
376 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
379 #address-cells = <1>;
380 #size-cells = <0>;
382 clock-names = "fck";
383 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
391 reg-names = "m_can", "message_ram";
392 power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
394 clock-names = "hclk", "cclk";
397 interrupt-names = "int0", "int1";
398 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
406 reg-names = "m_can", "message_ram";
407 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
409 clock-names = "hclk", "cclk";
412 interrupt-names = "int0", "int1";
413 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
418 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
421 #address-cells = <1>;
422 #size-cells = <0>;
423 power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>;
429 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
432 #address-cells = <1>;
433 #size-cells = <0>;
434 power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>;
440 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
443 #address-cells = <1>;
444 #size-cells = <0>;
445 power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>;
451 bootph-all;
452 compatible = "simple-bus";
453 #address-cells = <2>;
454 #size-cells = <2>;
456 ti,sci-dev-id = <323>;
457 dma-coherent;
458 dma-ranges;
461 bootph-all;
462 compatible = "ti,am654-navss-ringacc";
468 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
469 ti,num-rings = <286>;
470 ti,sci-rm-range-gp-rings = <0x1>;
472 ti,sci-dev-id = <328>;
473 msi-parent = <&main_udmass_inta>;
476 mcu_udmap: dma-controller@285c0000 {
477 bootph-all;
478 compatible = "ti,j721e-navss-mcu-udmap";
482 reg-names = "gcfg", "rchanrt", "tchanrt";
483 msi-parent = <&main_udmass_inta>;
484 #dma-cells = <1>;
487 ti,sci-dev-id = <329>;
489 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
491 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
493 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
498 compatible = "ti,am654-secure-proxy";
499 #mbox-cells = <1>;
500 reg-names = "target_data", "rt", "scfg";
507 * firmware on non-MPU processors
513 compatible = "ti,j721e-cpsw-nuss";
514 #address-cells = <2>;
515 #size-cells = <2>;
517 reg-names = "cpsw_nuss";
519 dma-coherent;
521 clock-names = "fck";
522 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
533 dma-names = "tx0", "tx1", "tx2", "tx3",
538 ethernet-ports {
539 #address-cells = <1>;
540 #size-cells = <0>;
544 ti,mac-only;
546 ti,syscon-efuse = <&mcu_conf 0x200>;
552 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
554 #address-cells = <1>;
555 #size-cells = <0>;
557 clock-names = "fck";
562 compatible = "ti,am65-cpts";
565 clock-names = "cpts";
566 assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */
567 assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */
568 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
569 interrupt-names = "cpts";
570 ti,cpts-ext-ts-inputs = <4>;
571 ti,cpts-periodic-outputs = <2>;
576 compatible = "ti,j721s2-r5fss";
577 ti,cluster-mode = <1>;
578 #address-cells = <1>;
579 #size-cells = <1>;
582 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
585 compatible = "ti,j721s2-r5f";
588 reg-names = "atcm", "btcm";
590 ti,sci-dev-id = <346>;
591 ti,sci-proc-ids = <0x01 0xff>;
593 firmware-name = "j784s4-mcu-r5f0_0-fw";
594 ti,atcm-enable = <1>;
595 ti,btcm-enable = <1>;
600 compatible = "ti,j721s2-r5f";
603 reg-names = "atcm", "btcm";
605 ti,sci-dev-id = <347>;
606 ti,sci-proc-ids = <0x02 0xff>;
608 firmware-name = "j784s4-mcu-r5f0_1-fw";
609 ti,atcm-enable = <1>;
610 ti,btcm-enable = <1>;
615 wkup_vtm0: temperature-sensor@42040000 {
616 compatible = "ti,j7200-vtm";
619 power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>;
620 #thermal-sensor-cells = <1>;
624 compatible = "ti,am3359-tscadc";
627 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
629 assigned-clocks = <&k3_clks 0 2>;
630 assigned-clock-rates = <60000000>;
631 clock-names = "fck";
634 dma-names = "fifo0", "fifo1";
638 #io-channel-cells = <1>;
639 compatible = "ti,am3359-adc";
644 compatible = "ti,am3359-tscadc";
647 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
649 assigned-clocks = <&k3_clks 1 2>;
650 assigned-clock-rates = <60000000>;
651 clock-names = "fck";
654 dma-names = "fifo0", "fifo1";
658 #io-channel-cells = <1>;
659 compatible = "ti,am3359-adc";
664 compatible = "simple-bus";
666 #address-cells = <2>;
667 #size-cells = <2>;
671 compatible = "ti,am654-ospi", "cdns,qspi-nor";
675 cdns,fifo-depth = <256>;
676 cdns,fifo-width = <4>;
677 cdns,trigger-address = <0x0>;
679 assigned-clocks = <&k3_clks 161 7>;
680 assigned-clock-parents = <&k3_clks 161 9>;
681 assigned-clock-rates = <166666666>;
682 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
683 #address-cells = <1>;
684 #size-cells = <0>;
689 compatible = "ti,am654-ospi", "cdns,qspi-nor";
693 cdns,fifo-depth = <256>;
694 cdns,fifo-width = <4>;
695 cdns,trigger-address = <0x0>;
697 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
698 #address-cells = <1>;
699 #size-cells = <0>;