Lines Matching +full:0 +full:xf005
20 reg = <0x00 0x44083000 0x00 0x1000>;
44 reg = <0x00 0x43000014 0x00 0x4>;
51 reg = <0x00 0x43600000 0x00 0x10000>,
52 <0x00 0x44880000 0x00 0x20000>,
53 <0x00 0x44860000 0x00 0x20000>;
64 reg = <0x00 0x41c00000 0x00 0x100000>;
65 ranges = <0x00 0x00 0x41c00000 0x100000>;
72 /* Proxy 0 addressing */
73 reg = <0x00 0x4301c000 0x00 0x034>;
76 pinctrl-single,function-mask = <0xffffffff>;
81 /* Proxy 0 addressing */
82 reg = <0x00 0x4301c038 0x00 0x02c>;
85 pinctrl-single,function-mask = <0xffffffff>;
90 /* Proxy 0 addressing */
91 reg = <0x00 0x4301c068 0x00 0x120>;
94 pinctrl-single,function-mask = <0xffffffff>;
99 /* Proxy 0 addressing */
100 reg = <0x00 0x4301c190 0x00 0x004>;
103 pinctrl-single,function-mask = <0xffffffff>;
108 reg = <0x00 0x42200000 0x00 0x400>;
121 reg = <0x00 0x40f04200 0x00 0x28>;
124 pinctrl-single,function-mask = <0x0000000f>;
132 reg = <0x00 0x40f04280 0x00 0x28>;
135 pinctrl-single,function-mask = <0x0000000f>;
142 reg = <0x00 0x40f00000 0x00 0x20000>;
145 ranges = <0x00 0x00 0x40f00000 0x20000>;
149 reg = <0x4040 0x4>;
156 reg = <0x00 0x40400000 0x00 0x400>;
171 reg = <0x00 0x40410000 0x00 0x400>;
185 reg = <0x00 0x40420000 0x00 0x400>;
199 reg = <0x00 0x40430000 0x00 0x400>;
213 reg = <0x00 0x40440000 0x00 0x400>;
227 reg = <0x00 0x40450000 0x00 0x400>;
241 reg = <0x00 0x40460000 0x00 0x400>;
255 reg = <0x00 0x40470000 0x00 0x400>;
269 reg = <0x00 0x40480000 0x00 0x400>;
283 reg = <0x00 0x40490000 0x00 0x400>;
297 reg = <0x00 0x42300000 0x00 0x200>;
300 clocks = <&k3_clks 397 0>;
308 reg = <0x00 0x40a00000 0x00 0x200>;
311 clocks = <&k3_clks 149 0>;
319 reg = <0x00 0x42110000 0x00 0x100>;
327 ti,davinci-gpio-unbanked = <0>;
329 clocks = <&k3_clks 167 0>;
336 reg = <0x00 0x42100000 0x00 0x100>;
344 ti,davinci-gpio-unbanked = <0>;
346 clocks = <&k3_clks 168 0>;
353 reg = <0x00 0x42120000 0x00 0x100>;
356 #size-cells = <0>;
365 reg = <0x00 0x40b00000 0x00 0x100>;
368 #size-cells = <0>;
377 reg = <0x00 0x40b10000 0x00 0x100>;
380 #size-cells = <0>;
389 reg = <0x00 0x40528000 0x00 0x200>,
390 <0x00 0x40500000 0x00 0x8000>;
398 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
404 reg = <0x00 0x40568000 0x00 0x200>,
405 <0x00 0x40540000 0x00 0x8000>;
413 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
419 reg = <0x00 0x040300000 0x00 0x400>;
422 #size-cells = <0>;
424 clocks = <&k3_clks 384 0>;
430 reg = <0x00 0x040310000 0x00 0x400>;
433 #size-cells = <0>;
435 clocks = <&k3_clks 385 0>;
441 reg = <0x00 0x040320000 0x00 0x400>;
444 #size-cells = <0>;
446 clocks = <&k3_clks 386 0>;
455 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
463 reg = <0x00 0x2b800000 0x00 0x400000>,
464 <0x00 0x2b000000 0x00 0x400000>,
465 <0x00 0x28590000 0x00 0x100>,
466 <0x00 0x2a500000 0x00 0x40000>,
467 <0x00 0x28440000 0x00 0x40000>;
470 ti,sci-rm-range-gp-rings = <0x1>;
479 reg = <0x00 0x285c0000 0x00 0x100>,
480 <0x00 0x2a800000 0x00 0x40000>,
481 <0x00 0x2aa00000 0x00 0x40000>;
489 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
490 <0x0f>; /* TX_HCHAN */
491 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
492 <0x0b>; /* RX_HCHAN */
493 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
501 reg = <0x00 0x2a480000 0x00 0x80000>,
502 <0x00 0x2a380000 0x00 0x80000>,
503 <0x00 0x2a400000 0x00 0x80000>;
516 reg = <0x00 0x46000000 0x00 0x200000>;
518 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
520 clocks = <&k3_clks 63 0>;
524 dmas = <&mcu_udmap 0xf000>,
525 <&mcu_udmap 0xf001>,
526 <&mcu_udmap 0xf002>,
527 <&mcu_udmap 0xf003>,
528 <&mcu_udmap 0xf004>,
529 <&mcu_udmap 0xf005>,
530 <&mcu_udmap 0xf006>,
531 <&mcu_udmap 0xf007>,
532 <&mcu_udmap 0x7000>;
540 #size-cells = <0>;
546 ti,syscon-efuse = <&mcu_conf 0x200>;
553 reg = <0x00 0xf00 0x00 0x100>;
555 #size-cells = <0>;
556 clocks = <&k3_clks 63 0>;
563 reg = <0x00 0x3d000 0x00 0x400>;
580 ranges = <0x41000000 0x00 0x41000000 0x20000>,
581 <0x41400000 0x00 0x41400000 0x20000>;
586 reg = <0x41000000 0x00010000>,
587 <0x41010000 0x00010000>;
591 ti,sci-proc-ids = <0x01 0xff>;
601 reg = <0x41400000 0x00010000>,
602 <0x41410000 0x00010000>;
606 ti,sci-proc-ids = <0x02 0xff>;
617 reg = <0x00 0x42040000 0x00 0x350>,
618 <0x00 0x42050000 0x00 0x350>;
625 reg = <0x00 0x40200000 0x00 0x1000>;
627 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
628 clocks = <&k3_clks 0 0>;
629 assigned-clocks = <&k3_clks 0 2>;
632 dmas = <&main_udmap 0x7400>,
633 <&main_udmap 0x7401>;
645 reg = <0x00 0x40210000 0x00 0x1000>;
648 clocks = <&k3_clks 1 0>;
652 dmas = <&main_udmap 0x7402>,
653 <&main_udmap 0x7403>;
665 reg = <0x00 0x47000000 0x00 0x100>;
672 reg = <0x00 0x47040000 0x00 0x100>,
673 <0x05 0x0000000 0x01 0x0000000>;
677 cdns,trigger-address = <0x0>;
684 #size-cells = <0>;
690 reg = <0x00 0x47050000 0x00 0x100>,
691 <0x07 0x0000000 0x01 0x0000000>;
695 cdns,trigger-address = <0x0>;
699 #size-cells = <0>;