dts/ti/k3-j784s4-evm.dts

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "k3-j784s4.dtsi"
15 	compatible = "ti,j784s4-evm", "ti,j784s4";
19 		stdout-path = "serial2:115200n8";
39 	reserved_memory: reserved-memory {
40 		#address-cells = <2>;
41 		#size-cells = <2>;
46 			no-map;
49 		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
50 			compatible = "shared-dma-pool";
52 			no-map;
55 		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
56 			compatible = "shared-dma-pool";
58 			no-map;
61 		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
62 			compatible = "shared-dma-pool";
64 			no-map;
67 		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
68 			compatible = "shared-dma-pool";
70 			no-map;
73 		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
74 			compatible = "shared-dma-pool";
76 			no-map;
79 		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
80 			compatible = "shared-dma-pool";
82 			no-map;
85 		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
86 			compatible = "shared-dma-pool";
88 			no-map;
91 		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
92 			compatible = "shared-dma-pool";
94 			no-map;
97 		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
98 			compatible = "shared-dma-pool";
100 			no-map;
103 		main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
104 			compatible = "shared-dma-pool";
106 			no-map;
109 		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
110 			compatible = "shared-dma-pool";
112 			no-map;
115 		main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
116 			compatible = "shared-dma-pool";
118 			no-map;
121 		main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
122 			compatible = "shared-dma-pool";
124 			no-map;
127 		main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
128 			compatible = "shared-dma-pool";
130 			no-map;
133 		main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
134 			compatible = "shared-dma-pool";
136 			no-map;
139 		main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
140 			compatible = "shared-dma-pool";
142 			no-map;
145 		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
146 			compatible = "shared-dma-pool";
148 			no-map;
151 		c71_0_memory_region: c71-memory@a8100000 {
152 			compatible = "shared-dma-pool";
154 			no-map;
157 		c71_1_dma_memory_region: c71-dma-memory@a9000000 {
158 			compatible = "shared-dma-pool";
160 			no-map;
163 		c71_1_memory_region: c71-memory@a9100000 {
164 			compatible = "shared-dma-pool";
166 			no-map;
169 		c71_2_dma_memory_region: c71-dma-memory@aa000000 {
170 			compatible = "shared-dma-pool";
172 			no-map;
175 		c71_2_memory_region: c71-memory@aa100000 {
176 			compatible = "shared-dma-pool";
178 			no-map;
181 		c71_3_dma_memory_region: c71-dma-memory@ab000000 {
182 			compatible = "shared-dma-pool";
184 			no-map;
187 		c71_3_memory_region: c71-memory@ab100000 {
188 			compatible = "shared-dma-pool";
190 			no-map;
194 	evm_12v0: regulator-evm12v0 {
196 		compatible = "regulator-fixed";
197 		regulator-name = "evm_12v0";
198 		regulator-min-microvolt = <12000000>;
199 		regulator-max-microvolt = <12000000>;
200 		regulator-always-on;
201 		regulator-boot-on;
204 	vsys_3v3: regulator-vsys3v3 {
206 		compatible = "regulator-fixed";
207 		regulator-name = "vsys_3v3";
208 		regulator-min-microvolt = <3300000>;
209 		regulator-max-microvolt = <3300000>;
210 		vin-supply = <&evm_12v0>;
211 		regulator-always-on;
212 		regulator-boot-on;
215 	vsys_5v0: regulator-vsys5v0 {
217 		compatible = "regulator-fixed";
218 		regulator-name = "vsys_5v0";
219 		regulator-min-microvolt = <5000000>;
220 		regulator-max-microvolt = <5000000>;
221 		vin-supply = <&evm_12v0>;
222 		regulator-always-on;
223 		regulator-boot-on;
226 	vdd_mmc1: regulator-sd {
228 		compatible = "regulator-fixed";
229 		regulator-name = "vdd_mmc1";
230 		regulator-min-microvolt = <3300000>;
231 		regulator-max-microvolt = <3300000>;
232 		regulator-boot-on;
233 		enable-active-high;
234 		vin-supply = <&vsys_3v3>;
238 	vdd_sd_dv: regulator-TLV71033 {
240 		compatible = "regulator-gpio";
241 		regulator-name = "tlv71033";
242 		pinctrl-names = "default";
243 		pinctrl-0 = <&vdd_sd_dv_pins_default>;
244 		regulator-min-microvolt = <1800000>;
245 		regulator-max-microvolt = <3300000>;
246 		regulator-boot-on;
247 		vin-supply = <&vsys_5v0>;
255 	bootph-all;
256 	main_uart8_pins_default: main-uart8-default-pins {
257 		bootph-all;
258 		pinctrl-single,pins = <
266 	main_i2c0_pins_default: main-i2c0-default-pins {
267 		pinctrl-single,pins = <
273 	main_mmc1_pins_default: main-mmc1-default-pins {
274 		bootph-all;
275 		pinctrl-single,pins = <
287 	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
288 		pinctrl-single,pins = <
295 	bootph-all;
296 	wkup_uart0_pins_default: wkup-uart0-default-pins {
297 		bootph-all;
298 		pinctrl-single,pins = <
304 	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
305 		bootph-all;
306 		pinctrl-single,pins = <
312 	mcu_uart0_pins_default: mcu-uart0-default-pins {
313 		bootph-all;
314 		pinctrl-single,pins = <
322 	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
323 		pinctrl-single,pins = <
339 	mcu_mdio_pins_default: mcu-mdio-default-pins {
340 		pinctrl-single,pins = <
346 	mcu_adc0_pins_default: mcu-adc0-default-pins {
347 		pinctrl-single,pins = <
359 	mcu_adc1_pins_default: mcu-adc1-default-pins {
360 		pinctrl-single,pins = <
374 	bootph-all;
375 	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
376 		bootph-all;
377 		pinctrl-single,pins = <
394 	bootph-all;
395 	mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins {
396 		bootph-all;
397 		pinctrl-single,pins = <
403 	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
404 		bootph-all;
405 		pinctrl-single,pins = <
421 	pinctrl-names = "default";
422 	pinctrl-0 = <&wkup_uart0_pins_default>;
426 	bootph-all;
428 	pinctrl-names = "default";
429 	pinctrl-0 = <&wkup_i2c0_pins_default>;
430 	clock-frequency = <400000>;
433 		/* CAV24C256WE-GT3 */
440 	bootph-all;
442 	pinctrl-names = "default";
443 	pinctrl-0 = <&mcu_uart0_pins_default>;
447 	bootph-all;
449 	pinctrl-names = "default";
450 	pinctrl-0 = <&main_uart8_pins_default>;
458 	bootph-all;
463 	bootph-all;
465 	pinctrl-names = "default";
466 	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>;
469 		bootph-all;
470 		compatible = "jedec,spi-nor";
472 		spi-tx-bus-width = <8>;
473 		spi-rx-bus-width = <8>;
474 		spi-max-frequency = <25000000>;
475 		cdns,tshsl-ns = <60>;
476 		cdns,tsd2d-ns = <60>;
477 		cdns,tchsh-ns = <60>;
478 		cdns,tslch-ns = <60>;
479 		cdns,read-delay = <4>;
482 			compatible = "fixed-partitions";
483 			#address-cells = <1>;
484 			#size-cells = <1>;
497 				label = "ospi.u-boot";
517 				bootph-all;
526 	bootph-all;
528 	pinctrl-names = "default";
529 	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
532 		bootph-all;
533 		compatible = "jedec,spi-nor";
535 		spi-tx-bus-width = <1>;
536 		spi-rx-bus-width = <4>;
537 		spi-max-frequency = <40000000>;
538 		cdns,tshsl-ns = <60>;
539 		cdns,tsd2d-ns = <60>;
540 		cdns,tchsh-ns = <60>;
541 		cdns,tslch-ns = <60>;
542 		cdns,read-delay = <2>;
545 			compatible = "fixed-partitions";
546 			#address-cells = <1>;
547 			#size-cells = <1>;
560 				label = "qspi.u-boot";
580 				bootph-all;
591 	pinctrl-names = "default";
592 	pinctrl-0 = <&main_i2c0_pins_default>;
594 	clock-frequency = <400000>;
599 		gpio-controller;
600 		#gpio-cells = <2>;
601 		gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ",
611 		gpio-controller;
612 		#gpio-cells = <2>;
613 		gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN",
625 	bootph-all;
628 	non-removable;
629 	ti,driver-strength-ohm = <50>;
630 	disable-wp;
634 	bootph-all;
637 	pinctrl-0 = <&main_mmc1_pins_default>;
638 	pinctrl-names = "default";
639 	disable-wp;
640 	vmmc-supply = <&vdd_mmc1>;
641 	vqmmc-supply = <&vdd_sd_dv>;
650 	pinctrl-names = "default";
651 	pinctrl-0 = <&mcu_cpsw_pins_default>;
655 	pinctrl-names = "default";
656 	pinctrl-0 = <&mcu_mdio_pins_default>;
658 	mcu_phy0: ethernet-phy@0 {
660 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
661 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
662 		ti,min-output-impedance;
668 	phy-mode = "rgmii-rxid";
669 	phy-handle = <&mcu_phy0>;
676 	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
677 		ti,mbox-rx = <0 0 0>;
678 		ti,mbox-tx = <1 0 0>;
681 	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
682 		ti,mbox-rx = <2 0 0>;
683 		ti,mbox-tx = <3 0 0>;
691 	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
692 		ti,mbox-rx = <0 0 0>;
693 		ti,mbox-tx = <1 0 0>;
696 	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
697 		ti,mbox-rx = <2 0 0>;
698 		ti,mbox-tx = <3 0 0>;
706 	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
707 		ti,mbox-rx = <0 0 0>;
708 		ti,mbox-tx = <1 0 0>;
711 	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
712 		ti,mbox-rx = <2 0 0>;
713 		ti,mbox-tx = <3 0 0>;
721 	mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
722 		ti,mbox-rx = <0 0 0>;
723 		ti,mbox-tx = <1 0 0>;
726 	mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
727 		ti,mbox-rx = <2 0 0>;
728 		ti,mbox-tx = <3 0 0>;
736 	mbox_c71_0: mbox-c71-0 {
737 		ti,mbox-rx = <0 0 0>;
738 		ti,mbox-tx = <1 0 0>;
741 	mbox_c71_1: mbox-c71-1 {
742 		ti,mbox-rx = <2 0 0>;
743 		ti,mbox-tx = <3 0 0>;
751 	mbox_c71_2: mbox-c71-2 {
752 		ti,mbox-rx = <0 0 0>;
753 		ti,mbox-tx = <1 0 0>;
756 	mbox_c71_3: mbox-c71-3 {
757 		ti,mbox-rx = <2 0 0>;
758 		ti,mbox-tx = <3 0 0>;
765 	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
772 	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
779 	memory-region = <&main_r5fss0_core0_dma_memory_region>,
786 	memory-region = <&main_r5fss0_core1_dma_memory_region>,
793 	memory-region = <&main_r5fss1_core0_dma_memory_region>,
800 	memory-region = <&main_r5fss1_core1_dma_memory_region>,
807 	memory-region = <&main_r5fss2_core0_dma_memory_region>,
814 	memory-region = <&main_r5fss2_core1_dma_memory_region>,
821 	memory-region = <&c71_0_dma_memory_region>,
828 	memory-region = <&c71_1_dma_memory_region>,
835 	memory-region = <&c71_2_dma_memory_region>,
842 	memory-region = <&c71_3_dma_memory_region>,
847 	pinctrl-0 = <&mcu_adc0_pins_default>;
848 	pinctrl-names = "default";
851 		ti,adc-channels = <0 1 2 3 4 5 6 7>;
856 	pinctrl-0 = <&mcu_adc1_pins_default>;
857 	pinctrl-names = "default";
860 		ti,adc-channels = <0 1 2 3 4 5 6 7>;