dts/ti/k3-j721s2-mcu-wakeup.dtsi

1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
9 	sms: system-controller@44083000 {
10 		compatible = "ti,k2g-sci";
11 		ti,host-id = <12>;
13 		mbox-names = "rx", "tx";
18 		reg-names = "debug_messages";
21 		k3_pds: power-controller {
22 			compatible = "ti,sci-pm-domain";
23 			#power-domain-cells = <2>;
26 		k3_clks: clock-controller {
27 			compatible = "ti,k2g-sci-clk";
28 			#clock-cells = <2>;
31 		k3_reset: reset-controller {
32 			compatible = "ti,sci-reset";
33 			#reset-cells = <2>;
38 		compatible = "ti,am654-chipid";
43 		compatible = "ti,am654-secure-proxy";
44 		#mbox-cells = <1>;
45 		reg-names = "target_data", "rt", "scfg";
52 		 * firmware on non-MPU processors
58 		compatible = "mmio-sram";
61 		#address-cells = <1>;
62 		#size-cells = <1>;
66 		compatible = "pinctrl-single";
67 		/* Proxy 0 addressing */
69 		#pinctrl-cells = <1>;
70 		pinctrl-single,register-width = <32>;
71 		pinctrl-single,function-mask = <0xffffffff>;
75 		compatible = "pinctrl-single";
76 		/* Proxy 0 addressing */
78 		#pinctrl-cells = <1>;
79 		pinctrl-single,register-width = <32>;
80 		pinctrl-single,function-mask = <0xffffffff>;
84 		compatible = "pinctrl-single";
85 		/* Proxy 0 addressing */
87 		#pinctrl-cells = <1>;
88 		pinctrl-single,register-width = <32>;
89 		pinctrl-single,function-mask = <0xffffffff>;
93 		compatible = "pinctrl-single";
94 		/* Proxy 0 addressing */
96 		#pinctrl-cells = <1>;
97 		pinctrl-single,register-width = <32>;
98 		pinctrl-single,function-mask = <0xffffffff>;
103 		compatible = "pinctrl-single";
105 		#pinctrl-cells = <1>;
106 		pinctrl-single,register-width = <32>;
107 		pinctrl-single,function-mask = <0x0000000f>;
108 		/* Non-MPU Firmware usage */
114 		compatible = "pinctrl-single";
116 		#pinctrl-cells = <1>;
117 		pinctrl-single,register-width = <32>;
118 		pinctrl-single,function-mask = <0x0000000f>;
119 		/* Non-MPU Firmware usage */
123 	wkup_gpio_intr: interrupt-controller@42200000 {
124 		compatible = "ti,sci-intr";
126 		ti,intr-trigger-type = <1>;
127 		interrupt-controller;
128 		interrupt-parent = <&gic500>;
129 		#interrupt-cells = <1>;
131 		ti,sci-dev-id = <125>;
132 		ti,interrupt-ranges = <16 960 16>;
136 		compatible = "syscon", "simple-mfd";
138 		#address-cells = <1>;
139 		#size-cells = <1>;
143 			compatible = "ti,am654-phy-gmii-sel";
145 			#phy-cells = <1>;
151 		compatible = "ti,am654-timer";
155 		clock-names = "fck";
156 		assigned-clocks = <&k3_clks 35 1>;
157 		assigned-clock-parents = <&k3_clks 35 2>;
158 		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
159 		ti,timer-pwm;
160 		/* Non-MPU Firmware usage */
165 		compatible = "ti,am654-timer";
169 		clock-names = "fck";
170 		assigned-clocks = <&k3_clks 83 1>;
171 		assigned-clock-parents = <&k3_clks 83 2>;
172 		power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
173 		ti,timer-pwm;
174 		/* Non-MPU Firmware usage */
179 		compatible = "ti,am654-timer";
183 		clock-names = "fck";
184 		assigned-clocks = <&k3_clks 84 1>;
185 		assigned-clock-parents = <&k3_clks 84 2>;
186 		power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
187 		ti,timer-pwm;
188 		/* Non-MPU Firmware usage */
193 		compatible = "ti,am654-timer";
197 		clock-names = "fck";
198 		assigned-clocks = <&k3_clks 85 1>;
199 		assigned-clock-parents = <&k3_clks 85 2>;
200 		power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
201 		ti,timer-pwm;
202 		/* Non-MPU Firmware usage */
207 		compatible = "ti,am654-timer";
211 		clock-names = "fck";
212 		assigned-clocks = <&k3_clks 86 1>;
213 		assigned-clock-parents = <&k3_clks 86 2>;
214 		power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
215 		ti,timer-pwm;
216 		/* Non-MPU Firmware usage */
221 		compatible = "ti,am654-timer";
225 		clock-names = "fck";
226 		assigned-clocks = <&k3_clks 87 1>;
227 		assigned-clock-parents = <&k3_clks 87 2>;
228 		power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
229 		ti,timer-pwm;
230 		/* Non-MPU Firmware usage */
235 		compatible = "ti,am654-timer";
239 		clock-names = "fck";
240 		assigned-clocks = <&k3_clks 88 1>;
241 		assigned-clock-parents = <&k3_clks 88 2>;
242 		power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
243 		ti,timer-pwm;
244 		/* Non-MPU Firmware usage */
249 		compatible = "ti,am654-timer";
253 		clock-names = "fck";
254 		assigned-clocks = <&k3_clks 89 1>;
255 		assigned-clock-parents = <&k3_clks 89 2>;
256 		power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
257 		ti,timer-pwm;
258 		/* Non-MPU Firmware usage */
263 		compatible = "ti,am654-timer";
267 		clock-names = "fck";
268 		assigned-clocks = <&k3_clks 90 1>;
269 		assigned-clock-parents = <&k3_clks 90 2>;
270 		power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
271 		ti,timer-pwm;
272 		/* Non-MPU Firmware usage */
277 		compatible = "ti,am654-timer";
281 		clock-names = "fck";
282 		assigned-clocks = <&k3_clks 91 1>;
283 		assigned-clock-parents = <&k3_clks 91 2>;
284 		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
285 		ti,timer-pwm;
286 		/* Non-MPU Firmware usage */
291 		compatible = "ti,j721e-uart", "ti,am654-uart";
294 		current-speed = <115200>;
296 		clock-names = "fclk";
297 		power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
302 		compatible = "ti,j721e-uart", "ti,am654-uart";
305 		current-speed = <115200>;
307 		clock-names = "fclk";
308 		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
313 		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
315 		gpio-controller;
316 		#gpio-cells = <2>;
317 		interrupt-parent = <&wkup_gpio_intr>;
319 		interrupt-controller;
320 		#interrupt-cells = <2>;
322 		ti,davinci-gpio-unbanked = <0>;
323 		power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
325 		clock-names = "gpio";
330 		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
332 		gpio-controller;
333 		#gpio-cells = <2>;
334 		interrupt-parent = <&wkup_gpio_intr>;
336 		interrupt-controller;
337 		#interrupt-cells = <2>;
339 		ti,davinci-gpio-unbanked = <0>;
340 		power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
342 		clock-names = "gpio";
347 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
350 		#address-cells = <1>;
351 		#size-cells = <0>;
353 		clock-names = "fck";
354 		power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
359 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
362 		#address-cells = <1>;
363 		#size-cells = <0>;
365 		clock-names = "fck";
366 		power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
371 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
374 		#address-cells = <1>;
375 		#size-cells = <0>;
377 		clock-names = "fck";
378 		power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
386 		reg-names = "m_can", "message_ram";
387 		power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
389 		clock-names = "hclk", "cclk";
392 		interrupt-names = "int0", "int1";
393 		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
401 		reg-names = "m_can", "message_ram";
402 		power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
404 		clock-names = "hclk", "cclk";
407 		interrupt-names = "int0", "int1";
408 		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
413 		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
416 		#address-cells = <1>;
417 		#size-cells = <0>;
418 		power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>;
424 		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
427 		#address-cells = <1>;
428 		#size-cells = <0>;
429 		power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
435 		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
438 		#address-cells = <1>;
439 		#size-cells = <0>;
440 		power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
446 		compatible = "simple-mfd";
447 		#address-cells = <2>;
448 		#size-cells = <2>;
450 		dma-coherent;
451 		dma-ranges;
453 		ti,sci-dev-id = <267>;
456 			compatible = "ti,am654-navss-ringacc";
462 			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
463 			ti,num-rings = <286>;
464 			ti,sci-rm-range-gp-rings = <0x1>;
466 			ti,sci-dev-id = <272>;
467 			msi-parent = <&main_udmass_inta>;
470 		mcu_udmap: dma-controller@285c0000 {
471 			compatible = "ti,j721e-navss-mcu-udmap";
475 			reg-names = "gcfg", "rchanrt", "tchanrt";
476 			msi-parent = <&main_udmass_inta>;
477 			#dma-cells = <1>;
480 			ti,sci-dev-id = <273>;
482 			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
484 			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
486 			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
491 		compatible = "ti,am654-secure-proxy";
492 		#mbox-cells = <1>;
493 		reg-names = "target_data", "rt", "scfg";
500 		 * firmware on non-MPU processors
506 		compatible = "ti,j721e-cpsw-nuss";
507 		#address-cells = <2>;
508 		#size-cells = <2>;
510 		reg-names = "cpsw_nuss";
512 		dma-coherent;
514 		clock-names = "fck";
515 		power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
526 		dma-names = "tx0", "tx1", "tx2", "tx3",
530 		ethernet-ports {
531 			#address-cells = <1>;
532 			#size-cells = <0>;
536 				ti,mac-only;
538 				ti,syscon-efuse = <&mcu_conf 0x200>;
544 			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
546 			#address-cells = <1>;
547 			#size-cells = <0>;
549 			clock-names = "fck";
554 			compatible = "ti,am65-cpts";
557 			clock-names = "cpts";
558 			assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
559 			assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
560 			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
561 			interrupt-names = "cpts";
562 			ti,cpts-ext-ts-inputs = <4>;
563 			ti,cpts-periodic-outputs = <2>;
568 		compatible = "ti,am3359-tscadc";
571 		power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
573 		assigned-clocks = <&k3_clks 0 2>;
574 		assigned-clock-rates = <60000000>;
575 		clock-names = "fck";
578 		dma-names = "fifo0", "fifo1";
582 			#io-channel-cells = <1>;
583 			compatible = "ti,am3359-adc";
588 		compatible = "ti,am3359-tscadc";
591 		power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
593 		assigned-clocks = <&k3_clks 1 2>;
594 		assigned-clock-rates = <60000000>;
595 		clock-names = "fck";
598 		dma-names = "fifo0", "fifo1";
602 			#io-channel-cells = <1>;
603 			compatible = "ti,am3359-adc";
608 		compatible = "simple-bus";
609 		#address-cells = <2>;
610 		#size-cells = <2>;
616 			compatible = "ti,am654-ospi", "cdns,qspi-nor";
620 			cdns,fifo-depth = <256>;
621 			cdns,fifo-width = <4>;
622 			cdns,trigger-address = <0x0>;
624 			assigned-clocks = <&k3_clks 109 5>;
625 			assigned-clock-parents = <&k3_clks 109 7>;
626 			assigned-clock-rates = <166666666>;
627 			power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
628 			#address-cells = <1>;
629 			#size-cells = <0>;
635 			compatible = "ti,am654-ospi", "cdns,qspi-nor";
639 			cdns,fifo-depth = <256>;
640 			cdns,fifo-width = <4>;
641 			cdns,trigger-address = <0x0>;
643 			power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
644 			#address-cells = <1>;
645 			#size-cells = <0>;
651 	wkup_vtm0: temperature-sensor@42040000 {
652 		compatible = "ti,j7200-vtm";
655 		power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>;
656 		#thermal-sensor-cells = <1>;