Lines Matching +full:0 +full:x42050000
19 reg = <0x00 0x44083000 0x00 0x1000>;
39 reg = <0x00 0x43000014 0x00 0x4>;
46 reg = <0x00 0x43600000 0x00 0x10000>,
47 <0x00 0x44880000 0x00 0x20000>,
48 <0x00 0x44860000 0x00 0x20000>;
59 reg = <0x00 0x41c00000 0x00 0x100000>;
60 ranges = <0x00 0x00 0x41c00000 0x100000>;
67 /* Proxy 0 addressing */
68 reg = <0x00 0x4301c000 0x00 0x034>;
71 pinctrl-single,function-mask = <0xffffffff>;
76 /* Proxy 0 addressing */
77 reg = <0x00 0x4301c038 0x00 0x02C>;
80 pinctrl-single,function-mask = <0xffffffff>;
85 /* Proxy 0 addressing */
86 reg = <0x00 0x4301c068 0x00 0x120>;
89 pinctrl-single,function-mask = <0xffffffff>;
94 /* Proxy 0 addressing */
95 reg = <0x00 0x4301c190 0x00 0x004>;
98 pinctrl-single,function-mask = <0xffffffff>;
104 reg = <0x00 0x40f04200 0x00 0x28>;
107 pinctrl-single,function-mask = <0x0000000f>;
115 reg = <0x00 0x40f04280 0x00 0x28>;
118 pinctrl-single,function-mask = <0x0000000f>;
125 reg = <0x00 0x42200000 0x00 0x400>;
137 reg = <0x0 0x40f00000 0x0 0x20000>;
140 ranges = <0x0 0x0 0x40f00000 0x20000>;
144 reg = <0x4040 0x4>;
152 reg = <0x00 0x40400000 0x00 0x400>;
166 reg = <0x00 0x40410000 0x00 0x400>;
180 reg = <0x00 0x40420000 0x00 0x400>;
194 reg = <0x00 0x40430000 0x00 0x400>;
208 reg = <0x00 0x40440000 0x00 0x400>;
222 reg = <0x00 0x40450000 0x00 0x400>;
236 reg = <0x00 0x40460000 0x00 0x400>;
250 reg = <0x00 0x40470000 0x00 0x400>;
264 reg = <0x00 0x40480000 0x00 0x400>;
278 reg = <0x00 0x40490000 0x00 0x400>;
292 reg = <0x00 0x42300000 0x00 0x200>;
303 reg = <0x00 0x40a00000 0x00 0x200>;
314 reg = <0x00 0x42110000 0x00 0x100>;
322 ti,davinci-gpio-unbanked = <0>;
324 clocks = <&k3_clks 115 0>;
331 reg = <0x00 0x42100000 0x00 0x100>;
339 ti,davinci-gpio-unbanked = <0>;
341 clocks = <&k3_clks 116 0>;
348 reg = <0x00 0x42120000 0x00 0x100>;
351 #size-cells = <0>;
360 reg = <0x00 0x40b00000 0x00 0x100>;
363 #size-cells = <0>;
372 reg = <0x00 0x40b10000 0x00 0x100>;
375 #size-cells = <0>;
384 reg = <0x00 0x40528000 0x00 0x200>,
385 <0x00 0x40500000 0x00 0x8000>;
388 clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
393 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
399 reg = <0x00 0x40568000 0x00 0x200>,
400 <0x00 0x40540000 0x00 0x8000>;
403 clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
408 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
414 reg = <0x00 0x040300000 0x00 0x400>;
417 #size-cells = <0>;
425 reg = <0x00 0x040310000 0x00 0x400>;
428 #size-cells = <0>;
436 reg = <0x00 0x040320000 0x00 0x400>;
439 #size-cells = <0>;
449 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
457 reg = <0x0 0x2b800000 0x0 0x400000>,
458 <0x0 0x2b000000 0x0 0x400000>,
459 <0x0 0x28590000 0x0 0x100>,
460 <0x0 0x2a500000 0x0 0x40000>,
461 <0x0 0x28440000 0x0 0x40000>;
464 ti,sci-rm-range-gp-rings = <0x1>;
472 reg = <0x0 0x285c0000 0x0 0x100>,
473 <0x0 0x2a800000 0x0 0x40000>,
474 <0x0 0x2aa00000 0x0 0x40000>;
482 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
483 <0x0f>; /* TX_HCHAN */
484 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
485 <0x0b>; /* RX_HCHAN */
486 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
494 reg = <0x00 0x2a480000 0x00 0x80000>,
495 <0x00 0x2a380000 0x00 0x80000>,
496 <0x00 0x2a400000 0x00 0x80000>;
509 reg = <0x0 0x46000000 0x0 0x200000>;
511 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
517 dmas = <&mcu_udmap 0xf000>,
518 <&mcu_udmap 0xf001>,
519 <&mcu_udmap 0xf002>,
520 <&mcu_udmap 0xf003>,
521 <&mcu_udmap 0xf004>,
522 <&mcu_udmap 0xf005>,
523 <&mcu_udmap 0xf006>,
524 <&mcu_udmap 0xf007>,
525 <&mcu_udmap 0x7000>;
532 #size-cells = <0>;
538 ti,syscon-efuse = <&mcu_conf 0x200>;
545 reg = <0x0 0xf00 0x0 0x100>;
547 #size-cells = <0>;
555 reg = <0x0 0x3d000 0x0 0x400>;
569 reg = <0x00 0x40200000 0x00 0x1000>;
571 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
572 clocks = <&k3_clks 0 0>;
573 assigned-clocks = <&k3_clks 0 2>;
576 dmas = <&main_udmap 0x7400>,
577 <&main_udmap 0x7401>;
589 reg = <0x00 0x40210000 0x00 0x1000>;
592 clocks = <&k3_clks 1 0>;
596 dmas = <&main_udmap 0x7402>,
597 <&main_udmap 0x7403>;
611 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
612 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
613 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
617 reg = <0x00 0x47040000 0x00 0x100>,
618 <0x05 0x00000000 0x01 0x00000000>;
622 cdns,trigger-address = <0x0>;
629 #size-cells = <0>;
636 reg = <0x00 0x47050000 0x00 0x100>,
637 <0x07 0x00000000 0x01 0x00000000>;
641 cdns,trigger-address = <0x0>;
645 #size-cells = <0>;
653 reg = <0x00 0x42040000 0x0 0x350>,
654 <0x00 0x42050000 0x0 0x350>;