Lines Matching +full:am654 +full:- +full:cpsw +full:- +full:nuss
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
24 #size-cells = <1>;
27 atf-sram@0 {
31 tifs-sram@1f0000 {
35 l3cache-sram@200000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
43 #address-cells = <1>;
44 #size-cells = <1>;
47 usb_serdes_mux: mux-controller@0 {
48 compatible = "mmio-mux";
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
55 compatible = "ti,am654-phy-gmii-sel";
57 #phy-cells = <1>;
60 serdes_ln_ctrl: mux-controller@80 {
61 compatible = "mmio-mux";
63 #mux-control-cells = <1>;
64 mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
68 ehrpwm_tbclk: clock-controller@140 {
69 compatible = "ti,am654-ehrpwm-tbclk";
71 #clock-cells = <1>;
76 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
77 #pwm-cells = <3>;
79 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
81 clock-names = "tbclk", "fck";
86 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
87 #pwm-cells = <3>;
89 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
91 clock-names = "tbclk", "fck";
96 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
97 #pwm-cells = <3>;
99 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
101 clock-names = "tbclk", "fck";
106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
107 #pwm-cells = <3>;
109 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
111 clock-names = "tbclk", "fck";
116 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
117 #pwm-cells = <3>;
119 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
121 clock-names = "tbclk", "fck";
126 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
127 #pwm-cells = <3>;
129 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
131 clock-names = "tbclk", "fck";
135 gic500: interrupt-controller@1800000 {
136 compatible = "arm,gic-v3";
137 #address-cells = <2>;
138 #size-cells = <2>;
140 #interrupt-cells = <3>;
141 interrupt-controller;
151 gic_its: msi-controller@1820000 {
152 compatible = "arm,gic-v3-its";
154 socionext,synquacer-pre-its = <0x1000000 0x400000>;
155 msi-controller;
156 #msi-cells = <1>;
160 main_gpio_intr: interrupt-controller@a00000 {
161 compatible = "ti,sci-intr";
163 ti,intr-trigger-type = <1>;
164 interrupt-controller;
165 interrupt-parent = <&gic500>;
166 #interrupt-cells = <1>;
168 ti,sci-dev-id = <148>;
169 ti,interrupt-ranges = <8 392 56>;
173 compatible = "pinctrl-single";
176 #pinctrl-cells = <1>;
177 pinctrl-single,register-width = <32>;
178 pinctrl-single,function-mask = <0xffffffff>;
183 compatible = "pinctrl-single";
185 #pinctrl-cells = <1>;
186 pinctrl-single,register-width = <32>;
187 pinctrl-single,function-mask = <0x00000007>;
192 compatible = "pinctrl-single";
194 #pinctrl-cells = <1>;
195 pinctrl-single,register-width = <32>;
196 pinctrl-single,function-mask = <0x0000001f>;
200 compatible = "ti,j721e-sa2ul";
202 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
203 #address-cells = <2>;
204 #size-cells = <2>;
209 dma-names = "tx", "rx1", "rx2";
212 compatible = "inside-secure,safexcel-eip76";
219 compatible = "ti,am654-timer";
223 clock-names = "fck";
224 assigned-clocks = <&k3_clks 63 1>;
225 assigned-clock-parents = <&k3_clks 63 2>;
226 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
227 ti,timer-pwm;
231 compatible = "ti,am654-timer";
235 clock-names = "fck";
236 assigned-clocks = <&k3_clks 64 1>;
237 assigned-clock-parents = <&k3_clks 64 2>;
238 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
239 ti,timer-pwm;
243 compatible = "ti,am654-timer";
247 clock-names = "fck";
248 assigned-clocks = <&k3_clks 65 1>;
249 assigned-clock-parents = <&k3_clks 65 2>;
250 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
251 ti,timer-pwm;
255 compatible = "ti,am654-timer";
259 clock-names = "fck";
260 assigned-clocks = <&k3_clks 66 1>;
261 assigned-clock-parents = <&k3_clks 66 2>;
262 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
263 ti,timer-pwm;
267 compatible = "ti,am654-timer";
271 clock-names = "fck";
272 assigned-clocks = <&k3_clks 67 1>;
273 assigned-clock-parents = <&k3_clks 67 2>;
274 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
275 ti,timer-pwm;
279 compatible = "ti,am654-timer";
283 clock-names = "fck";
284 assigned-clocks = <&k3_clks 68 1>;
285 assigned-clock-parents = <&k3_clks 68 2>;
286 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
287 ti,timer-pwm;
291 compatible = "ti,am654-timer";
295 clock-names = "fck";
296 assigned-clocks = <&k3_clks 69 1>;
297 assigned-clock-parents = <&k3_clks 69 2>;
298 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
299 ti,timer-pwm;
303 compatible = "ti,am654-timer";
307 clock-names = "fck";
308 assigned-clocks = <&k3_clks 70 1>;
309 assigned-clock-parents = <&k3_clks 70 2>;
310 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
311 ti,timer-pwm;
315 compatible = "ti,am654-timer";
319 clock-names = "fck";
320 assigned-clocks = <&k3_clks 71 1>;
321 assigned-clock-parents = <&k3_clks 71 2>;
322 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
323 ti,timer-pwm;
327 compatible = "ti,am654-timer";
331 clock-names = "fck";
332 assigned-clocks = <&k3_clks 72 1>;
333 assigned-clock-parents = <&k3_clks 72 2>;
334 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
335 ti,timer-pwm;
339 compatible = "ti,am654-timer";
343 clock-names = "fck";
344 assigned-clocks = <&k3_clks 73 1>;
345 assigned-clock-parents = <&k3_clks 73 2>;
346 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
347 ti,timer-pwm;
351 compatible = "ti,am654-timer";
355 clock-names = "fck";
356 assigned-clocks = <&k3_clks 74 1>;
357 assigned-clock-parents = <&k3_clks 74 2>;
358 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
359 ti,timer-pwm;
363 compatible = "ti,am654-timer";
367 clock-names = "fck";
368 assigned-clocks = <&k3_clks 75 1>;
369 assigned-clock-parents = <&k3_clks 75 2>;
370 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
371 ti,timer-pwm;
375 compatible = "ti,am654-timer";
379 clock-names = "fck";
380 assigned-clocks = <&k3_clks 76 1>;
381 assigned-clock-parents = <&k3_clks 76 2>;
382 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
383 ti,timer-pwm;
387 compatible = "ti,am654-timer";
391 clock-names = "fck";
392 assigned-clocks = <&k3_clks 77 1>;
393 assigned-clock-parents = <&k3_clks 77 2>;
394 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
395 ti,timer-pwm;
399 compatible = "ti,am654-timer";
403 clock-names = "fck";
404 assigned-clocks = <&k3_clks 78 1>;
405 assigned-clock-parents = <&k3_clks 78 2>;
406 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
407 ti,timer-pwm;
411 compatible = "ti,am654-timer";
415 clock-names = "fck";
416 assigned-clocks = <&k3_clks 79 1>;
417 assigned-clock-parents = <&k3_clks 79 2>;
418 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
419 ti,timer-pwm;
423 compatible = "ti,am654-timer";
427 clock-names = "fck";
428 assigned-clocks = <&k3_clks 80 1>;
429 assigned-clock-parents = <&k3_clks 80 2>;
430 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
431 ti,timer-pwm;
435 compatible = "ti,am654-timer";
439 clock-names = "fck";
440 assigned-clocks = <&k3_clks 81 1>;
441 assigned-clock-parents = <&k3_clks 81 2>;
442 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
443 ti,timer-pwm;
447 compatible = "ti,am654-timer";
451 clock-names = "fck";
452 assigned-clocks = <&k3_clks 82 1>;
453 assigned-clock-parents = <&k3_clks 82 2>;
454 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
455 ti,timer-pwm;
459 compatible = "ti,j721e-uart", "ti,am654-uart";
462 current-speed = <115200>;
464 clock-names = "fclk";
465 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
470 compatible = "ti,j721e-uart", "ti,am654-uart";
473 current-speed = <115200>;
475 clock-names = "fclk";
476 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
481 compatible = "ti,j721e-uart", "ti,am654-uart";
484 current-speed = <115200>;
486 clock-names = "fclk";
487 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
492 compatible = "ti,j721e-uart", "ti,am654-uart";
495 current-speed = <115200>;
497 clock-names = "fclk";
498 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
503 compatible = "ti,j721e-uart", "ti,am654-uart";
506 current-speed = <115200>;
508 clock-names = "fclk";
509 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
514 compatible = "ti,j721e-uart", "ti,am654-uart";
517 current-speed = <115200>;
519 clock-names = "fclk";
520 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
525 compatible = "ti,j721e-uart", "ti,am654-uart";
528 current-speed = <115200>;
530 clock-names = "fclk";
531 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
536 compatible = "ti,j721e-uart", "ti,am654-uart";
539 current-speed = <115200>;
541 clock-names = "fclk";
542 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
547 compatible = "ti,j721e-uart", "ti,am654-uart";
550 current-speed = <115200>;
552 clock-names = "fclk";
553 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
558 compatible = "ti,j721e-uart", "ti,am654-uart";
561 current-speed = <115200>;
563 clock-names = "fclk";
564 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
569 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
571 gpio-controller;
572 #gpio-cells = <2>;
573 interrupt-parent = <&main_gpio_intr>;
575 interrupt-controller;
576 #interrupt-cells = <2>;
578 ti,davinci-gpio-unbanked = <0>;
579 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
581 clock-names = "gpio";
586 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
588 gpio-controller;
589 #gpio-cells = <2>;
590 interrupt-parent = <&main_gpio_intr>;
592 interrupt-controller;
593 #interrupt-cells = <2>;
595 ti,davinci-gpio-unbanked = <0>;
596 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
598 clock-names = "gpio";
603 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
605 gpio-controller;
606 #gpio-cells = <2>;
607 interrupt-parent = <&main_gpio_intr>;
609 interrupt-controller;
610 #interrupt-cells = <2>;
612 ti,davinci-gpio-unbanked = <0>;
613 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
615 clock-names = "gpio";
620 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
622 gpio-controller;
623 #gpio-cells = <2>;
624 interrupt-parent = <&main_gpio_intr>;
626 interrupt-controller;
627 #interrupt-cells = <2>;
629 ti,davinci-gpio-unbanked = <0>;
630 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
632 clock-names = "gpio";
637 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
640 #address-cells = <1>;
641 #size-cells = <0>;
643 clock-names = "fck";
644 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
648 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
651 #address-cells = <1>;
652 #size-cells = <0>;
654 clock-names = "fck";
655 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
660 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
663 #address-cells = <1>;
664 #size-cells = <0>;
666 clock-names = "fck";
667 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
672 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
675 #address-cells = <1>;
676 #size-cells = <0>;
678 clock-names = "fck";
679 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
684 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
687 #address-cells = <1>;
688 #size-cells = <0>;
690 clock-names = "fck";
691 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
696 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
699 #address-cells = <1>;
700 #size-cells = <0>;
702 clock-names = "fck";
703 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
708 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
711 #address-cells = <1>;
712 #size-cells = <0>;
714 clock-names = "fck";
715 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
720 compatible = "ti,j721e-sdhci-8bit";
724 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
726 clock-names = "clk_ahb", "clk_xin";
727 assigned-clocks = <&k3_clks 98 1>;
728 assigned-clock-parents = <&k3_clks 98 2>;
729 bus-width = <8>;
730 ti,otap-del-sel-legacy = <0x0>;
731 ti,otap-del-sel-mmc-hs = <0x0>;
732 ti,otap-del-sel-ddr52 = <0x6>;
733 ti,otap-del-sel-hs200 = <0x8>;
734 ti,otap-del-sel-hs400 = <0x5>;
735 ti,itap-del-sel-legacy = <0x10>;
736 ti,itap-del-sel-mmc-hs = <0xa>;
737 ti,strobe-sel = <0x77>;
738 ti,clkbuf-sel = <0x7>;
739 ti,trm-icp = <0x8>;
740 mmc-ddr-1_8v;
741 mmc-hs200-1_8v;
742 mmc-hs400-1_8v;
743 dma-coherent;
748 compatible = "ti,j721e-sdhci-4bit";
752 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
754 clock-names = "clk_ahb", "clk_xin";
755 assigned-clocks = <&k3_clks 99 1>;
756 assigned-clock-parents = <&k3_clks 99 2>;
757 bus-width = <4>;
758 ti,otap-del-sel-legacy = <0x0>;
759 ti,otap-del-sel-sd-hs = <0x0>;
760 ti,otap-del-sel-sdr12 = <0xf>;
761 ti,otap-del-sel-sdr25 = <0xf>;
762 ti,otap-del-sel-sdr50 = <0xc>;
763 ti,otap-del-sel-sdr104 = <0x5>;
764 ti,otap-del-sel-ddr50 = <0xc>;
765 ti,itap-del-sel-legacy = <0x0>;
766 ti,itap-del-sel-sd-hs = <0x0>;
767 ti,itap-del-sel-sdr12 = <0x0>;
768 ti,itap-del-sel-sdr25 = <0x0>;
769 ti,clkbuf-sel = <0x7>;
770 ti,trm-icp = <0x8>;
771 dma-coherent;
773 sdhci-caps-mask = <0x00000003 0x00000000>;
778 compatible = "simple-mfd";
779 #address-cells = <2>;
780 #size-cells = <2>;
782 ti,sci-dev-id = <224>;
783 dma-coherent;
784 dma-ranges;
786 main_navss_intr: interrupt-controller@310e0000 {
787 compatible = "ti,sci-intr";
789 ti,intr-trigger-type = <4>;
790 interrupt-controller;
791 interrupt-parent = <&gic500>;
792 #interrupt-cells = <1>;
794 ti,sci-dev-id = <227>;
795 ti,interrupt-ranges = <0 64 64>,
800 main_udmass_inta: msi-controller@33d00000 {
801 compatible = "ti,sci-inta";
803 interrupt-controller;
804 #interrupt-cells = <0>;
805 interrupt-parent = <&main_navss_intr>;
806 msi-controller;
808 ti,sci-dev-id = <265>;
809 ti,interrupt-ranges = <0 0 256>;
813 compatible = "ti,am654-secure-proxy";
814 #mbox-cells = <1>;
815 reg-names = "target_data", "rt", "scfg";
819 interrupt-names = "rx_011";
824 compatible = "ti,am654-hwspinlock";
826 #hwlock-cells = <1>;
830 compatible = "ti,am654-mailbox";
832 #mbox-cells = <1>;
833 ti,mbox-num-users = <4>;
834 ti,mbox-num-fifos = <16>;
835 interrupt-parent = <&main_navss_intr>;
840 compatible = "ti,am654-mailbox";
842 #mbox-cells = <1>;
843 ti,mbox-num-users = <4>;
844 ti,mbox-num-fifos = <16>;
845 interrupt-parent = <&main_navss_intr>;
850 compatible = "ti,am654-mailbox";
852 #mbox-cells = <1>;
853 ti,mbox-num-users = <4>;
854 ti,mbox-num-fifos = <16>;
855 interrupt-parent = <&main_navss_intr>;
860 compatible = "ti,am654-mailbox";
862 #mbox-cells = <1>;
863 ti,mbox-num-users = <4>;
864 ti,mbox-num-fifos = <16>;
865 interrupt-parent = <&main_navss_intr>;
870 compatible = "ti,am654-mailbox";
872 #mbox-cells = <1>;
873 ti,mbox-num-users = <4>;
874 ti,mbox-num-fifos = <16>;
875 interrupt-parent = <&main_navss_intr>;
880 compatible = "ti,am654-mailbox";
882 #mbox-cells = <1>;
883 ti,mbox-num-users = <4>;
884 ti,mbox-num-fifos = <16>;
885 interrupt-parent = <&main_navss_intr>;
890 compatible = "ti,am654-mailbox";
892 #mbox-cells = <1>;
893 ti,mbox-num-users = <4>;
894 ti,mbox-num-fifos = <16>;
895 interrupt-parent = <&main_navss_intr>;
900 compatible = "ti,am654-mailbox";
902 #mbox-cells = <1>;
903 ti,mbox-num-users = <4>;
904 ti,mbox-num-fifos = <16>;
905 interrupt-parent = <&main_navss_intr>;
910 compatible = "ti,am654-mailbox";
912 #mbox-cells = <1>;
913 ti,mbox-num-users = <4>;
914 ti,mbox-num-fifos = <16>;
915 interrupt-parent = <&main_navss_intr>;
920 compatible = "ti,am654-mailbox";
922 #mbox-cells = <1>;
923 ti,mbox-num-users = <4>;
924 ti,mbox-num-fifos = <16>;
925 interrupt-parent = <&main_navss_intr>;
930 compatible = "ti,am654-mailbox";
932 #mbox-cells = <1>;
933 ti,mbox-num-users = <4>;
934 ti,mbox-num-fifos = <16>;
935 interrupt-parent = <&main_navss_intr>;
940 compatible = "ti,am654-mailbox";
942 #mbox-cells = <1>;
943 ti,mbox-num-users = <4>;
944 ti,mbox-num-fifos = <16>;
945 interrupt-parent = <&main_navss_intr>;
950 compatible = "ti,am654-mailbox";
952 #mbox-cells = <1>;
953 ti,mbox-num-users = <4>;
954 ti,mbox-num-fifos = <16>;
955 interrupt-parent = <&main_navss_intr>;
960 compatible = "ti,am654-mailbox";
962 #mbox-cells = <1>;
963 ti,mbox-num-users = <4>;
964 ti,mbox-num-fifos = <16>;
965 interrupt-parent = <&main_navss_intr>;
970 compatible = "ti,am654-mailbox";
972 #mbox-cells = <1>;
973 ti,mbox-num-users = <4>;
974 ti,mbox-num-fifos = <16>;
975 interrupt-parent = <&main_navss_intr>;
980 compatible = "ti,am654-mailbox";
982 #mbox-cells = <1>;
983 ti,mbox-num-users = <4>;
984 ti,mbox-num-fifos = <16>;
985 interrupt-parent = <&main_navss_intr>;
990 compatible = "ti,am654-mailbox";
992 #mbox-cells = <1>;
993 ti,mbox-num-users = <4>;
994 ti,mbox-num-fifos = <16>;
995 interrupt-parent = <&main_navss_intr>;
1000 compatible = "ti,am654-mailbox";
1002 #mbox-cells = <1>;
1003 ti,mbox-num-users = <4>;
1004 ti,mbox-num-fifos = <16>;
1005 interrupt-parent = <&main_navss_intr>;
1010 compatible = "ti,am654-mailbox";
1012 #mbox-cells = <1>;
1013 ti,mbox-num-users = <4>;
1014 ti,mbox-num-fifos = <16>;
1015 interrupt-parent = <&main_navss_intr>;
1020 compatible = "ti,am654-mailbox";
1022 #mbox-cells = <1>;
1023 ti,mbox-num-users = <4>;
1024 ti,mbox-num-fifos = <16>;
1025 interrupt-parent = <&main_navss_intr>;
1030 compatible = "ti,am654-mailbox";
1032 #mbox-cells = <1>;
1033 ti,mbox-num-users = <4>;
1034 ti,mbox-num-fifos = <16>;
1035 interrupt-parent = <&main_navss_intr>;
1040 compatible = "ti,am654-mailbox";
1042 #mbox-cells = <1>;
1043 ti,mbox-num-users = <4>;
1044 ti,mbox-num-fifos = <16>;
1045 interrupt-parent = <&main_navss_intr>;
1050 compatible = "ti,am654-mailbox";
1052 #mbox-cells = <1>;
1053 ti,mbox-num-users = <4>;
1054 ti,mbox-num-fifos = <16>;
1055 interrupt-parent = <&main_navss_intr>;
1060 compatible = "ti,am654-mailbox";
1062 #mbox-cells = <1>;
1063 ti,mbox-num-users = <4>;
1064 ti,mbox-num-fifos = <16>;
1065 interrupt-parent = <&main_navss_intr>;
1070 compatible = "ti,am654-navss-ringacc";
1076 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
1077 ti,num-rings = <1024>;
1078 ti,sci-rm-range-gp-rings = <0x1>;
1080 ti,sci-dev-id = <259>;
1081 msi-parent = <&main_udmass_inta>;
1084 main_udmap: dma-controller@31150000 {
1085 compatible = "ti,j721e-navss-main-udmap";
1089 reg-names = "gcfg", "rchanrt", "tchanrt";
1090 msi-parent = <&main_udmass_inta>;
1091 #dma-cells = <1>;
1094 ti,sci-dev-id = <263>;
1097 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1100 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1103 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1107 compatible = "ti,j721e-cpts";
1109 reg-names = "cpts";
1111 clock-names = "cpts";
1112 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
1113 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
1114 interrupts-extended = <&main_navss_intr 391>;
1115 interrupt-names = "cpts";
1116 ti,cpts-periodic-outputs = <6>;
1117 ti,cpts-ext-ts-inputs = <8>;
1122 compatible = "ti,j721e-cpsw-nuss";
1124 reg-names = "cpsw_nuss";
1126 #address-cells = <2>;
1127 #size-cells = <2>;
1128 dma-coherent;
1130 clock-names = "fck";
1131 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
1142 dma-names = "tx0", "tx1", "tx2", "tx3",
1148 ethernet-ports {
1149 #address-cells = <1>;
1150 #size-cells = <0>;
1154 ti,mac-only;
1162 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1167 clock-names = "fck";
1173 compatible = "ti,am65-cpts";
1176 clock-names = "cpts";
1177 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1178 interrupt-names = "cpts";
1179 ti,cpts-ext-ts-inputs = <4>;
1180 ti,cpts-periodic-outputs = <2>;
1184 usbss0: cdns-usb@4104000 {
1185 compatible = "ti,j721e-usb";
1188 clock-names = "ref", "lpm";
1189 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
1190 assigned-clock-parents = <&k3_clks 360 17>;
1191 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
1192 #address-cells = <2>;
1193 #size-cells = <2>;
1195 dma-coherent;
1204 reg-names = "otg", "xhci", "dev";
1208 interrupt-names = "host", "peripheral", "otg";
1209 maximum-speed = "super-speed";
1215 compatible = "ti,j721s2-wiz-10g";
1216 #address-cells = <1>;
1217 #size-cells = <1>;
1218 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
1220 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1221 num-lanes = <4>;
1222 #reset-cells = <1>;
1223 #clock-cells = <1>;
1226 assigned-clocks = <&k3_clks 365 3>;
1227 assigned-clock-parents = <&k3_clks 365 7>;
1230 compatible = "ti,j721e-serdes-10g";
1232 reg-names = "torrent_phy";
1234 reset-names = "torrent_reset";
1237 clock-names = "refclk", "phy_en_refclk";
1238 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1241 assigned-clock-parents = <&k3_clks 365 3>,
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1246 #clock-cells = <1>;
1253 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
1258 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1259 interrupt-names = "link_state";
1262 ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
1263 max-link-speed = <3>;
1264 num-lanes = <4>;
1265 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
1267 clock-names = "fck";
1268 #address-cells = <3>;
1269 #size-cells = <2>;
1270 bus-range = <0x0 0xff>;
1271 vendor-id = <0x104c>;
1272 device-id = <0xb013>;
1273 msi-map = <0x0 &gic_its 0x0 0x10000>;
1274 dma-coherent;
1277 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1278 #interrupt-cells = <1>;
1279 interrupt-map-mask = <0 0 0 7>;
1280 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1287 pcie1_intc: interrupt-controller {
1288 interrupt-controller;
1289 #interrupt-cells = <1>;
1290 interrupt-parent = <&gic500>;
1299 reg-names = "m_can", "message_ram";
1300 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1302 clock-names = "hclk", "cclk";
1305 interrupt-names = "int0", "int1";
1306 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1314 reg-names = "m_can", "message_ram";
1315 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1317 clock-names = "hclk", "cclk";
1320 interrupt-names = "int0", "int1";
1321 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1329 reg-names = "m_can", "message_ram";
1330 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1332 clock-names = "hclk", "cclk";
1335 interrupt-names = "int0", "int1";
1336 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1344 reg-names = "m_can", "message_ram";
1345 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1347 clock-names = "hclk", "cclk";
1350 interrupt-names = "int0", "int1";
1351 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1359 reg-names = "m_can", "message_ram";
1360 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
1362 clock-names = "hclk", "cclk";
1365 interrupt-names = "int0", "int1";
1366 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1374 reg-names = "m_can", "message_ram";
1375 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
1377 clock-names = "hclk", "cclk";
1380 interrupt-names = "int0", "int1";
1381 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1389 reg-names = "m_can", "message_ram";
1390 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1392 clock-names = "hclk", "cclk";
1395 interrupt-names = "int0", "int1";
1396 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1404 reg-names = "m_can", "message_ram";
1405 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1407 clock-names = "hclk", "cclk";
1410 interrupt-names = "int0", "int1";
1411 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1419 reg-names = "m_can", "message_ram";
1420 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1422 clock-names = "hclk", "cclk";
1425 interrupt-names = "int0", "int1";
1426 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1434 reg-names = "m_can", "message_ram";
1435 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1437 clock-names = "hclk", "cclk";
1440 interrupt-names = "int0", "int1";
1441 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1449 reg-names = "m_can", "message_ram";
1450 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1452 clock-names = "hclk", "cclk";
1455 interrupt-names = "int0", "int1";
1456 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1464 reg-names = "m_can", "message_ram";
1465 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1467 clock-names = "hclk", "cclk";
1470 interrupt-names = "int0", "int1";
1471 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1479 reg-names = "m_can", "message_ram";
1480 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
1482 clock-names = "hclk", "cclk";
1485 interrupt-names = "int0", "int1";
1486 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1494 reg-names = "m_can", "message_ram";
1495 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
1497 clock-names = "hclk", "cclk";
1500 interrupt-names = "int0", "int1";
1501 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1509 reg-names = "m_can", "message_ram";
1510 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
1512 clock-names = "hclk", "cclk";
1515 interrupt-names = "int0", "int1";
1516 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1524 reg-names = "m_can", "message_ram";
1525 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
1527 clock-names = "hclk", "cclk";
1530 interrupt-names = "int0", "int1";
1531 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1539 reg-names = "m_can", "message_ram";
1540 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
1542 clock-names = "hclk", "cclk";
1545 interrupt-names = "int0", "int1";
1546 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1554 reg-names = "m_can", "message_ram";
1555 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
1557 clock-names = "hclk", "cclk";
1560 interrupt-names = "int0", "int1";
1561 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1566 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1571 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
1577 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1580 #address-cells = <1>;
1581 #size-cells = <0>;
1582 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
1588 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1593 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
1599 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1604 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
1610 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1615 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
1621 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1626 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
1632 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1635 #address-cells = <1>;
1636 #size-cells = <0>;
1637 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
1643 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1648 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
1654 compatible = "ti,j721e-dss";
1672 reg-names = "common_m", "common_s0",
1683 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1684 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
1689 interrupt-names = "common_m",