Lines Matching +full:0 +full:x04a90000
13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
32 reg = <0x1f0000 0x10000>;
36 reg = <0x200000 0x200000>;
42 reg = <0x00 0x00104000 0x00 0x18000>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
47 usb_serdes_mux: mux-controller@0 {
49 reg = <0x0 0x4>;
51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
56 reg = <0x34 0x4>;
62 reg = <0x80 0x10>;
64 mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
65 <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
70 reg = <0x140 0x18>;
78 reg = <0x00 0x3000000 0x00 0x100>;
80 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
88 reg = <0x00 0x3010000 0x00 0x100>;
90 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
98 reg = <0x00 0x3020000 0x00 0x100>;
100 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
108 reg = <0x00 0x3030000 0x00 0x100>;
110 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
118 reg = <0x00 0x3040000 0x00 0x100>;
120 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
128 reg = <0x00 0x3050000 0x00 0x100>;
130 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
142 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
143 <0x00 0x01900000 0x00 0x100000>, /* GICR */
144 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
145 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
146 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
153 reg = <0x00 0x01820000 0x00 0x10000>;
154 socionext,synquacer-pre-its = <0x1000000 0x400000>;
162 reg = <0x00 0x00a00000 0x00 0x800>;
174 /* Proxy 0 addressing */
175 reg = <0x0 0x11c000 0x0 0x120>;
178 pinctrl-single,function-mask = <0xffffffff>;
184 reg = <0x00 0x104200 0x00 0x50>;
187 pinctrl-single,function-mask = <0x00000007>;
193 reg = <0x00 0x104280 0x00 0x20>;
196 pinctrl-single,function-mask = <0x0000001f>;
201 reg = <0x00 0x04e00000 0x00 0x1200>;
205 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
207 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
208 <&main_udmap 0x4a41>;
213 reg = <0x00 0x04e10000 0x00 0x7d>;
220 reg = <0x00 0x2400000 0x00 0x400>;
232 reg = <0x00 0x2410000 0x00 0x400>;
244 reg = <0x00 0x2420000 0x00 0x400>;
256 reg = <0x00 0x2430000 0x00 0x400>;
268 reg = <0x00 0x2440000 0x00 0x400>;
280 reg = <0x00 0x2450000 0x00 0x400>;
292 reg = <0x00 0x2460000 0x00 0x400>;
304 reg = <0x00 0x2470000 0x00 0x400>;
316 reg = <0x00 0x2480000 0x00 0x400>;
328 reg = <0x00 0x2490000 0x00 0x400>;
340 reg = <0x00 0x24a0000 0x00 0x400>;
352 reg = <0x00 0x24b0000 0x00 0x400>;
364 reg = <0x00 0x24c0000 0x00 0x400>;
376 reg = <0x00 0x24d0000 0x00 0x400>;
388 reg = <0x00 0x24e0000 0x00 0x400>;
400 reg = <0x00 0x24f0000 0x00 0x400>;
412 reg = <0x00 0x2500000 0x00 0x400>;
424 reg = <0x00 0x2510000 0x00 0x400>;
436 reg = <0x00 0x2520000 0x00 0x400>;
448 reg = <0x00 0x2530000 0x00 0x400>;
460 reg = <0x00 0x02800000 0x00 0x200>;
471 reg = <0x00 0x02810000 0x00 0x200>;
482 reg = <0x00 0x02820000 0x00 0x200>;
493 reg = <0x00 0x02830000 0x00 0x200>;
504 reg = <0x00 0x02840000 0x00 0x200>;
515 reg = <0x00 0x02850000 0x00 0x200>;
526 reg = <0x00 0x02860000 0x00 0x200>;
537 reg = <0x00 0x02870000 0x00 0x200>;
548 reg = <0x00 0x02880000 0x00 0x200>;
559 reg = <0x00 0x02890000 0x00 0x200>;
570 reg = <0x00 0x00600000 0x00 0x100>;
578 ti,davinci-gpio-unbanked = <0>;
580 clocks = <&k3_clks 111 0>;
587 reg = <0x00 0x00610000 0x00 0x100>;
595 ti,davinci-gpio-unbanked = <0>;
597 clocks = <&k3_clks 112 0>;
604 reg = <0x00 0x00620000 0x00 0x100>;
612 ti,davinci-gpio-unbanked = <0>;
614 clocks = <&k3_clks 113 0>;
621 reg = <0x00 0x00630000 0x00 0x100>;
629 ti,davinci-gpio-unbanked = <0>;
631 clocks = <&k3_clks 114 0>;
638 reg = <0x00 0x02000000 0x00 0x100>;
641 #size-cells = <0>;
649 reg = <0x00 0x02010000 0x00 0x100>;
652 #size-cells = <0>;
661 reg = <0x00 0x02020000 0x00 0x100>;
664 #size-cells = <0>;
673 reg = <0x00 0x02030000 0x00 0x100>;
676 #size-cells = <0>;
685 reg = <0x00 0x02040000 0x00 0x100>;
688 #size-cells = <0>;
697 reg = <0x00 0x02050000 0x00 0x100>;
700 #size-cells = <0>;
709 reg = <0x00 0x02060000 0x00 0x100>;
712 #size-cells = <0>;
721 reg = <0x00 0x04f80000 0x00 0x1000>,
722 <0x00 0x04f88000 0x00 0x400>;
730 ti,otap-del-sel-legacy = <0x0>;
731 ti,otap-del-sel-mmc-hs = <0x0>;
732 ti,otap-del-sel-ddr52 = <0x6>;
733 ti,otap-del-sel-hs200 = <0x8>;
734 ti,otap-del-sel-hs400 = <0x5>;
735 ti,itap-del-sel-legacy = <0x10>;
736 ti,itap-del-sel-mmc-hs = <0xa>;
737 ti,strobe-sel = <0x77>;
738 ti,clkbuf-sel = <0x7>;
739 ti,trm-icp = <0x8>;
749 reg = <0x00 0x04fb0000 0x00 0x1000>,
750 <0x00 0x04fb8000 0x00 0x400>;
758 ti,otap-del-sel-legacy = <0x0>;
759 ti,otap-del-sel-sd-hs = <0x0>;
760 ti,otap-del-sel-sdr12 = <0xf>;
761 ti,otap-del-sel-sdr25 = <0xf>;
762 ti,otap-del-sel-sdr50 = <0xc>;
763 ti,otap-del-sel-sdr104 = <0x5>;
764 ti,otap-del-sel-ddr50 = <0xc>;
765 ti,itap-del-sel-legacy = <0x0>;
766 ti,itap-del-sel-sd-hs = <0x0>;
767 ti,itap-del-sel-sdr12 = <0x0>;
768 ti,itap-del-sel-sdr25 = <0x0>;
769 ti,clkbuf-sel = <0x7>;
770 ti,trm-icp = <0x8>;
773 sdhci-caps-mask = <0x00000003 0x00000000>;
781 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
788 reg = <0x00 0x310e0000 0x00 0x4000>;
795 ti,interrupt-ranges = <0 64 64>,
802 reg = <0x00 0x33d00000 0x00 0x100000>;
804 #interrupt-cells = <0>;
809 ti,interrupt-ranges = <0 0 256>;
816 reg = <0x00 0x32c00000 0x00 0x100000>,
817 <0x00 0x32400000 0x00 0x100000>,
818 <0x00 0x32800000 0x00 0x100000>;
825 reg = <0x00 0x30e00000 0x00 0x1000>;
831 reg = <0x00 0x31f80000 0x00 0x200>;
841 reg = <0x00 0x31f81000 0x00 0x200>;
851 reg = <0x00 0x31f82000 0x00 0x200>;
861 reg = <0x00 0x31f83000 0x00 0x200>;
871 reg = <0x00 0x31f84000 0x00 0x200>;
881 reg = <0x00 0x31f85000 0x00 0x200>;
891 reg = <0x00 0x31f86000 0x00 0x200>;
901 reg = <0x00 0x31f87000 0x00 0x200>;
911 reg = <0x00 0x31f88000 0x00 0x200>;
921 reg = <0x00 0x31f89000 0x00 0x200>;
931 reg = <0x00 0x31f8a000 0x00 0x200>;
941 reg = <0x00 0x31f8b000 0x00 0x200>;
951 reg = <0x00 0x31f90000 0x00 0x200>;
961 reg = <0x00 0x31f91000 0x00 0x200>;
971 reg = <0x00 0x31f92000 0x00 0x200>;
981 reg = <0x00 0x31f93000 0x00 0x200>;
991 reg = <0x00 0x31f94000 0x00 0x200>;
1001 reg = <0x00 0x31f95000 0x00 0x200>;
1011 reg = <0x00 0x31f96000 0x00 0x200>;
1021 reg = <0x00 0x31f97000 0x00 0x200>;
1031 reg = <0x00 0x31f98000 0x00 0x200>;
1041 reg = <0x00 0x31f99000 0x00 0x200>;
1051 reg = <0x00 0x31f9a000 0x00 0x200>;
1061 reg = <0x00 0x31f9b000 0x00 0x200>;
1071 reg = <0x0 0x3c000000 0x0 0x400000>,
1072 <0x0 0x38000000 0x0 0x400000>,
1073 <0x0 0x31120000 0x0 0x100>,
1074 <0x0 0x33000000 0x0 0x40000>,
1075 <0x0 0x31080000 0x0 0x40000>;
1078 ti,sci-rm-range-gp-rings = <0x1>;
1086 reg = <0x0 0x31150000 0x0 0x100>,
1087 <0x0 0x34000000 0x0 0x80000>,
1088 <0x0 0x35000000 0x0 0x200000>;
1097 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1098 <0x0f>, /* TX_HCHAN */
1099 <0x10>; /* TX_UHCHAN */
1100 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1101 <0x0b>, /* RX_HCHAN */
1102 <0x0c>; /* RX_UHCHAN */
1103 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1108 reg = <0x0 0x310d0000 0x0 0x400>;
1123 reg = <0x00 0xc200000 0x00 0x200000>;
1125 ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
1133 dmas = <&main_udmap 0xc640>,
1134 <&main_udmap 0xc641>,
1135 <&main_udmap 0xc642>,
1136 <&main_udmap 0xc643>,
1137 <&main_udmap 0xc644>,
1138 <&main_udmap 0xc645>,
1139 <&main_udmap 0xc646>,
1140 <&main_udmap 0xc647>,
1141 <&main_udmap 0x4640>;
1150 #size-cells = <0>;
1163 reg = <0x00 0xf00 0x00 0x100>;
1165 #size-cells = <0>;
1174 reg = <0x00 0x3d000 0x00 0x400>;
1186 reg = <0x00 0x04104000 0x00 0x100>;
1201 reg = <0x00 0x06000000 0x00 0x10000>,
1202 <0x00 0x06010000 0x00 0x10000>,
1203 <0x00 0x06020000 0x00 0x10000>;
1219 clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
1224 ranges = <0x5060000 0x0 0x5060000 0x10000>;
1231 reg = <0x05060000 0x00010000>;
1233 resets = <&serdes_wiz0 0>;
1245 #size-cells = <0>;
1254 reg = <0x00 0x02910000 0x00 0x1000>,
1255 <0x00 0x02917000 0x00 0x400>,
1256 <0x00 0x0d800000 0x00 0x800000>,
1257 <0x00 0x18000000 0x00 0x1000>;
1262 ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
1270 bus-range = <0x0 0xff>;
1271 vendor-id = <0x104c>;
1272 device-id = <0xb013>;
1273 msi-map = <0x0 &gic_its 0x0 0x10000>;
1275 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
1276 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
1277 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1279 interrupt-map-mask = <0 0 0 7>;
1280 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1281 <0 0 0 2 &pcie1_intc 0>, /* INT B */
1282 <0 0 0 3 &pcie1_intc 0>, /* INT C */
1283 <0 0 0 4 &pcie1_intc 0>; /* INT D */
1297 reg = <0x00 0x02701000 0x00 0x200>,
1298 <0x00 0x02708000 0x00 0x8000>;
1301 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
1306 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1312 reg = <0x00 0x02711000 0x00 0x200>,
1313 <0x00 0x02718000 0x00 0x8000>;
1316 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
1321 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1327 reg = <0x00 0x02721000 0x00 0x200>,
1328 <0x00 0x02728000 0x00 0x8000>;
1331 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
1336 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1342 reg = <0x00 0x02731000 0x00 0x200>,
1343 <0x00 0x02738000 0x00 0x8000>;
1346 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
1351 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1357 reg = <0x00 0x02741000 0x00 0x200>,
1358 <0x00 0x02748000 0x00 0x8000>;
1361 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
1366 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1372 reg = <0x00 0x02751000 0x00 0x200>,
1373 <0x00 0x02758000 0x00 0x8000>;
1376 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
1381 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1387 reg = <0x00 0x02761000 0x00 0x200>,
1388 <0x00 0x02768000 0x00 0x8000>;
1391 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
1396 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1402 reg = <0x00 0x02771000 0x00 0x200>,
1403 <0x00 0x02778000 0x00 0x8000>;
1406 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
1411 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1417 reg = <0x00 0x02781000 0x00 0x200>,
1418 <0x00 0x02788000 0x00 0x8000>;
1421 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
1426 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1432 reg = <0x00 0x02791000 0x00 0x200>,
1433 <0x00 0x02798000 0x00 0x8000>;
1436 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
1441 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1447 reg = <0x00 0x027a1000 0x00 0x200>,
1448 <0x00 0x027a8000 0x00 0x8000>;
1451 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
1456 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1462 reg = <0x00 0x027b1000 0x00 0x200>,
1463 <0x00 0x027b8000 0x00 0x8000>;
1466 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
1471 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1477 reg = <0x00 0x027c1000 0x00 0x200>,
1478 <0x00 0x027c8000 0x00 0x8000>;
1481 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
1486 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1492 reg = <0x00 0x027d1000 0x00 0x200>,
1493 <0x00 0x027d8000 0x00 0x8000>;
1496 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
1501 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1507 reg = <0x00 0x02681000 0x00 0x200>,
1508 <0x00 0x02688000 0x00 0x8000>;
1511 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
1516 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1522 reg = <0x00 0x02691000 0x00 0x200>,
1523 <0x00 0x02698000 0x00 0x8000>;
1526 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
1531 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1537 reg = <0x00 0x026a1000 0x00 0x200>,
1538 <0x00 0x026a8000 0x00 0x8000>;
1541 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
1546 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1552 reg = <0x00 0x026b1000 0x00 0x200>,
1553 <0x00 0x026b8000 0x00 0x8000>;
1556 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
1561 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1567 reg = <0x00 0x02100000 0x00 0x400>;
1570 #size-cells = <0>;
1578 reg = <0x00 0x02110000 0x00 0x400>;
1581 #size-cells = <0>;
1589 reg = <0x00 0x02120000 0x00 0x400>;
1592 #size-cells = <0>;
1600 reg = <0x00 0x02130000 0x00 0x400>;
1603 #size-cells = <0>;
1611 reg = <0x00 0x02140000 0x00 0x400>;
1614 #size-cells = <0>;
1622 reg = <0x00 0x02150000 0x00 0x400>;
1625 #size-cells = <0>;
1633 reg = <0x00 0x02160000 0x00 0x400>;
1636 #size-cells = <0>;
1644 reg = <0x00 0x02170000 0x00 0x400>;
1647 #size-cells = <0>;
1655 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1656 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1657 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1658 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1659 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1660 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1661 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1662 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1663 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1664 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1665 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1666 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1667 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1668 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1669 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1670 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1671 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1678 clocks = <&k3_clks 158 0>,