Lines Matching +full:dp +full:- +full:phy0
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
16 compatible = "ti,j721e-sk", "ti,j721e";
29 stdout-path = "serial2:115200n8";
39 reserved_memory: reserved-memory {
40 #address-cells = <2>;
41 #size-cells = <2>;
47 no-map;
50 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
51 compatible = "shared-dma-pool";
53 no-map;
56 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
57 compatible = "shared-dma-pool";
59 no-map;
62 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
63 compatible = "shared-dma-pool";
65 no-map;
68 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
69 compatible = "shared-dma-pool";
71 no-map;
74 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
75 compatible = "shared-dma-pool";
77 no-map;
80 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
81 compatible = "shared-dma-pool";
83 no-map;
86 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
87 compatible = "shared-dma-pool";
89 no-map;
92 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
93 compatible = "shared-dma-pool";
95 no-map;
98 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
99 compatible = "shared-dma-pool";
101 no-map;
104 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
105 compatible = "shared-dma-pool";
107 no-map;
110 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
111 compatible = "shared-dma-pool";
113 no-map;
116 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
117 compatible = "shared-dma-pool";
119 no-map;
122 c66_0_dma_memory_region: c66-dma-memory@a6000000 {
123 compatible = "shared-dma-pool";
125 no-map;
128 c66_0_memory_region: c66-memory@a6100000 {
129 compatible = "shared-dma-pool";
131 no-map;
134 c66_1_dma_memory_region: c66-dma-memory@a7000000 {
135 compatible = "shared-dma-pool";
137 no-map;
140 c66_1_memory_region: c66-memory@a7100000 {
141 compatible = "shared-dma-pool";
143 no-map;
146 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
147 compatible = "shared-dma-pool";
149 no-map;
152 c71_0_memory_region: c71-memory@a8100000 {
153 compatible = "shared-dma-pool";
155 no-map;
158 rtos_ipc_memory_region: ipc-memories@aa000000 {
161 no-map;
165 vusb_main: fixedregulator-vusb-main5v0 {
167 compatible = "regulator-fixed";
168 regulator-name = "vusb-main5v0";
169 regulator-min-microvolt = <5000000>;
170 regulator-max-microvolt = <5000000>;
171 regulator-always-on;
172 regulator-boot-on;
175 vsys_3v3: fixedregulator-vsys3v3 {
177 compatible = "regulator-fixed";
178 regulator-name = "vsys_3v3";
179 regulator-min-microvolt = <3300000>;
180 regulator-max-microvolt = <3300000>;
181 vin-supply = <&vusb_main>;
182 regulator-always-on;
183 regulator-boot-on;
186 vdd_mmc1: fixedregulator-sd {
187 compatible = "regulator-fixed";
188 pinctrl-names = "default";
189 pinctrl-0 = <&vdd_mmc1_en_pins_default>;
190 regulator-name = "vdd_mmc1";
191 regulator-min-microvolt = <3300000>;
192 regulator-max-microvolt = <3300000>;
193 regulator-boot-on;
194 enable-active-high;
195 vin-supply = <&vsys_3v3>;
199 vdd_sd_dv_alt: gpio-regulator-tps659411 {
200 compatible = "regulator-gpio";
201 pinctrl-names = "default";
202 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
203 regulator-name = "tps659411";
204 regulator-min-microvolt = <1800000>;
205 regulator-max-microvolt = <3300000>;
206 regulator-boot-on;
207 vin-supply = <&vsys_3v3>;
213 dp_pwr_3v3: fixedregulator-dp-prw {
214 compatible = "regulator-fixed";
215 regulator-name = "dp-pwr";
216 regulator-min-microvolt = <3300000>;
217 regulator-max-microvolt = <3300000>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&dp_pwr_en_pins_default>;
221 enable-active-high;
225 compatible = "dp-connector";
227 type = "full-size";
228 dp-pwr-supply = <&dp_pwr_3v3>;
232 remote-endpoint = <&dp0_out>;
237 hdmi-connector {
238 compatible = "hdmi-connector";
242 pinctrl-names = "default";
243 pinctrl-0 = <&hdmi_hpd_pins_default>;
245 ddc-i2c-bus = <&main_i2c1>;
248 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>;
252 remote-endpoint = <&tfp410_out>;
257 dvi-bridge {
260 pinctrl-names = "default";
261 pinctrl-0 = <&hdmi_pdn_pins_default>;
263 powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>;
267 #address-cells = <1>;
268 #size-cells = <0>;
274 remote-endpoint = <&dpi1_out>;
275 pclk-sample = <1>;
283 remote-endpoint =
292 main_mmc1_pins_default: main-mmc1-default-pins {
293 pinctrl-single,pins = <
305 main_uart0_pins_default: main-uart0-default-pins {
306 pinctrl-single,pins = <
314 main_uart1_pins_default: main-uart1-default-pins {
315 pinctrl-single,pins = <
321 main_i2c0_pins_default: main-i2c0-default-pins {
322 pinctrl-single,pins = <
328 main_i2c1_pins_default: main-i2c1-default-pins {
329 pinctrl-single,pins = <
335 main_i2c3_pins_default: main-i2c3-default-pins {
336 pinctrl-single,pins = <
342 main_usbss0_pins_default: main-usbss0-default-pins {
343 pinctrl-single,pins = <
349 main_usbss1_pins_default: main-usbss1-default-pins {
350 pinctrl-single,pins = <
355 dp0_pins_default: dp0-default-pins {
356 pinctrl-single,pins = <
361 dp_pwr_en_pins_default: dp-pwr-en-default-pins {
362 pinctrl-single,pins = <
367 dss_vout0_pins_default: dss-vout0-default-pins {
368 pinctrl-single,pins = <
400 hdmi_hpd_pins_default: hdmi-hpd-default-pins {
401 pinctrl-single,pins = <
406 hdmi_pdn_pins_default: hdmi-pdn-default-pins {
407 pinctrl-single,pins = <
413 ekey_reset_pins_default: ekey-reset-pns-default-pins {
414 pinctrl-single,pins = <
419 main_i2c5_pins_default: main-i2c5-default-pins {
420 pinctrl-single,pins = <
426 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
427 pinctrl-single,pins = <
454 rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins {
455 pinctrl-single,pins = <
462 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
463 pinctrl-single,pins = <
479 mcu_mdio_pins_default: mcu-mdio1-default-pins {
480 pinctrl-single,pins = <
486 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
487 pinctrl-single,pins = <
502 vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
503 pinctrl-single,pins = <
508 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
509 pinctrl-single,pins = <
514 wkup_uart0_pins_default: wkup-uart0-default-pins {
515 pinctrl-single,pins = <
521 mcu_uart0_pins_default: mcu-uart0-default-pins {
522 pinctrl-single,pins = <
530 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
531 pinctrl-single,pins = <
538 mkey_reset_pins_default: mkey-reset-pns-default-pins {
539 pinctrl-single,pins = <
548 pinctrl-names = "default";
549 pinctrl-0 = <&wkup_uart0_pins_default>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&wkup_i2c0_pins_default>;
556 clock-frequency = <400000>;
559 /* AT24C512C-MAHM-T */
567 pinctrl-names = "default";
568 pinctrl-0 = <&mcu_uart0_pins_default>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&main_uart0_pins_default>;
576 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&main_uart1_pins_default>;
588 vmmc-supply = <&vdd_mmc1>;
589 vqmmc-supply = <&vdd_sd_dv_alt>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&main_mmc1_pins_default>;
592 ti,driver-strength-ohm = <50>;
593 disable-wp;
598 pinctrl-names = "default";
599 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
602 compatible = "jedec,spi-nor";
604 spi-tx-bus-width = <8>;
605 spi-rx-bus-width = <8>;
606 spi-max-frequency = <25000000>;
607 cdns,tshsl-ns = <60>;
608 cdns,tsd2d-ns = <60>;
609 cdns,tchsh-ns = <60>;
610 cdns,tslch-ns = <60>;
611 cdns,read-delay = <4>;
614 compatible = "fixed-partitions";
615 #address-cells = <1>;
616 #size-cells = <1>;
629 label = "ospi.u-boot";
663 pinctrl-names = "default";
664 pinctrl-0 = <&main_i2c0_pins_default>;
665 clock-frequency = <400000>;
667 i2c-mux@71 {
669 #address-cells = <1>;
670 #size-cells = <0>;
675 #address-cells = <1>;
676 #size-cells = <0>;
682 #address-cells = <1>;
683 #size-cells = <0>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&main_i2c1_pins_default>;
694 clock-frequency = <100000>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&main_i2c3_pins_default>;
701 clock-frequency = <400000>;
703 i2c-mux@70 {
705 #address-cells = <1>;
706 #size-cells = <0>;
711 #address-cells = <1>;
712 #size-cells = <0>;
718 #address-cells = <1>;
719 #size-cells = <0>;
728 pinctrl-names = "default";
729 pinctrl-0 = <&main_i2c5_pins_default>;
730 clock-frequency = <400000>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&rpi_header_gpio0_pins_default>;
741 pinctrl-names = "default";
742 pinctrl-0 = <&rpi_header_gpio1_pins_default>;
750 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
754 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
763 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
764 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
770 cdns,num-lanes = <2>;
771 #phy-cells = <0>;
772 cdns,phy-type = <PHY_TYPE_USB3>;
781 cdns,phy-type = <PHY_TYPE_DP>;
782 cdns,num-lanes = <4>;
783 cdns,max-bit-rate = <5400>;
784 #phy-cells = <0>;
790 phy-names = "dpphy";
791 pinctrl-names = "default";
792 pinctrl-0 = <&dp0_pins_default>;
796 pinctrl-names = "default";
797 pinctrl-0 = <&main_usbss0_pins_default>;
798 ti,vbus-divider;
803 maximum-speed = "super-speed";
805 phy-names = "cdns3,usb3-phy";
811 cdns,num-lanes = <1>;
812 #phy-cells = <0>;
813 cdns,phy-type = <PHY_TYPE_USB3>;
819 pinctrl-names = "default";
820 pinctrl-0 = <&main_usbss1_pins_default>;
821 ti,vbus-divider;
826 maximum-speed = "super-speed";
828 phy-names = "cdns3,usb3-phy";
832 pinctrl-names = "default";
833 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
837 phy0: ethernet-phy@0 { label
839 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
840 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
845 phy-mode = "rgmii-rxid";
846 phy-handle = <&phy0>;
850 pinctrl-names = "default";
851 pinctrl-0 = <&dss_vout0_pins_default>;
853 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
857 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
864 #address-cells = <1>;
865 #size-cells = <0>;
871 remote-endpoint = <&dp0_in>;
879 remote-endpoint = <&tfp410_in>;
885 #address-cells = <1>;
886 #size-cells = <0>;
891 remote-endpoint = <&dpi0_out>;
898 remote-endpoint = <&dp_connector_in>;
906 cdns,num-lanes = <1>;
907 #phy-cells = <0>;
908 cdns,phy-type = <PHY_TYPE_PCIE>;
916 cdns,num-lanes = <2>;
917 #phy-cells = <0>;
918 cdns,phy-type = <PHY_TYPE_PCIE>;
925 pinctrl-names = "default";
926 pinctrl-0 = <&ekey_reset_pins_default>;
927 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>;
930 phy-names = "pcie-phy";
931 num-lanes = <1>;
936 pinctrl-names = "default";
937 pinctrl-0 = <&mkey_reset_pins_default>;
938 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
941 phy-names = "pcie-phy";
942 num-lanes = <2>;
953 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
954 ti,mbox-rx = <0 0 0>;
955 ti,mbox-tx = <1 0 0>;
958 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
959 ti,mbox-rx = <2 0 0>;
960 ti,mbox-tx = <3 0 0>;
968 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
969 ti,mbox-rx = <0 0 0>;
970 ti,mbox-tx = <1 0 0>;
973 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
974 ti,mbox-rx = <2 0 0>;
975 ti,mbox-tx = <3 0 0>;
983 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
984 ti,mbox-rx = <0 0 0>;
985 ti,mbox-tx = <1 0 0>;
988 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
989 ti,mbox-rx = <2 0 0>;
990 ti,mbox-tx = <3 0 0>;
998 mbox_c66_0: mbox-c66-0 {
999 ti,mbox-rx = <0 0 0>;
1000 ti,mbox-tx = <1 0 0>;
1003 mbox_c66_1: mbox-c66-1 {
1004 ti,mbox-rx = <2 0 0>;
1005 ti,mbox-tx = <3 0 0>;
1013 mbox_c71_0: mbox-c71-0 {
1014 ti,mbox-rx = <0 0 0>;
1015 ti,mbox-tx = <1 0 0>;
1021 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
1027 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
1033 memory-region = <&main_r5fss0_core0_dma_memory_region>,
1039 memory-region = <&main_r5fss0_core1_dma_memory_region>,
1045 memory-region = <&main_r5fss1_core0_dma_memory_region>,
1051 memory-region = <&main_r5fss1_core1_dma_memory_region>,
1058 memory-region = <&c66_0_dma_memory_region>,
1065 memory-region = <&c66_1_dma_memory_region>,
1072 memory-region = <&c71_0_dma_memory_region>,