Lines Matching +full:0 +full:x43000014
19 reg = <0x00 0x44083000 0x0 0x1000>;
39 reg = <0x0 0x40f00000 0x0 0x20000>;
42 ranges = <0x0 0x0 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
53 reg = <0x0 0x43000014 0x0 0x4>;
58 /* Proxy 0 addressing */
59 reg = <0x00 0x4301c000 0x00 0x178>;
62 pinctrl-single,function-mask = <0xffffffff>;
68 reg = <0x00 0x40f04200 0x00 0x28>;
71 pinctrl-single,function-mask = <0x0000000f>;
79 reg = <0x00 0x40f04280 0x00 0x28>;
82 pinctrl-single,function-mask = <0x0000000f>;
89 reg = <0x00 0x41c00000 0x00 0x100000>;
90 ranges = <0x0 0x00 0x41c00000 0x100000>;
97 reg = <0x00 0x40400000 0x00 0x400>;
111 reg = <0x00 0x40410000 0x00 0x400>;
115 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
125 reg = <0x00 0x40420000 0x00 0x400>;
139 reg = <0x00 0x40430000 0x00 0x400>;
143 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
153 reg = <0x00 0x40440000 0x00 0x400>;
167 reg = <0x00 0x40450000 0x00 0x400>;
171 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>;
181 reg = <0x00 0x40460000 0x00 0x400>;
195 reg = <0x00 0x40470000 0x00 0x400>;
199 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>;
209 reg = <0x00 0x40480000 0x00 0x400>;
223 reg = <0x00 0x40490000 0x00 0x400>;
227 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>;
236 reg = <0x00 0x42300000 0x00 0x100>;
241 clocks = <&k3_clks 287 0>;
248 reg = <0x00 0x40a00000 0x00 0x100>;
253 clocks = <&k3_clks 149 0>;
260 reg = <0x00 0x42200000 0x00 0x400>;
272 reg = <0x0 0x42110000 0x0 0x100>;
280 ti,davinci-gpio-unbanked = <0>;
282 clocks = <&k3_clks 113 0>;
289 reg = <0x0 0x42100000 0x0 0x100>;
297 ti,davinci-gpio-unbanked = <0>;
299 clocks = <&k3_clks 114 0>;
306 reg = <0x0 0x40b00000 0x0 0x100>;
309 #size-cells = <0>;
311 clocks = <&k3_clks 194 0>;
318 reg = <0x0 0x40b10000 0x0 0x100>;
321 #size-cells = <0>;
323 clocks = <&k3_clks 195 0>;
330 reg = <0x0 0x42120000 0x0 0x100>;
333 #size-cells = <0>;
335 clocks = <&k3_clks 197 0>;
342 reg = <0x0 0x47000000 0x0 0x100>;
349 reg = <0x00 0x47000004 0x00 0x2>;
351 mux-reg-masks = <0x4 0x2>; /* HBMC select */
356 reg = <0x00 0x47034000 0x00 0x100>,
357 <0x05 0x00000000 0x01 0x0000000>;
359 clocks = <&k3_clks 102 0>;
364 mux-controls = <&hbmc_mux 0>;
370 reg = <0x0 0x47040000 0x0 0x100>,
371 <0x5 0x00000000 0x1 0x0000000>;
375 cdns,trigger-address = <0x0>;
376 clocks = <&k3_clks 103 0>;
377 assigned-clocks = <&k3_clks 103 0>;
382 #size-cells = <0>;
388 reg = <0x0 0x47050000 0x0 0x100>,
389 <0x7 0x00000000 0x1 0x00000000>;
393 cdns,trigger-address = <0x0>;
394 clocks = <&k3_clks 104 0>;
397 #size-cells = <0>;
404 reg = <0x0 0x40200000 0x0 0x1000>;
406 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
407 clocks = <&k3_clks 0 1>;
408 assigned-clocks = <&k3_clks 0 3>;
411 dmas = <&main_udmap 0x7400>,
412 <&main_udmap 0x7401>;
424 reg = <0x0 0x40210000 0x0 0x1000>;
431 dmas = <&main_udmap 0x7402>,
432 <&main_udmap 0x7403>;
446 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
454 reg = <0x0 0x2b800000 0x0 0x400000>,
455 <0x0 0x2b000000 0x0 0x400000>,
456 <0x0 0x28590000 0x0 0x100>,
457 <0x0 0x2a500000 0x0 0x40000>,
458 <0x0 0x28440000 0x0 0x40000>;
461 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
469 reg = <0x0 0x285c0000 0x0 0x100>,
470 <0x0 0x2a800000 0x0 0x40000>,
471 <0x0 0x2aa00000 0x0 0x40000>;
480 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
481 <0x0f>; /* TX_HCHAN */
482 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
483 <0x0b>; /* RX_HCHAN */
484 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
492 reg = <0x0 0x2a480000 0x0 0x80000>,
493 <0x0 0x2a380000 0x0 0x80000>,
494 <0x0 0x2a400000 0x0 0x80000>;
507 reg = <0x0 0x46000000 0x0 0x200000>;
509 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
515 dmas = <&mcu_udmap 0xf000>,
516 <&mcu_udmap 0xf001>,
517 <&mcu_udmap 0xf002>,
518 <&mcu_udmap 0xf003>,
519 <&mcu_udmap 0xf004>,
520 <&mcu_udmap 0xf005>,
521 <&mcu_udmap 0xf006>,
522 <&mcu_udmap 0xf007>,
523 <&mcu_udmap 0x7000>;
530 #size-cells = <0>;
536 ti,syscon-efuse = <&mcu_conf 0x200>;
543 reg = <0x0 0xf00 0x0 0x100>;
545 #size-cells = <0>;
553 reg = <0x0 0x3d000 0x0 0x400>;
568 ranges = <0x41000000 0x00 0x41000000 0x20000>,
569 <0x41400000 0x00 0x41400000 0x20000>;
574 reg = <0x41000000 0x00008000>,
575 <0x41010000 0x00008000>;
579 ti,sci-proc-ids = <0x01 0xff>;
589 reg = <0x41400000 0x00008000>,
590 <0x41410000 0x00008000>;
594 ti,sci-proc-ids = <0x02 0xff>;
605 reg = <0x00 0x40528000 0x00 0x200>,
606 <0x00 0x40500000 0x00 0x8000>;
609 clocks = <&k3_clks 172 0>, <&k3_clks 172 1>;
614 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
620 reg = <0x00 0x40568000 0x00 0x200>,
621 <0x00 0x40540000 0x00 0x8000>;
624 clocks = <&k3_clks 173 0>, <&k3_clks 173 1>;
629 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
635 reg = <0x00 0x040300000 0x00 0x400>;
638 #size-cells = <0>;
646 reg = <0x00 0x040310000 0x00 0x400>;
649 #size-cells = <0>;
657 reg = <0x00 0x040320000 0x00 0x400>;
660 #size-cells = <0>;
668 reg = <0x00 0x42040000 0x00 0x350>,
669 <0x00 0x42050000 0x00 0x350>,
670 <0x00 0x43000300 0x00 0x10>;