Lines Matching +full:am654 +full:- +full:cpsw +full:- +full:nuss
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
20 cmn_refclk1: clock-cmnrefclk1 {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <0>;
29 compatible = "mmio-sram";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 atf-sram@0 {
40 scm_conf: scm-conf@100000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
43 #address-cells = <1>;
44 #size-cells = <1>;
47 serdes_ln_ctrl: mux-controller@4080 {
48 compatible = "mmio-mux";
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
57 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
66 compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
67 ti,qsgmii-main-ports = <2>, <2>;
69 #phy-cells = <1>;
72 usb_serdes_mux: mux-controller@4000 {
73 compatible = "mmio-mux";
74 #mux-control-cells = <1>;
75 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
79 ehrpwm_tbclk: clock-controller@4140 {
80 compatible = "ti,am654-ehrpwm-tbclk";
82 #clock-cells = <1>;
87 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
88 #pwm-cells = <3>;
90 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
92 clock-names = "tbclk", "fck";
97 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
98 #pwm-cells = <3>;
100 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
102 clock-names = "tbclk", "fck";
107 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
108 #pwm-cells = <3>;
110 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
112 clock-names = "tbclk", "fck";
117 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
118 #pwm-cells = <3>;
120 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
122 clock-names = "tbclk", "fck";
127 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
128 #pwm-cells = <3>;
130 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
132 clock-names = "tbclk", "fck";
137 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
138 #pwm-cells = <3>;
140 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
142 clock-names = "tbclk", "fck";
146 gic500: interrupt-controller@1800000 {
147 compatible = "arm,gic-v3";
148 #address-cells = <2>;
149 #size-cells = <2>;
151 #interrupt-cells = <3>;
152 interrupt-controller;
162 gic_its: msi-controller@1820000 {
163 compatible = "arm,gic-v3-its";
165 socionext,synquacer-pre-its = <0x1000000 0x400000>;
166 msi-controller;
167 #msi-cells = <1>;
171 main_gpio_intr: interrupt-controller@a00000 {
172 compatible = "ti,sci-intr";
174 ti,intr-trigger-type = <1>;
175 interrupt-controller;
176 interrupt-parent = <&gic500>;
177 #interrupt-cells = <1>;
179 ti,sci-dev-id = <131>;
180 ti,interrupt-ranges = <8 392 56>;
184 compatible = "simple-mfd";
185 #address-cells = <2>;
186 #size-cells = <2>;
188 dma-coherent;
189 dma-ranges;
191 ti,sci-dev-id = <199>;
193 main_navss_intr: interrupt-controller@310e0000 {
194 compatible = "ti,sci-intr";
196 ti,intr-trigger-type = <4>;
197 interrupt-controller;
198 interrupt-parent = <&gic500>;
199 #interrupt-cells = <1>;
201 ti,sci-dev-id = <213>;
202 ti,interrupt-ranges = <0 64 64>,
207 main_udmass_inta: interrupt-controller@33d00000 {
208 compatible = "ti,sci-inta";
210 interrupt-controller;
211 interrupt-parent = <&main_navss_intr>;
212 msi-controller;
213 #interrupt-cells = <0>;
215 ti,sci-dev-id = <209>;
216 ti,interrupt-ranges = <0 0 256>;
220 compatible = "ti,am654-secure-proxy";
221 #mbox-cells = <1>;
222 reg-names = "target_data", "rt", "scfg";
226 interrupt-names = "rx_011";
231 compatible = "arm,smmu-v3";
233 interrupt-parent = <&gic500>;
236 interrupt-names = "eventq", "gerror";
237 #iommu-cells = <1>;
241 compatible = "ti,am654-hwspinlock";
243 #hwlock-cells = <1>;
247 compatible = "ti,am654-mailbox";
249 #mbox-cells = <1>;
250 ti,mbox-num-users = <4>;
251 ti,mbox-num-fifos = <16>;
252 interrupt-parent = <&main_navss_intr>;
257 compatible = "ti,am654-mailbox";
259 #mbox-cells = <1>;
260 ti,mbox-num-users = <4>;
261 ti,mbox-num-fifos = <16>;
262 interrupt-parent = <&main_navss_intr>;
267 compatible = "ti,am654-mailbox";
269 #mbox-cells = <1>;
270 ti,mbox-num-users = <4>;
271 ti,mbox-num-fifos = <16>;
272 interrupt-parent = <&main_navss_intr>;
277 compatible = "ti,am654-mailbox";
279 #mbox-cells = <1>;
280 ti,mbox-num-users = <4>;
281 ti,mbox-num-fifos = <16>;
282 interrupt-parent = <&main_navss_intr>;
287 compatible = "ti,am654-mailbox";
289 #mbox-cells = <1>;
290 ti,mbox-num-users = <4>;
291 ti,mbox-num-fifos = <16>;
292 interrupt-parent = <&main_navss_intr>;
297 compatible = "ti,am654-mailbox";
299 #mbox-cells = <1>;
300 ti,mbox-num-users = <4>;
301 ti,mbox-num-fifos = <16>;
302 interrupt-parent = <&main_navss_intr>;
307 compatible = "ti,am654-mailbox";
309 #mbox-cells = <1>;
310 ti,mbox-num-users = <4>;
311 ti,mbox-num-fifos = <16>;
312 interrupt-parent = <&main_navss_intr>;
317 compatible = "ti,am654-mailbox";
319 #mbox-cells = <1>;
320 ti,mbox-num-users = <4>;
321 ti,mbox-num-fifos = <16>;
322 interrupt-parent = <&main_navss_intr>;
327 compatible = "ti,am654-mailbox";
329 #mbox-cells = <1>;
330 ti,mbox-num-users = <4>;
331 ti,mbox-num-fifos = <16>;
332 interrupt-parent = <&main_navss_intr>;
337 compatible = "ti,am654-mailbox";
339 #mbox-cells = <1>;
340 ti,mbox-num-users = <4>;
341 ti,mbox-num-fifos = <16>;
342 interrupt-parent = <&main_navss_intr>;
347 compatible = "ti,am654-mailbox";
349 #mbox-cells = <1>;
350 ti,mbox-num-users = <4>;
351 ti,mbox-num-fifos = <16>;
352 interrupt-parent = <&main_navss_intr>;
357 compatible = "ti,am654-mailbox";
359 #mbox-cells = <1>;
360 ti,mbox-num-users = <4>;
361 ti,mbox-num-fifos = <16>;
362 interrupt-parent = <&main_navss_intr>;
367 compatible = "ti,am654-navss-ringacc";
373 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
374 ti,num-rings = <1024>;
375 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
377 ti,sci-dev-id = <211>;
378 msi-parent = <&main_udmass_inta>;
381 main_udmap: dma-controller@31150000 {
382 compatible = "ti,j721e-navss-main-udmap";
386 reg-names = "gcfg", "rchanrt", "tchanrt";
387 msi-parent = <&main_udmass_inta>;
388 #dma-cells = <1>;
391 ti,sci-dev-id = <212>;
394 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
397 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
400 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
404 compatible = "ti,j721e-cpts";
406 reg-names = "cpts";
408 clock-names = "cpts";
409 interrupts-extended = <&main_navss_intr 391>;
410 interrupt-names = "cpts";
411 ti,cpts-periodic-outputs = <6>;
412 ti,cpts-ext-ts-inputs = <8>;
417 compatible = "ti,j721e-cpswxg-nuss";
418 #address-cells = <2>;
419 #size-cells = <2>;
421 reg-names = "cpsw_nuss";
424 clock-names = "fck";
425 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
436 dma-names = "tx0", "tx1", "tx2", "tx3",
442 ethernet-ports {
443 #address-cells = <1>;
444 #size-cells = <0>;
447 ti,mac-only;
454 ti,mac-only;
461 ti,mac-only;
468 ti,mac-only;
475 ti,mac-only;
482 ti,mac-only;
489 ti,mac-only;
496 ti,mac-only;
503 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
505 #address-cells = <1>;
506 #size-cells = <0>;
508 clock-names = "fck";
514 compatible = "ti,j721e-cpts";
517 clock-names = "cpts";
518 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
519 interrupt-names = "cpts";
520 ti,cpts-ext-ts-inputs = <4>;
521 ti,cpts-periodic-outputs = <2>;
526 compatible = "ti,j721e-sa2ul";
528 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
529 #address-cells = <2>;
530 #size-cells = <2>;
535 dma-names = "tx", "rx1", "rx2";
538 compatible = "inside-secure,safexcel-eip76";
545 compatible = "pinctrl-single";
548 #pinctrl-cells = <1>;
549 pinctrl-single,register-width = <32>;
550 pinctrl-single,function-mask = <0xffffffff>;
555 compatible = "pinctrl-single";
557 #pinctrl-cells = <1>;
558 pinctrl-single,register-width = <32>;
559 pinctrl-single,function-mask = <0x00000007>;
564 compatible = "pinctrl-single";
566 #pinctrl-cells = <1>;
567 pinctrl-single,register-width = <32>;
568 pinctrl-single,function-mask = <0x0000001f>;
572 compatible = "ti,j721e-wiz-16g";
573 #address-cells = <1>;
574 #size-cells = <1>;
575 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
577 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
578 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
579 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
580 num-lanes = <2>;
581 #reset-cells = <1>;
584 wiz0_pll0_refclk: pll0-refclk {
586 #clock-cells = <0>;
587 assigned-clocks = <&wiz0_pll0_refclk>;
588 assigned-clock-parents = <&k3_clks 292 11>;
591 wiz0_pll1_refclk: pll1-refclk {
593 #clock-cells = <0>;
594 assigned-clocks = <&wiz0_pll1_refclk>;
595 assigned-clock-parents = <&k3_clks 292 0>;
598 wiz0_refclk_dig: refclk-dig {
600 #clock-cells = <0>;
601 assigned-clocks = <&wiz0_refclk_dig>;
602 assigned-clock-parents = <&k3_clks 292 11>;
605 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
607 #clock-cells = <0>;
610 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
612 #clock-cells = <0>;
616 compatible = "ti,sierra-phy-t0";
617 reg-names = "serdes";
619 #address-cells = <1>;
620 #size-cells = <0>;
621 #clock-cells = <1>;
623 reset-names = "sierra_reset";
626 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
632 compatible = "ti,j721e-wiz-16g";
633 #address-cells = <1>;
634 #size-cells = <1>;
635 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
637 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
638 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
639 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
640 num-lanes = <2>;
641 #reset-cells = <1>;
644 wiz1_pll0_refclk: pll0-refclk {
646 #clock-cells = <0>;
647 assigned-clocks = <&wiz1_pll0_refclk>;
648 assigned-clock-parents = <&k3_clks 293 13>;
651 wiz1_pll1_refclk: pll1-refclk {
653 #clock-cells = <0>;
654 assigned-clocks = <&wiz1_pll1_refclk>;
655 assigned-clock-parents = <&k3_clks 293 0>;
658 wiz1_refclk_dig: refclk-dig {
660 #clock-cells = <0>;
661 assigned-clocks = <&wiz1_refclk_dig>;
662 assigned-clock-parents = <&k3_clks 293 13>;
665 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
667 #clock-cells = <0>;
670 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
672 #clock-cells = <0>;
676 compatible = "ti,sierra-phy-t0";
677 reg-names = "serdes";
679 #address-cells = <1>;
680 #size-cells = <0>;
681 #clock-cells = <1>;
683 reset-names = "sierra_reset";
686 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
692 compatible = "ti,j721e-wiz-16g";
693 #address-cells = <1>;
694 #size-cells = <1>;
695 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
697 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
698 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
699 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
700 num-lanes = <2>;
701 #reset-cells = <1>;
704 wiz2_pll0_refclk: pll0-refclk {
706 #clock-cells = <0>;
707 assigned-clocks = <&wiz2_pll0_refclk>;
708 assigned-clock-parents = <&k3_clks 294 11>;
711 wiz2_pll1_refclk: pll1-refclk {
713 #clock-cells = <0>;
714 assigned-clocks = <&wiz2_pll1_refclk>;
715 assigned-clock-parents = <&k3_clks 294 0>;
718 wiz2_refclk_dig: refclk-dig {
720 #clock-cells = <0>;
721 assigned-clocks = <&wiz2_refclk_dig>;
722 assigned-clock-parents = <&k3_clks 294 11>;
725 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
727 #clock-cells = <0>;
730 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
732 #clock-cells = <0>;
736 compatible = "ti,sierra-phy-t0";
737 reg-names = "serdes";
739 #address-cells = <1>;
740 #size-cells = <0>;
741 #clock-cells = <1>;
743 reset-names = "sierra_reset";
746 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
752 compatible = "ti,j721e-wiz-16g";
753 #address-cells = <1>;
754 #size-cells = <1>;
755 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
757 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
758 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
759 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
760 num-lanes = <2>;
761 #reset-cells = <1>;
764 wiz3_pll0_refclk: pll0-refclk {
766 #clock-cells = <0>;
767 assigned-clocks = <&wiz3_pll0_refclk>;
768 assigned-clock-parents = <&k3_clks 295 9>;
771 wiz3_pll1_refclk: pll1-refclk {
773 #clock-cells = <0>;
774 assigned-clocks = <&wiz3_pll1_refclk>;
775 assigned-clock-parents = <&k3_clks 295 0>;
778 wiz3_refclk_dig: refclk-dig {
780 #clock-cells = <0>;
781 assigned-clocks = <&wiz3_refclk_dig>;
782 assigned-clock-parents = <&k3_clks 295 9>;
785 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
787 #clock-cells = <0>;
790 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
792 #clock-cells = <0>;
796 compatible = "ti,sierra-phy-t0";
797 reg-names = "serdes";
799 #address-cells = <1>;
800 #size-cells = <0>;
801 #clock-cells = <1>;
803 reset-names = "sierra_reset";
806 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
812 compatible = "ti,j721e-pcie-host";
817 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
818 interrupt-names = "link_state";
821 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
822 max-link-speed = <3>;
823 num-lanes = <2>;
824 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
826 clock-names = "fck";
827 #address-cells = <3>;
828 #size-cells = <2>;
829 bus-range = <0x0 0xff>;
830 vendor-id = <0x104c>;
831 device-id = <0xb00d>;
832 msi-map = <0x0 &gic_its 0x0 0x10000>;
833 dma-coherent;
836 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
841 compatible = "ti,j721e-pcie-host";
846 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
847 interrupt-names = "link_state";
850 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
851 max-link-speed = <3>;
852 num-lanes = <2>;
853 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
855 clock-names = "fck";
856 #address-cells = <3>;
857 #size-cells = <2>;
858 bus-range = <0x0 0xff>;
859 vendor-id = <0x104c>;
860 device-id = <0xb00d>;
861 msi-map = <0x0 &gic_its 0x10000 0x10000>;
862 dma-coherent;
865 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
870 compatible = "ti,j721e-pcie-host";
875 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
876 interrupt-names = "link_state";
879 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
880 max-link-speed = <3>;
881 num-lanes = <2>;
882 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
884 clock-names = "fck";
885 #address-cells = <3>;
886 #size-cells = <2>;
887 bus-range = <0x0 0xff>;
888 vendor-id = <0x104c>;
889 device-id = <0xb00d>;
890 msi-map = <0x0 &gic_its 0x20000 0x10000>;
891 dma-coherent;
894 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
899 compatible = "ti,j721e-pcie-host";
904 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
905 interrupt-names = "link_state";
908 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
909 max-link-speed = <3>;
910 num-lanes = <2>;
911 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
913 clock-names = "fck";
914 #address-cells = <3>;
915 #size-cells = <2>;
916 bus-range = <0x0 0xff>;
917 vendor-id = <0x104c>;
918 device-id = <0xb00d>;
919 msi-map = <0x0 &gic_its 0x30000 0x10000>;
920 dma-coherent;
923 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
928 compatible = "ti,am64-wiz-10g";
929 #address-cells = <1>;
930 #size-cells = <1>;
931 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
933 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
934 assigned-clocks = <&k3_clks 297 9>;
935 assigned-clock-parents = <&k3_clks 297 10>;
936 assigned-clock-rates = <19200000>;
937 num-lanes = <4>;
938 #reset-cells = <1>;
939 #clock-cells = <1>;
948 compatible = "ti,j721e-serdes-10g";
951 reg-names = "torrent_phy", "dptx_phy";
954 reset-names = "torrent_reset";
956 clock-names = "refclk";
957 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
960 assigned-clock-parents = <&k3_clks 297 9>,
963 #address-cells = <1>;
964 #size-cells = <0>;
969 compatible = "ti,am654-timer";
973 clock-names = "fck";
974 assigned-clocks = <&k3_clks 49 1>;
975 assigned-clock-parents = <&k3_clks 49 2>;
976 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
977 ti,timer-pwm;
981 compatible = "ti,am654-timer";
985 clock-names = "fck";
986 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
987 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
988 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
989 ti,timer-pwm;
993 compatible = "ti,am654-timer";
997 clock-names = "fck";
998 assigned-clocks = <&k3_clks 51 1>;
999 assigned-clock-parents = <&k3_clks 51 2>;
1000 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
1001 ti,timer-pwm;
1005 compatible = "ti,am654-timer";
1009 clock-names = "fck";
1010 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1011 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
1012 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1013 ti,timer-pwm;
1017 compatible = "ti,am654-timer";
1021 clock-names = "fck";
1022 assigned-clocks = <&k3_clks 53 1>;
1023 assigned-clock-parents = <&k3_clks 53 2>;
1024 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1025 ti,timer-pwm;
1029 compatible = "ti,am654-timer";
1033 clock-names = "fck";
1034 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1035 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
1036 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1037 ti,timer-pwm;
1041 compatible = "ti,am654-timer";
1045 clock-names = "fck";
1046 assigned-clocks = <&k3_clks 55 1>;
1047 assigned-clock-parents = <&k3_clks 55 2>;
1048 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1049 ti,timer-pwm;
1053 compatible = "ti,am654-timer";
1057 clock-names = "fck";
1058 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1059 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
1060 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1061 ti,timer-pwm;
1065 compatible = "ti,am654-timer";
1069 clock-names = "fck";
1070 assigned-clocks = <&k3_clks 58 1>;
1071 assigned-clock-parents = <&k3_clks 58 2>;
1072 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1073 ti,timer-pwm;
1077 compatible = "ti,am654-timer";
1081 clock-names = "fck";
1082 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1083 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
1084 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1085 ti,timer-pwm;
1089 compatible = "ti,am654-timer";
1093 clock-names = "fck";
1094 assigned-clocks = <&k3_clks 60 1>;
1095 assigned-clock-parents = <&k3_clks 60 2>;
1096 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1097 ti,timer-pwm;
1101 compatible = "ti,am654-timer";
1105 clock-names = "fck";
1106 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1107 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
1108 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1109 ti,timer-pwm;
1113 compatible = "ti,am654-timer";
1117 clock-names = "fck";
1118 assigned-clocks = <&k3_clks 63 1>;
1119 assigned-clock-parents = <&k3_clks 63 2>;
1120 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1121 ti,timer-pwm;
1125 compatible = "ti,am654-timer";
1129 clock-names = "fck";
1130 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1131 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
1132 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1133 ti,timer-pwm;
1137 compatible = "ti,am654-timer";
1141 clock-names = "fck";
1142 assigned-clocks = <&k3_clks 65 1>;
1143 assigned-clock-parents = <&k3_clks 65 2>;
1144 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1145 ti,timer-pwm;
1149 compatible = "ti,am654-timer";
1153 clock-names = "fck";
1154 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1155 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
1156 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1157 ti,timer-pwm;
1161 compatible = "ti,am654-timer";
1165 clock-names = "fck";
1166 assigned-clocks = <&k3_clks 67 1>;
1167 assigned-clock-parents = <&k3_clks 67 2>;
1168 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1169 ti,timer-pwm;
1173 compatible = "ti,am654-timer";
1177 clock-names = "fck";
1178 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1179 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
1180 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1181 ti,timer-pwm;
1185 compatible = "ti,am654-timer";
1189 clock-names = "fck";
1190 assigned-clocks = <&k3_clks 69 1>;
1191 assigned-clock-parents = <&k3_clks 69 2>;
1192 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1193 ti,timer-pwm;
1197 compatible = "ti,am654-timer";
1201 clock-names = "fck";
1202 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1203 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
1204 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1205 ti,timer-pwm;
1209 compatible = "ti,j721e-uart", "ti,am654-uart";
1212 clock-frequency = <48000000>;
1213 current-speed = <115200>;
1214 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
1216 clock-names = "fclk";
1221 compatible = "ti,j721e-uart", "ti,am654-uart";
1224 clock-frequency = <48000000>;
1225 current-speed = <115200>;
1226 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1228 clock-names = "fclk";
1233 compatible = "ti,j721e-uart", "ti,am654-uart";
1236 clock-frequency = <48000000>;
1237 current-speed = <115200>;
1238 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
1240 clock-names = "fclk";
1245 compatible = "ti,j721e-uart", "ti,am654-uart";
1248 clock-frequency = <48000000>;
1249 current-speed = <115200>;
1250 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
1252 clock-names = "fclk";
1257 compatible = "ti,j721e-uart", "ti,am654-uart";
1260 clock-frequency = <48000000>;
1261 current-speed = <115200>;
1262 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
1264 clock-names = "fclk";
1269 compatible = "ti,j721e-uart", "ti,am654-uart";
1272 clock-frequency = <48000000>;
1273 current-speed = <115200>;
1274 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
1276 clock-names = "fclk";
1281 compatible = "ti,j721e-uart", "ti,am654-uart";
1284 clock-frequency = <48000000>;
1285 current-speed = <115200>;
1286 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
1288 clock-names = "fclk";
1293 compatible = "ti,j721e-uart", "ti,am654-uart";
1296 clock-frequency = <48000000>;
1297 current-speed = <115200>;
1298 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
1300 clock-names = "fclk";
1305 compatible = "ti,j721e-uart", "ti,am654-uart";
1308 clock-frequency = <48000000>;
1309 current-speed = <115200>;
1310 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
1312 clock-names = "fclk";
1317 compatible = "ti,j721e-uart", "ti,am654-uart";
1320 clock-frequency = <48000000>;
1321 current-speed = <115200>;
1322 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1324 clock-names = "fclk";
1329 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1331 gpio-controller;
1332 #gpio-cells = <2>;
1333 interrupt-parent = <&main_gpio_intr>;
1336 interrupt-controller;
1337 #interrupt-cells = <2>;
1339 ti,davinci-gpio-unbanked = <0>;
1340 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
1342 clock-names = "gpio";
1347 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1349 gpio-controller;
1350 #gpio-cells = <2>;
1351 interrupt-parent = <&main_gpio_intr>;
1353 interrupt-controller;
1354 #interrupt-cells = <2>;
1356 ti,davinci-gpio-unbanked = <0>;
1357 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
1359 clock-names = "gpio";
1364 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1366 gpio-controller;
1367 #gpio-cells = <2>;
1368 interrupt-parent = <&main_gpio_intr>;
1371 interrupt-controller;
1372 #interrupt-cells = <2>;
1374 ti,davinci-gpio-unbanked = <0>;
1375 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
1377 clock-names = "gpio";
1382 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1384 gpio-controller;
1385 #gpio-cells = <2>;
1386 interrupt-parent = <&main_gpio_intr>;
1388 interrupt-controller;
1389 #interrupt-cells = <2>;
1391 ti,davinci-gpio-unbanked = <0>;
1392 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1394 clock-names = "gpio";
1399 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1401 gpio-controller;
1402 #gpio-cells = <2>;
1403 interrupt-parent = <&main_gpio_intr>;
1406 interrupt-controller;
1407 #interrupt-cells = <2>;
1409 ti,davinci-gpio-unbanked = <0>;
1410 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1412 clock-names = "gpio";
1417 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1419 gpio-controller;
1420 #gpio-cells = <2>;
1421 interrupt-parent = <&main_gpio_intr>;
1423 interrupt-controller;
1424 #interrupt-cells = <2>;
1426 ti,davinci-gpio-unbanked = <0>;
1427 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1429 clock-names = "gpio";
1434 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1436 gpio-controller;
1437 #gpio-cells = <2>;
1438 interrupt-parent = <&main_gpio_intr>;
1441 interrupt-controller;
1442 #interrupt-cells = <2>;
1444 ti,davinci-gpio-unbanked = <0>;
1445 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1447 clock-names = "gpio";
1452 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1454 gpio-controller;
1455 #gpio-cells = <2>;
1456 interrupt-parent = <&main_gpio_intr>;
1458 interrupt-controller;
1459 #interrupt-cells = <2>;
1461 ti,davinci-gpio-unbanked = <0>;
1462 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1464 clock-names = "gpio";
1469 compatible = "ti,j721e-sdhci-8bit";
1472 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1473 clock-names = "clk_ahb", "clk_xin";
1475 assigned-clocks = <&k3_clks 91 1>;
1476 assigned-clock-parents = <&k3_clks 91 2>;
1477 bus-width = <8>;
1478 mmc-hs200-1_8v;
1479 mmc-ddr-1_8v;
1480 ti,otap-del-sel-legacy = <0x0>;
1481 ti,otap-del-sel-mmc-hs = <0x0>;
1482 ti,otap-del-sel-ddr52 = <0x5>;
1483 ti,otap-del-sel-hs200 = <0x6>;
1484 ti,otap-del-sel-hs400 = <0x0>;
1485 ti,itap-del-sel-legacy = <0x10>;
1486 ti,itap-del-sel-mmc-hs = <0xa>;
1487 ti,itap-del-sel-ddr52 = <0x3>;
1488 ti,trm-icp = <0x8>;
1489 dma-coherent;
1494 compatible = "ti,j721e-sdhci-4bit";
1497 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1498 clock-names = "clk_ahb", "clk_xin";
1500 assigned-clocks = <&k3_clks 92 0>;
1501 assigned-clock-parents = <&k3_clks 92 1>;
1502 ti,otap-del-sel-legacy = <0x0>;
1503 ti,otap-del-sel-sd-hs = <0x0>;
1504 ti,otap-del-sel-sdr12 = <0xf>;
1505 ti,otap-del-sel-sdr25 = <0xf>;
1506 ti,otap-del-sel-sdr50 = <0xc>;
1507 ti,otap-del-sel-ddr50 = <0xc>;
1508 ti,otap-del-sel-sdr104 = <0x5>;
1509 ti,itap-del-sel-legacy = <0x0>;
1510 ti,itap-del-sel-sd-hs = <0x0>;
1511 ti,itap-del-sel-sdr12 = <0x0>;
1512 ti,itap-del-sel-sdr25 = <0x0>;
1513 ti,itap-del-sel-ddr50 = <0x2>;
1514 ti,trm-icp = <0x8>;
1515 ti,clkbuf-sel = <0x7>;
1516 dma-coherent;
1517 sdhci-caps-mask = <0x2 0x0>;
1522 compatible = "ti,j721e-sdhci-4bit";
1525 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1526 clock-names = "clk_ahb", "clk_xin";
1528 assigned-clocks = <&k3_clks 93 0>;
1529 assigned-clock-parents = <&k3_clks 93 1>;
1530 ti,otap-del-sel-legacy = <0x0>;
1531 ti,otap-del-sel-sd-hs = <0x0>;
1532 ti,otap-del-sel-sdr12 = <0xf>;
1533 ti,otap-del-sel-sdr25 = <0xf>;
1534 ti,otap-del-sel-sdr50 = <0xc>;
1535 ti,otap-del-sel-ddr50 = <0xc>;
1536 ti,otap-del-sel-sdr104 = <0x5>;
1537 ti,itap-del-sel-legacy = <0x0>;
1538 ti,itap-del-sel-sd-hs = <0x0>;
1539 ti,itap-del-sel-sdr12 = <0x0>;
1540 ti,itap-del-sel-sdr25 = <0x0>;
1541 ti,itap-del-sel-ddr50 = <0x2>;
1542 ti,trm-icp = <0x8>;
1543 ti,clkbuf-sel = <0x7>;
1544 dma-coherent;
1545 sdhci-caps-mask = <0x2 0x0>;
1549 usbss0: cdns-usb@4104000 {
1550 compatible = "ti,j721e-usb";
1552 dma-coherent;
1553 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1555 clock-names = "ref", "lpm";
1556 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1557 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1558 #address-cells = <2>;
1559 #size-cells = <2>;
1567 reg-names = "otg", "xhci", "dev";
1571 interrupt-names = "host",
1574 maximum-speed = "super-speed";
1579 usbss1: cdns-usb@4114000 {
1580 compatible = "ti,j721e-usb";
1582 dma-coherent;
1583 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1585 clock-names = "ref", "lpm";
1586 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1587 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1588 #address-cells = <2>;
1589 #size-cells = <2>;
1597 reg-names = "otg", "xhci", "dev";
1601 interrupt-names = "host",
1604 maximum-speed = "super-speed";
1610 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1615 clock-names = "fck";
1617 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1622 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1625 #address-cells = <1>;
1626 #size-cells = <0>;
1627 clock-names = "fck";
1629 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1634 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1637 #address-cells = <1>;
1638 #size-cells = <0>;
1639 clock-names = "fck";
1641 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1646 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1649 #address-cells = <1>;
1650 #size-cells = <0>;
1651 clock-names = "fck";
1653 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1658 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1661 #address-cells = <1>;
1662 #size-cells = <0>;
1663 clock-names = "fck";
1665 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1670 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1673 #address-cells = <1>;
1674 #size-cells = <0>;
1675 clock-names = "fck";
1677 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1682 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1685 #address-cells = <1>;
1686 #size-cells = <0>;
1687 clock-names = "fck";
1689 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1693 ufs_wrapper: ufs-wrapper@4e80000 {
1694 compatible = "ti,j721e-ufs";
1696 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1698 assigned-clocks = <&k3_clks 277 1>;
1699 assigned-clock-parents = <&k3_clks 277 4>;
1701 #address-cells = <2>;
1702 #size-cells = <2>;
1705 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1708 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1710 clock-names = "core_clk", "phy_clk", "ref_clk";
1711 dma-coherent;
1715 mhdp: dp-bridge@a000000 {
1716 compatible = "ti,j721e-mhdp8546";
1723 reg-names = "mhdptx", "j721e-intg";
1727 interrupt-parent = <&gic500>;
1730 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1733 #address-cells = <1>;
1734 #size-cells = <0>;
1747 compatible = "ti,j721e-dss";
1770 reg-names = "common_m", "common_s0",
1782 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1784 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1790 interrupt-names = "common_m",
1800 compatible = "ti,am33xx-mcasp-audio";
1803 reg-names = "mpu","dat";
1806 interrupt-names = "tx", "rx";
1809 dma-names = "tx", "rx";
1812 clock-names = "fck";
1813 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1818 compatible = "ti,am33xx-mcasp-audio";
1821 reg-names = "mpu","dat";
1824 interrupt-names = "tx", "rx";
1827 dma-names = "tx", "rx";
1830 clock-names = "fck";
1831 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1836 compatible = "ti,am33xx-mcasp-audio";
1839 reg-names = "mpu","dat";
1842 interrupt-names = "tx", "rx";
1845 dma-names = "tx", "rx";
1848 clock-names = "fck";
1849 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1854 compatible = "ti,am33xx-mcasp-audio";
1857 reg-names = "mpu","dat";
1860 interrupt-names = "tx", "rx";
1863 dma-names = "tx", "rx";
1866 clock-names = "fck";
1867 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1872 compatible = "ti,am33xx-mcasp-audio";
1875 reg-names = "mpu","dat";
1878 interrupt-names = "tx", "rx";
1881 dma-names = "tx", "rx";
1884 clock-names = "fck";
1885 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1890 compatible = "ti,am33xx-mcasp-audio";
1893 reg-names = "mpu","dat";
1896 interrupt-names = "tx", "rx";
1899 dma-names = "tx", "rx";
1902 clock-names = "fck";
1903 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1908 compatible = "ti,am33xx-mcasp-audio";
1911 reg-names = "mpu","dat";
1914 interrupt-names = "tx", "rx";
1917 dma-names = "tx", "rx";
1920 clock-names = "fck";
1921 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1926 compatible = "ti,am33xx-mcasp-audio";
1929 reg-names = "mpu","dat";
1932 interrupt-names = "tx", "rx";
1935 dma-names = "tx", "rx";
1938 clock-names = "fck";
1939 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1944 compatible = "ti,am33xx-mcasp-audio";
1947 reg-names = "mpu","dat";
1950 interrupt-names = "tx", "rx";
1953 dma-names = "tx", "rx";
1956 clock-names = "fck";
1957 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1962 compatible = "ti,am33xx-mcasp-audio";
1965 reg-names = "mpu","dat";
1968 interrupt-names = "tx", "rx";
1971 dma-names = "tx", "rx";
1974 clock-names = "fck";
1975 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1980 compatible = "ti,am33xx-mcasp-audio";
1983 reg-names = "mpu","dat";
1986 interrupt-names = "tx", "rx";
1989 dma-names = "tx", "rx";
1992 clock-names = "fck";
1993 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1998 compatible = "ti,am33xx-mcasp-audio";
2001 reg-names = "mpu","dat";
2004 interrupt-names = "tx", "rx";
2007 dma-names = "tx", "rx";
2010 clock-names = "fck";
2011 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
2016 compatible = "ti,j7-rti-wdt";
2019 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
2020 assigned-clocks = <&k3_clks 252 1>;
2021 assigned-clock-parents = <&k3_clks 252 5>;
2025 compatible = "ti,j7-rti-wdt";
2028 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
2029 assigned-clocks = <&k3_clks 253 1>;
2030 assigned-clock-parents = <&k3_clks 253 5>;
2034 compatible = "ti,j721e-r5fss";
2035 ti,cluster-mode = <1>;
2036 #address-cells = <1>;
2037 #size-cells = <1>;
2040 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
2043 compatible = "ti,j721e-r5f";
2046 reg-names = "atcm", "btcm";
2048 ti,sci-dev-id = <245>;
2049 ti,sci-proc-ids = <0x06 0xff>;
2051 firmware-name = "j7-main-r5f0_0-fw";
2052 ti,atcm-enable = <1>;
2053 ti,btcm-enable = <1>;
2058 compatible = "ti,j721e-r5f";
2061 reg-names = "atcm", "btcm";
2063 ti,sci-dev-id = <246>;
2064 ti,sci-proc-ids = <0x07 0xff>;
2066 firmware-name = "j7-main-r5f0_1-fw";
2067 ti,atcm-enable = <1>;
2068 ti,btcm-enable = <1>;
2074 compatible = "ti,j721e-r5fss";
2075 ti,cluster-mode = <1>;
2076 #address-cells = <1>;
2077 #size-cells = <1>;
2080 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
2083 compatible = "ti,j721e-r5f";
2086 reg-names = "atcm", "btcm";
2088 ti,sci-dev-id = <247>;
2089 ti,sci-proc-ids = <0x08 0xff>;
2091 firmware-name = "j7-main-r5f1_0-fw";
2092 ti,atcm-enable = <1>;
2093 ti,btcm-enable = <1>;
2098 compatible = "ti,j721e-r5f";
2101 reg-names = "atcm", "btcm";
2103 ti,sci-dev-id = <248>;
2104 ti,sci-proc-ids = <0x09 0xff>;
2106 firmware-name = "j7-main-r5f1_1-fw";
2107 ti,atcm-enable = <1>;
2108 ti,btcm-enable = <1>;
2114 compatible = "ti,j721e-c66-dsp";
2118 reg-names = "l2sram", "l1pram", "l1dram";
2120 ti,sci-dev-id = <142>;
2121 ti,sci-proc-ids = <0x03 0xff>;
2123 firmware-name = "j7-c66_0-fw";
2128 compatible = "ti,j721e-c66-dsp";
2132 reg-names = "l2sram", "l1pram", "l1dram";
2134 ti,sci-dev-id = <143>;
2135 ti,sci-proc-ids = <0x04 0xff>;
2137 firmware-name = "j7-c66_1-fw";
2142 compatible = "ti,j721e-c71-dsp";
2145 reg-names = "l2sram", "l1dram";
2147 ti,sci-dev-id = <15>;
2148 ti,sci-proc-ids = <0x30 0xff>;
2150 firmware-name = "j7-c71_0-fw";
2155 compatible = "ti,j721e-icssg";
2157 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
2158 #address-cells = <1>;
2159 #size-cells = <1>;
2166 reg-names = "dram0", "dram1",
2171 compatible = "ti,pruss-cfg", "syscon";
2173 #address-cells = <1>;
2174 #size-cells = <1>;
2178 #address-cells = <1>;
2179 #size-cells = <0>;
2181 icssg0_coreclk_mux: coreclk-mux@3c {
2183 #clock-cells = <0>;
2186 assigned-clocks = <&icssg0_coreclk_mux>;
2187 assigned-clock-parents = <&k3_clks 119 1>;
2190 icssg0_iepclk_mux: iepclk-mux@30 {
2192 #clock-cells = <0>;
2195 assigned-clocks = <&icssg0_iepclk_mux>;
2196 assigned-clock-parents = <&icssg0_coreclk_mux>;
2201 icssg0_mii_rt: mii-rt@32000 {
2202 compatible = "ti,pruss-mii", "syscon";
2206 icssg0_mii_g_rt: mii-g-rt@33000 {
2207 compatible = "ti,pruss-mii-g", "syscon";
2211 icssg0_intc: interrupt-controller@20000 {
2212 compatible = "ti,icssg-intc";
2214 interrupt-controller;
2215 #interrupt-cells = <3>;
2224 interrupt-names = "host_intr0", "host_intr1",
2231 compatible = "ti,j721e-pru";
2235 reg-names = "iram", "control", "debug";
2236 firmware-name = "j7-pru0_0-fw";
2240 compatible = "ti,j721e-rtu";
2244 reg-names = "iram", "control", "debug";
2245 firmware-name = "j7-rtu0_0-fw";
2249 compatible = "ti,j721e-tx-pru";
2253 reg-names = "iram", "control", "debug";
2254 firmware-name = "j7-txpru0_0-fw";
2258 compatible = "ti,j721e-pru";
2262 reg-names = "iram", "control", "debug";
2263 firmware-name = "j7-pru0_1-fw";
2267 compatible = "ti,j721e-rtu";
2271 reg-names = "iram", "control", "debug";
2272 firmware-name = "j7-rtu0_1-fw";
2276 compatible = "ti,j721e-tx-pru";
2280 reg-names = "iram", "control", "debug";
2281 firmware-name = "j7-txpru0_1-fw";
2288 clock-names = "fck";
2289 #address-cells = <1>;
2290 #size-cells = <0>;
2297 compatible = "ti,j721e-icssg";
2299 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
2300 #address-cells = <1>;
2301 #size-cells = <1>;
2308 reg-names = "dram0", "dram1",
2313 compatible = "ti,pruss-cfg", "syscon";
2315 #address-cells = <1>;
2316 #size-cells = <1>;
2320 #address-cells = <1>;
2321 #size-cells = <0>;
2323 icssg1_coreclk_mux: coreclk-mux@3c {
2325 #clock-cells = <0>;
2328 assigned-clocks = <&icssg1_coreclk_mux>;
2329 assigned-clock-parents = <&k3_clks 120 4>;
2332 icssg1_iepclk_mux: iepclk-mux@30 {
2334 #clock-cells = <0>;
2337 assigned-clocks = <&icssg1_iepclk_mux>;
2338 assigned-clock-parents = <&icssg1_coreclk_mux>;
2343 icssg1_mii_rt: mii-rt@32000 {
2344 compatible = "ti,pruss-mii", "syscon";
2348 icssg1_mii_g_rt: mii-g-rt@33000 {
2349 compatible = "ti,pruss-mii-g", "syscon";
2353 icssg1_intc: interrupt-controller@20000 {
2354 compatible = "ti,icssg-intc";
2356 interrupt-controller;
2357 #interrupt-cells = <3>;
2366 interrupt-names = "host_intr0", "host_intr1",
2373 compatible = "ti,j721e-pru";
2377 reg-names = "iram", "control", "debug";
2378 firmware-name = "j7-pru1_0-fw";
2382 compatible = "ti,j721e-rtu";
2386 reg-names = "iram", "control", "debug";
2387 firmware-name = "j7-rtu1_0-fw";
2391 compatible = "ti,j721e-tx-pru";
2395 reg-names = "iram", "control", "debug";
2396 firmware-name = "j7-txpru1_0-fw";
2400 compatible = "ti,j721e-pru";
2404 reg-names = "iram", "control", "debug";
2405 firmware-name = "j7-pru1_1-fw";
2409 compatible = "ti,j721e-rtu";
2413 reg-names = "iram", "control", "debug";
2414 firmware-name = "j7-rtu1_1-fw";
2418 compatible = "ti,j721e-tx-pru";
2422 reg-names = "iram", "control", "debug";
2423 firmware-name = "j7-txpru1_1-fw";
2430 clock-names = "fck";
2431 #address-cells = <1>;
2432 #size-cells = <0>;
2442 reg-names = "m_can", "message_ram";
2443 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
2445 clock-names = "hclk", "cclk";
2448 interrupt-names = "int0", "int1";
2449 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2457 reg-names = "m_can", "message_ram";
2458 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
2460 clock-names = "hclk", "cclk";
2463 interrupt-names = "int0", "int1";
2464 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2472 reg-names = "m_can", "message_ram";
2473 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
2475 clock-names = "hclk", "cclk";
2478 interrupt-names = "int0", "int1";
2479 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2487 reg-names = "m_can", "message_ram";
2488 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
2490 clock-names = "hclk", "cclk";
2493 interrupt-names = "int0", "int1";
2494 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2502 reg-names = "m_can", "message_ram";
2503 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
2505 clock-names = "hclk", "cclk";
2508 interrupt-names = "int0", "int1";
2509 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2517 reg-names = "m_can", "message_ram";
2518 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
2520 clock-names = "hclk", "cclk";
2523 interrupt-names = "int0", "int1";
2524 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2532 reg-names = "m_can", "message_ram";
2533 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
2535 clock-names = "hclk", "cclk";
2538 interrupt-names = "int0", "int1";
2539 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2547 reg-names = "m_can", "message_ram";
2548 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
2550 clock-names = "hclk", "cclk";
2553 interrupt-names = "int0", "int1";
2554 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2562 reg-names = "m_can", "message_ram";
2563 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
2565 clock-names = "hclk", "cclk";
2568 interrupt-names = "int0", "int1";
2569 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2577 reg-names = "m_can", "message_ram";
2578 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
2580 clock-names = "hclk", "cclk";
2583 interrupt-names = "int0", "int1";
2584 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2592 reg-names = "m_can", "message_ram";
2593 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
2595 clock-names = "hclk", "cclk";
2598 interrupt-names = "int0", "int1";
2599 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2607 reg-names = "m_can", "message_ram";
2608 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
2610 clock-names = "hclk", "cclk";
2613 interrupt-names = "int0", "int1";
2614 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2622 reg-names = "m_can", "message_ram";
2623 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
2625 clock-names = "hclk", "cclk";
2628 interrupt-names = "int0", "int1";
2629 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2637 reg-names = "m_can", "message_ram";
2638 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
2640 clock-names = "hclk", "cclk";
2643 interrupt-names = "int0", "int1";
2644 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2649 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2652 #address-cells = <1>;
2653 #size-cells = <0>;
2654 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
2660 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2663 #address-cells = <1>;
2664 #size-cells = <0>;
2665 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
2671 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2674 #address-cells = <1>;
2675 #size-cells = <0>;
2676 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
2682 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2685 #address-cells = <1>;
2686 #size-cells = <0>;
2687 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
2693 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2696 #address-cells = <1>;
2697 #size-cells = <0>;
2698 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
2704 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2707 #address-cells = <1>;
2708 #size-cells = <0>;
2709 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
2715 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2718 #address-cells = <1>;
2719 #size-cells = <0>;
2720 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
2726 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2729 #address-cells = <1>;
2730 #size-cells = <0>;
2731 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
2737 compatible = "ti,j721e-esm";
2739 ti,esm-pins = <344>, <345>;