Lines Matching +full:0 +full:x04ad0000
15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
49 reg = <0x00004080 0x50>;
51 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
52 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
53 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
54 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
55 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
68 reg = <0x4044 0x20>;
75 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
76 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
81 reg = <0x4140 0x18>;
89 reg = <0x00 0x3000000 0x00 0x100>;
91 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
99 reg = <0x00 0x3010000 0x00 0x100>;
101 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
109 reg = <0x00 0x3020000 0x00 0x100>;
111 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
119 reg = <0x00 0x3030000 0x00 0x100>;
121 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
129 reg = <0x00 0x3040000 0x00 0x100>;
131 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
139 reg = <0x00 0x3050000 0x00 0x100>;
141 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
153 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
154 <0x00 0x01900000 0x00 0x100000>, /* GICR */
155 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
156 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
157 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
164 reg = <0x00 0x01820000 0x00 0x10000>;
165 socionext,synquacer-pre-its = <0x1000000 0x400000>;
173 reg = <0x00 0x00a00000 0x00 0x800>;
187 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
195 reg = <0x0 0x310e0000 0x0 0x4000>;
202 ti,interrupt-ranges = <0 64 64>,
209 reg = <0x0 0x33d00000 0x0 0x100000>;
213 #interrupt-cells = <0>;
216 ti,interrupt-ranges = <0 0 256>;
223 reg = <0x00 0x32c00000 0x00 0x100000>,
224 <0x00 0x32400000 0x00 0x100000>,
225 <0x00 0x32800000 0x00 0x100000>;
232 reg = <0x0 0x36600000 0x0 0x100000>;
242 reg = <0x00 0x30e00000 0x00 0x1000>;
248 reg = <0x00 0x31f80000 0x00 0x200>;
258 reg = <0x00 0x31f81000 0x00 0x200>;
268 reg = <0x00 0x31f82000 0x00 0x200>;
278 reg = <0x00 0x31f83000 0x00 0x200>;
288 reg = <0x00 0x31f84000 0x00 0x200>;
298 reg = <0x00 0x31f85000 0x00 0x200>;
308 reg = <0x00 0x31f86000 0x00 0x200>;
318 reg = <0x00 0x31f87000 0x00 0x200>;
328 reg = <0x00 0x31f88000 0x00 0x200>;
338 reg = <0x00 0x31f89000 0x00 0x200>;
348 reg = <0x00 0x31f8a000 0x00 0x200>;
358 reg = <0x00 0x31f8b000 0x00 0x200>;
368 reg = <0x0 0x3c000000 0x0 0x400000>,
369 <0x0 0x38000000 0x0 0x400000>,
370 <0x0 0x31120000 0x0 0x100>,
371 <0x0 0x33000000 0x0 0x40000>,
372 <0x0 0x31080000 0x0 0x40000>;
375 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
383 reg = <0x0 0x31150000 0x0 0x100>,
384 <0x0 0x34000000 0x0 0x100000>,
385 <0x0 0x35000000 0x0 0x100000>;
394 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
395 <0x0f>, /* TX_HCHAN */
396 <0x10>; /* TX_UHCHAN */
397 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
398 <0x0b>, /* RX_HCHAN */
399 <0x0c>; /* RX_UHCHAN */
400 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
405 reg = <0x0 0x310d0000 0x0 0x400>;
420 reg = <0x0 0xc000000 0x0 0x200000>;
422 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
427 dmas = <&main_udmap 0xca00>,
428 <&main_udmap 0xca01>,
429 <&main_udmap 0xca02>,
430 <&main_udmap 0xca03>,
431 <&main_udmap 0xca04>,
432 <&main_udmap 0xca05>,
433 <&main_udmap 0xca06>,
434 <&main_udmap 0xca07>,
435 <&main_udmap 0x4a00>;
444 #size-cells = <0>;
504 reg = <0x0 0xf00 0x0 0x100>;
506 #size-cells = <0>;
515 reg = <0x0 0x3d000 0x0 0x400>;
527 reg = <0x0 0x4e00000 0x0 0x1200>;
531 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
533 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
534 <&main_udmap 0x4001>;
539 reg = <0x0 0x4e10000 0x0 0x7d>;
546 /* Proxy 0 addressing */
547 reg = <0x0 0x11c000 0x0 0x2b4>;
550 pinctrl-single,function-mask = <0xffffffff>;
556 reg = <0x00 0x104200 0x00 0x50>;
559 pinctrl-single,function-mask = <0x00000007>;
565 reg = <0x00 0x104280 0x00 0x20>;
568 pinctrl-single,function-mask = <0x0000001f>;
578 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
582 ranges = <0x5000000 0x0 0x5000000 0x10000>;
586 #clock-cells = <0>;
592 clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
593 #clock-cells = <0>;
595 assigned-clock-parents = <&k3_clks 292 0>;
599 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
600 #clock-cells = <0>;
607 #clock-cells = <0>;
612 #clock-cells = <0>;
618 reg = <0x5000000 0x10000>;
620 #size-cells = <0>;
622 resets = <&serdes_wiz0 0>;
638 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
642 ranges = <0x5010000 0x0 0x5010000 0x10000>;
646 #clock-cells = <0>;
652 clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
653 #clock-cells = <0>;
655 assigned-clock-parents = <&k3_clks 293 0>;
659 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
660 #clock-cells = <0>;
667 #clock-cells = <0>;
672 #clock-cells = <0>;
678 reg = <0x5010000 0x10000>;
680 #size-cells = <0>;
682 resets = <&serdes_wiz1 0>;
698 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
702 ranges = <0x5020000 0x0 0x5020000 0x10000>;
706 #clock-cells = <0>;
712 clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
713 #clock-cells = <0>;
715 assigned-clock-parents = <&k3_clks 294 0>;
719 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
720 #clock-cells = <0>;
727 #clock-cells = <0>;
732 #clock-cells = <0>;
738 reg = <0x5020000 0x10000>;
740 #size-cells = <0>;
742 resets = <&serdes_wiz2 0>;
758 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
762 ranges = <0x5030000 0x0 0x5030000 0x10000>;
766 #clock-cells = <0>;
772 clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
773 #clock-cells = <0>;
775 assigned-clock-parents = <&k3_clks 295 0>;
779 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
780 #clock-cells = <0>;
787 #clock-cells = <0>;
792 #clock-cells = <0>;
798 reg = <0x5030000 0x10000>;
800 #size-cells = <0>;
802 resets = <&serdes_wiz3 0>;
813 reg = <0x00 0x02900000 0x00 0x1000>,
814 <0x00 0x02907000 0x00 0x400>,
815 <0x00 0x0d000000 0x00 0x00800000>,
816 <0x00 0x10000000 0x00 0x00001000>;
821 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
829 bus-range = <0x0 0xff>;
830 vendor-id = <0x104c>;
831 device-id = <0xb00d>;
832 msi-map = <0x0 &gic_its 0x0 0x10000>;
834 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
835 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
836 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
842 reg = <0x00 0x02910000 0x00 0x1000>,
843 <0x00 0x02917000 0x00 0x400>,
844 <0x00 0x0d800000 0x00 0x00800000>,
845 <0x00 0x18000000 0x00 0x00001000>;
850 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
858 bus-range = <0x0 0xff>;
859 vendor-id = <0x104c>;
860 device-id = <0xb00d>;
861 msi-map = <0x0 &gic_its 0x10000 0x10000>;
863 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
864 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
865 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
871 reg = <0x00 0x02920000 0x00 0x1000>,
872 <0x00 0x02927000 0x00 0x400>,
873 <0x00 0x0e000000 0x00 0x00800000>,
874 <0x44 0x00000000 0x00 0x00001000>;
879 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
887 bus-range = <0x0 0xff>;
888 vendor-id = <0x104c>;
889 device-id = <0xb00d>;
890 msi-map = <0x0 &gic_its 0x20000 0x10000>;
892 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
893 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
894 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
900 reg = <0x00 0x02930000 0x00 0x1000>,
901 <0x00 0x02937000 0x00 0x400>,
902 <0x00 0x0e800000 0x00 0x00800000>,
903 <0x44 0x10000000 0x00 0x00001000>;
908 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
916 bus-range = <0x0 0xff>;
917 vendor-id = <0x104c>;
918 device-id = <0xb00d>;
919 msi-map = <0x0 &gic_its 0x30000 0x10000>;
921 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
922 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
923 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
940 ranges = <0x05050000 0x00 0x05050000 0x010000>,
941 <0x0a030a00 0x00 0x0a030a00 0x40>;
949 reg = <0x05050000 0x010000>,
950 <0x0a030a00 0x40>; /* DPTX PHY */
953 resets = <&serdes_wiz4 0>;
964 #size-cells = <0>;
970 reg = <0x00 0x2400000 0x00 0x400>;
982 reg = <0x00 0x2410000 0x00 0x400>;
986 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
994 reg = <0x00 0x2420000 0x00 0x400>;
1006 reg = <0x00 0x2430000 0x00 0x400>;
1010 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1018 reg = <0x00 0x2440000 0x00 0x400>;
1030 reg = <0x00 0x2450000 0x00 0x400>;
1034 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1042 reg = <0x00 0x2460000 0x00 0x400>;
1054 reg = <0x00 0x2470000 0x00 0x400>;
1058 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1066 reg = <0x00 0x2480000 0x00 0x400>;
1078 reg = <0x00 0x2490000 0x00 0x400>;
1082 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1090 reg = <0x00 0x24a0000 0x00 0x400>;
1102 reg = <0x00 0x24b0000 0x00 0x400>;
1106 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1114 reg = <0x00 0x24c0000 0x00 0x400>;
1126 reg = <0x00 0x24d0000 0x00 0x400>;
1130 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1138 reg = <0x00 0x24e0000 0x00 0x400>;
1150 reg = <0x00 0x24f0000 0x00 0x400>;
1154 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1162 reg = <0x00 0x2500000 0x00 0x400>;
1174 reg = <0x00 0x2510000 0x00 0x400>;
1178 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1186 reg = <0x00 0x2520000 0x00 0x400>;
1198 reg = <0x00 0x2530000 0x00 0x400>;
1202 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1210 reg = <0x00 0x02800000 0x00 0x100>;
1215 clocks = <&k3_clks 146 0>;
1222 reg = <0x00 0x02810000 0x00 0x100>;
1227 clocks = <&k3_clks 278 0>;
1234 reg = <0x00 0x02820000 0x00 0x100>;
1239 clocks = <&k3_clks 279 0>;
1246 reg = <0x00 0x02830000 0x00 0x100>;
1251 clocks = <&k3_clks 280 0>;
1258 reg = <0x00 0x02840000 0x00 0x100>;
1263 clocks = <&k3_clks 281 0>;
1270 reg = <0x00 0x02850000 0x00 0x100>;
1275 clocks = <&k3_clks 282 0>;
1282 reg = <0x00 0x02860000 0x00 0x100>;
1287 clocks = <&k3_clks 283 0>;
1294 reg = <0x00 0x02870000 0x00 0x100>;
1299 clocks = <&k3_clks 284 0>;
1306 reg = <0x00 0x02880000 0x00 0x100>;
1311 clocks = <&k3_clks 285 0>;
1318 reg = <0x00 0x02890000 0x00 0x100>;
1323 clocks = <&k3_clks 286 0>;
1330 reg = <0x0 0x00600000 0x0 0x100>;
1339 ti,davinci-gpio-unbanked = <0>;
1341 clocks = <&k3_clks 105 0>;
1348 reg = <0x0 0x00601000 0x0 0x100>;
1356 ti,davinci-gpio-unbanked = <0>;
1358 clocks = <&k3_clks 106 0>;
1365 reg = <0x0 0x00610000 0x0 0x100>;
1374 ti,davinci-gpio-unbanked = <0>;
1376 clocks = <&k3_clks 107 0>;
1383 reg = <0x0 0x00611000 0x0 0x100>;
1391 ti,davinci-gpio-unbanked = <0>;
1393 clocks = <&k3_clks 108 0>;
1400 reg = <0x0 0x00620000 0x0 0x100>;
1409 ti,davinci-gpio-unbanked = <0>;
1411 clocks = <&k3_clks 109 0>;
1418 reg = <0x0 0x00621000 0x0 0x100>;
1426 ti,davinci-gpio-unbanked = <0>;
1428 clocks = <&k3_clks 110 0>;
1435 reg = <0x0 0x00630000 0x0 0x100>;
1444 ti,davinci-gpio-unbanked = <0>;
1446 clocks = <&k3_clks 111 0>;
1453 reg = <0x0 0x00631000 0x0 0x100>;
1461 ti,davinci-gpio-unbanked = <0>;
1463 clocks = <&k3_clks 112 0>;
1470 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1474 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1480 ti,otap-del-sel-legacy = <0x0>;
1481 ti,otap-del-sel-mmc-hs = <0x0>;
1482 ti,otap-del-sel-ddr52 = <0x5>;
1483 ti,otap-del-sel-hs200 = <0x6>;
1484 ti,otap-del-sel-hs400 = <0x0>;
1485 ti,itap-del-sel-legacy = <0x10>;
1486 ti,itap-del-sel-mmc-hs = <0xa>;
1487 ti,itap-del-sel-ddr52 = <0x3>;
1488 ti,trm-icp = <0x8>;
1495 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1499 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1500 assigned-clocks = <&k3_clks 92 0>;
1502 ti,otap-del-sel-legacy = <0x0>;
1503 ti,otap-del-sel-sd-hs = <0x0>;
1504 ti,otap-del-sel-sdr12 = <0xf>;
1505 ti,otap-del-sel-sdr25 = <0xf>;
1506 ti,otap-del-sel-sdr50 = <0xc>;
1507 ti,otap-del-sel-ddr50 = <0xc>;
1508 ti,otap-del-sel-sdr104 = <0x5>;
1509 ti,itap-del-sel-legacy = <0x0>;
1510 ti,itap-del-sel-sd-hs = <0x0>;
1511 ti,itap-del-sel-sdr12 = <0x0>;
1512 ti,itap-del-sel-sdr25 = <0x0>;
1513 ti,itap-del-sel-ddr50 = <0x2>;
1514 ti,trm-icp = <0x8>;
1515 ti,clkbuf-sel = <0x7>;
1517 sdhci-caps-mask = <0x2 0x0>;
1523 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1527 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1528 assigned-clocks = <&k3_clks 93 0>;
1530 ti,otap-del-sel-legacy = <0x0>;
1531 ti,otap-del-sel-sd-hs = <0x0>;
1532 ti,otap-del-sel-sdr12 = <0xf>;
1533 ti,otap-del-sel-sdr25 = <0xf>;
1534 ti,otap-del-sel-sdr50 = <0xc>;
1535 ti,otap-del-sel-ddr50 = <0xc>;
1536 ti,otap-del-sel-sdr104 = <0x5>;
1537 ti,itap-del-sel-legacy = <0x0>;
1538 ti,itap-del-sel-sd-hs = <0x0>;
1539 ti,itap-del-sel-sdr12 = <0x0>;
1540 ti,itap-del-sel-sdr25 = <0x0>;
1541 ti,itap-del-sel-ddr50 = <0x2>;
1542 ti,trm-icp = <0x8>;
1543 ti,clkbuf-sel = <0x7>;
1545 sdhci-caps-mask = <0x2 0x0>;
1551 reg = <0x00 0x4104000 0x00 0x100>;
1564 reg = <0x00 0x6000000 0x00 0x10000>,
1565 <0x00 0x6010000 0x00 0x10000>,
1566 <0x00 0x6020000 0x00 0x10000>;
1568 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1570 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1581 reg = <0x00 0x4114000 0x00 0x100>;
1594 reg = <0x00 0x6400000 0x00 0x10000>,
1595 <0x00 0x6410000 0x00 0x10000>,
1596 <0x00 0x6420000 0x00 0x10000>;
1598 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1600 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1611 reg = <0x0 0x2000000 0x0 0x100>;
1614 #size-cells = <0>;
1616 clocks = <&k3_clks 187 0>;
1623 reg = <0x0 0x2010000 0x0 0x100>;
1626 #size-cells = <0>;
1628 clocks = <&k3_clks 188 0>;
1635 reg = <0x0 0x2020000 0x0 0x100>;
1638 #size-cells = <0>;
1640 clocks = <&k3_clks 189 0>;
1647 reg = <0x0 0x2030000 0x0 0x100>;
1650 #size-cells = <0>;
1652 clocks = <&k3_clks 190 0>;
1659 reg = <0x0 0x2040000 0x0 0x100>;
1662 #size-cells = <0>;
1664 clocks = <&k3_clks 191 0>;
1671 reg = <0x0 0x2050000 0x0 0x100>;
1674 #size-cells = <0>;
1676 clocks = <&k3_clks 192 0>;
1683 reg = <0x0 0x2060000 0x0 0x100>;
1686 #size-cells = <0>;
1688 clocks = <&k3_clks 193 0>;
1695 reg = <0x0 0x4e80000 0x0 0x100>;
1706 reg = <0x0 0x4e84000 0x0 0x10000>;
1709 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1721 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
1722 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
1734 #size-cells = <0>;
1736 port@0 {
1737 reg = <0>;
1749 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1750 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1751 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1752 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1754 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1755 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1756 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1757 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1759 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1760 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1761 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1762 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1764 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1765 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1766 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1767 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1768 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1777 clocks = <&k3_clks 152 0>,
1801 reg = <0x0 0x02b00000 0x0 0x2000>,
1802 <0x0 0x02b08000 0x0 0x1000>;
1808 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1819 reg = <0x0 0x02b10000 0x0 0x2000>,
1820 <0x0 0x02b18000 0x0 0x1000>;
1826 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1837 reg = <0x0 0x02b20000 0x0 0x2000>,
1838 <0x0 0x02b28000 0x0 0x1000>;
1844 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1855 reg = <0x0 0x02b30000 0x0 0x2000>,
1856 <0x0 0x02b38000 0x0 0x1000>;
1862 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1873 reg = <0x0 0x02b40000 0x0 0x2000>,
1874 <0x0 0x02b48000 0x0 0x1000>;
1880 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1891 reg = <0x0 0x02b50000 0x0 0x2000>,
1892 <0x0 0x02b58000 0x0 0x1000>;
1898 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1909 reg = <0x0 0x02b60000 0x0 0x2000>,
1910 <0x0 0x02b68000 0x0 0x1000>;
1916 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1927 reg = <0x0 0x02b70000 0x0 0x2000>,
1928 <0x0 0x02b78000 0x0 0x1000>;
1934 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1945 reg = <0x0 0x02b80000 0x0 0x2000>,
1946 <0x0 0x02b88000 0x0 0x1000>;
1952 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1963 reg = <0x0 0x02b90000 0x0 0x2000>,
1964 <0x0 0x02b98000 0x0 0x1000>;
1970 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1981 reg = <0x0 0x02ba0000 0x0 0x2000>,
1982 <0x0 0x02ba8000 0x0 0x1000>;
1988 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1999 reg = <0x0 0x02bb0000 0x0 0x2000>,
2000 <0x0 0x02bb8000 0x0 0x1000>;
2006 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
2017 reg = <0x0 0x2200000 0x0 0x100>;
2026 reg = <0x0 0x2210000 0x0 0x100>;
2038 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
2039 <0x5d00000 0x00 0x5d00000 0x20000>;
2044 reg = <0x5c00000 0x00008000>,
2045 <0x5c10000 0x00008000>;
2049 ti,sci-proc-ids = <0x06 0xff>;
2059 reg = <0x5d00000 0x00008000>,
2060 <0x5d10000 0x00008000>;
2064 ti,sci-proc-ids = <0x07 0xff>;
2078 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
2079 <0x5f00000 0x00 0x5f00000 0x20000>;
2084 reg = <0x5e00000 0x00008000>,
2085 <0x5e10000 0x00008000>;
2089 ti,sci-proc-ids = <0x08 0xff>;
2099 reg = <0x5f00000 0x00008000>,
2100 <0x5f10000 0x00008000>;
2104 ti,sci-proc-ids = <0x09 0xff>;
2115 reg = <0x4d 0x80800000 0x00 0x00048000>,
2116 <0x4d 0x80e00000 0x00 0x00008000>,
2117 <0x4d 0x80f00000 0x00 0x00008000>;
2121 ti,sci-proc-ids = <0x03 0xff>;
2129 reg = <0x4d 0x81800000 0x00 0x00048000>,
2130 <0x4d 0x81e00000 0x00 0x00008000>,
2131 <0x4d 0x81f00000 0x00 0x00008000>;
2135 ti,sci-proc-ids = <0x04 0xff>;
2143 reg = <0x00 0x64800000 0x00 0x00080000>,
2144 <0x00 0x64e00000 0x00 0x0000c000>;
2148 ti,sci-proc-ids = <0x30 0xff>;
2156 reg = <0x00 0xb000000 0x00 0x80000>;
2160 ranges = <0x0 0x00 0x0b000000 0x100000>;
2162 icssg0_mem: memories@0 {
2163 reg = <0x0 0x2000>,
2164 <0x2000 0x2000>,
2165 <0x10000 0x10000>;
2172 reg = <0x26000 0x200>;
2175 ranges = <0x0 0x26000 0x2000>;
2179 #size-cells = <0>;
2182 reg = <0x3c>;
2183 #clock-cells = <0>;
2191 reg = <0x30>;
2192 #clock-cells = <0>;
2203 reg = <0x32000 0x100>;
2208 reg = <0x33000 0x1000>;
2213 reg = <0x20000 0x2000>;
2232 reg = <0x34000 0x3000>,
2233 <0x22000 0x100>,
2234 <0x22400 0x100>;
2241 reg = <0x4000 0x2000>,
2242 <0x23000 0x100>,
2243 <0x23400 0x100>;
2250 reg = <0xa000 0x1800>,
2251 <0x25000 0x100>,
2252 <0x25400 0x100>;
2259 reg = <0x38000 0x3000>,
2260 <0x24000 0x100>,
2261 <0x24400 0x100>;
2268 reg = <0x6000 0x2000>,
2269 <0x23800 0x100>,
2270 <0x23c00 0x100>;
2277 reg = <0xc000 0x1800>,
2278 <0x25800 0x100>,
2279 <0x25c00 0x100>;
2286 reg = <0x32400 0x100>;
2290 #size-cells = <0>;
2298 reg = <0x00 0xb100000 0x00 0x80000>;
2302 ranges = <0x0 0x00 0x0b100000 0x100000>;
2305 reg = <0x0 0x2000>,
2306 <0x2000 0x2000>,
2307 <0x10000 0x10000>;
2314 reg = <0x26000 0x200>;
2317 ranges = <0x0 0x26000 0x2000>;
2321 #size-cells = <0>;
2324 reg = <0x3c>;
2325 #clock-cells = <0>;
2333 reg = <0x30>;
2334 #clock-cells = <0>;
2345 reg = <0x32000 0x100>;
2350 reg = <0x33000 0x1000>;
2355 reg = <0x20000 0x2000>;
2374 reg = <0x34000 0x4000>,
2375 <0x22000 0x100>,
2376 <0x22400 0x100>;
2383 reg = <0x4000 0x2000>,
2384 <0x23000 0x100>,
2385 <0x23400 0x100>;
2392 reg = <0xa000 0x1800>,
2393 <0x25000 0x100>,
2394 <0x25400 0x100>;
2401 reg = <0x38000 0x4000>,
2402 <0x24000 0x100>,
2403 <0x24400 0x100>;
2410 reg = <0x6000 0x2000>,
2411 <0x23800 0x100>,
2412 <0x23c00 0x100>;
2419 reg = <0xc000 0x1800>,
2420 <0x25800 0x100>,
2421 <0x25c00 0x100>;
2428 reg = <0x32400 0x100>;
2432 #size-cells = <0>;
2440 reg = <0x00 0x02701000 0x00 0x200>,
2441 <0x00 0x02708000 0x00 0x8000>;
2444 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
2449 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2455 reg = <0x00 0x02711000 0x00 0x200>,
2456 <0x00 0x02718000 0x00 0x8000>;
2459 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
2464 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2470 reg = <0x00 0x02721000 0x00 0x200>,
2471 <0x00 0x02728000 0x00 0x8000>;
2474 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
2479 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2485 reg = <0x00 0x02731000 0x00 0x200>,
2486 <0x00 0x02738000 0x00 0x8000>;
2489 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
2494 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2500 reg = <0x00 0x02741000 0x00 0x200>,
2501 <0x00 0x02748000 0x00 0x8000>;
2504 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
2509 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2515 reg = <0x00 0x02751000 0x00 0x200>,
2516 <0x00 0x02758000 0x00 0x8000>;
2519 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
2524 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2530 reg = <0x00 0x02761000 0x00 0x200>,
2531 <0x00 0x02768000 0x00 0x8000>;
2534 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
2539 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2545 reg = <0x00 0x02771000 0x00 0x200>,
2546 <0x00 0x02778000 0x00 0x8000>;
2549 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
2554 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2560 reg = <0x00 0x02781000 0x00 0x200>,
2561 <0x00 0x02788000 0x00 0x8000>;
2564 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
2569 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2575 reg = <0x00 0x02791000 0x00 0x200>,
2576 <0x00 0x02798000 0x00 0x8000>;
2579 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
2584 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2590 reg = <0x00 0x027a1000 0x00 0x200>,
2591 <0x00 0x027a8000 0x00 0x8000>;
2594 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
2599 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2605 reg = <0x00 0x027b1000 0x00 0x200>,
2606 <0x00 0x027b8000 0x00 0x8000>;
2609 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
2614 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2620 reg = <0x00 0x027c1000 0x00 0x200>,
2621 <0x00 0x027c8000 0x00 0x8000>;
2624 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
2629 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2635 reg = <0x00 0x027d1000 0x00 0x200>,
2636 <0x00 0x027d8000 0x00 0x8000>;
2639 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
2644 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2650 reg = <0x00 0x02100000 0x00 0x400>;
2653 #size-cells = <0>;
2661 reg = <0x00 0x02110000 0x00 0x400>;
2664 #size-cells = <0>;
2672 reg = <0x00 0x02120000 0x00 0x400>;
2675 #size-cells = <0>;
2683 reg = <0x00 0x02130000 0x00 0x400>;
2686 #size-cells = <0>;
2694 reg = <0x00 0x02140000 0x00 0x400>;
2697 #size-cells = <0>;
2705 reg = <0x00 0x02150000 0x00 0x400>;
2708 #size-cells = <0>;
2716 reg = <0x00 0x02160000 0x00 0x400>;
2719 #size-cells = <0>;
2727 reg = <0x00 0x02170000 0x00 0x400>;
2730 #size-cells = <0>;
2738 reg = <0x0 0x700000 0x0 0x1000>;