dts/ti/k3-j7200-mcu-wakeup.dtsi

1 // SPDX-License-Identifier: GPL-2.0
3  * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 	dmsc: system-controller@44083000 {
10 		compatible = "ti,k2g-sci";
11 		ti,host-id = <12>;
13 		mbox-names = "rx", "tx";
18 		reg-names = "debug_messages";
21 		k3_pds: power-controller {
22 			compatible = "ti,sci-pm-domain";
23 			#power-domain-cells = <2>;
26 		k3_clks: clock-controller {
27 			compatible = "ti,k2g-sci-clk";
28 			#clock-cells = <2>;
31 		k3_reset: reset-controller {
32 			compatible = "ti,sci-reset";
33 			#reset-cells = <2>;
39 		compatible = "ti,am654-timer";
43 		clock-names = "fck";
44 		assigned-clocks = <&k3_clks 35 1>;
45 		assigned-clock-parents = <&k3_clks 35 2>;
46 		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
47 		ti,timer-pwm;
52 		compatible = "ti,am654-timer";
56 		clock-names = "fck";
57 		assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
58 		assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
59 		power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
60 		ti,timer-pwm;
65 		compatible = "ti,am654-timer";
69 		clock-names = "fck";
70 		assigned-clocks = <&k3_clks 72 1>;
71 		assigned-clock-parents = <&k3_clks 72 2>;
72 		power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
73 		ti,timer-pwm;
78 		compatible = "ti,am654-timer";
82 		clock-names = "fck";
83 		assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
84 		assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
85 		power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
86 		ti,timer-pwm;
91 		compatible = "ti,am654-timer";
95 		clock-names = "fck";
96 		assigned-clocks = <&k3_clks 74 1>;
97 		assigned-clock-parents = <&k3_clks 74 2>;
98 		power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
99 		ti,timer-pwm;
104 		compatible = "ti,am654-timer";
108 		clock-names = "fck";
109 		assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
110 		assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>;
111 		power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
112 		ti,timer-pwm;
117 		compatible = "ti,am654-timer";
121 		clock-names = "fck";
122 		assigned-clocks = <&k3_clks 76 1>;
123 		assigned-clock-parents = <&k3_clks 76 2>;
124 		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
125 		ti,timer-pwm;
130 		compatible = "ti,am654-timer";
134 		clock-names = "fck";
135 		assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
136 		assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>;
137 		power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
138 		ti,timer-pwm;
143 		compatible = "ti,am654-timer";
147 		clock-names = "fck";
148 		assigned-clocks = <&k3_clks 78 1>;
149 		assigned-clock-parents = <&k3_clks 78 2>;
150 		power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
151 		ti,timer-pwm;
156 		compatible = "ti,am654-timer";
160 		clock-names = "fck";
161 		assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
162 		assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>;
163 		power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
164 		ti,timer-pwm;
168 		compatible = "syscon", "simple-mfd";
170 		#address-cells = <1>;
171 		#size-cells = <1>;
175 			compatible = "ti,am654-phy-gmii-sel";
177 			#phy-cells = <1>;
182 		compatible = "ti,am654-chipid";
188 		compatible = "ti,j7200-padconf", "pinctrl-single";
190 		#pinctrl-cells = <1>;
191 		pinctrl-single,register-width = <32>;
192 		pinctrl-single,function-mask = <0x0000000F>;
198 		compatible = "ti,j7200-padconf", "pinctrl-single";
200 		#pinctrl-cells = <1>;
201 		pinctrl-single,register-width = <32>;
202 		pinctrl-single,function-mask = <0x0000000F>;
207 		compatible = "ti,j7200-padconf", "pinctrl-single";
210 		#pinctrl-cells = <1>;
211 		pinctrl-single,register-width = <32>;
212 		pinctrl-single,function-mask = <0xffffffff>;
216 		compatible = "ti,j7200-padconf", "pinctrl-single";
219 		#pinctrl-cells = <1>;
220 		pinctrl-single,register-width = <32>;
221 		pinctrl-single,function-mask = <0xffffffff>;
225 		compatible = "ti,j7200-padconf", "pinctrl-single";
228 		#pinctrl-cells = <1>;
229 		pinctrl-single,register-width = <32>;
230 		pinctrl-single,function-mask = <0xffffffff>;
234 		compatible = "ti,j7200-padconf", "pinctrl-single";
237 		#pinctrl-cells = <1>;
238 		pinctrl-single,register-width = <32>;
239 		pinctrl-single,function-mask = <0xffffffff>;
243 		compatible = "mmio-sram";
246 		#address-cells = <1>;
247 		#size-cells = <1>;
251 		compatible = "ti,j721e-uart", "ti,am654-uart";
254 		clock-frequency = <48000000>;
255 		current-speed = <115200>;
256 		power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
258 		clock-names = "fclk";
263 		compatible = "ti,j721e-uart", "ti,am654-uart";
266 		clock-frequency = <96000000>;
267 		current-speed = <115200>;
268 		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
270 		clock-names = "fclk";
274 	wkup_gpio_intr: interrupt-controller@42200000 {
275 		compatible = "ti,sci-intr";
277 		ti,intr-trigger-type = <1>;
278 		interrupt-controller;
279 		interrupt-parent = <&gic500>;
280 		#interrupt-cells = <1>;
281 		ti,sci = <&dmsc>;
282 		ti,sci-dev-id = <137>;
283 		ti,interrupt-ranges = <16 960 16>;
287 		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
289 		gpio-controller;
290 		#gpio-cells = <2>;
291 		interrupt-parent = <&wkup_gpio_intr>;
293 		interrupt-controller;
294 		#interrupt-cells = <2>;
296 		ti,davinci-gpio-unbanked = <0>;
297 		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
299 		clock-names = "gpio";
304 		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
306 		gpio-controller;
307 		#gpio-cells = <2>;
308 		interrupt-parent = <&wkup_gpio_intr>;
310 		interrupt-controller;
311 		#interrupt-cells = <2>;
313 		ti,davinci-gpio-unbanked = <0>;
314 		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
316 		clock-names = "gpio";
321 		compatible = "simple-mfd";
322 		#address-cells = <2>;
323 		#size-cells = <2>;
325 		dma-coherent;
326 		dma-ranges;
327 		ti,sci-dev-id = <232>;
330 			compatible = "ti,am654-navss-ringacc";
336 			reg-names = "rt", "fifos", "proxy_gcfg",
338 			ti,num-rings = <286>;
339 			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
340 			ti,sci = <&dmsc>;
341 			ti,sci-dev-id = <235>;
342 			msi-parent = <&main_udmass_inta>;
345 		mcu_udmap: dma-controller@285c0000 {
346 			compatible = "ti,j721e-navss-mcu-udmap";
350 			reg-names = "gcfg", "rchanrt", "tchanrt";
351 			msi-parent = <&main_udmass_inta>;
352 			#dma-cells = <1>;
354 			ti,sci = <&dmsc>;
355 			ti,sci-dev-id = <236>;
358 			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
360 			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
362 			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
367 		compatible = "ti,am654-secure-proxy";
368 		#mbox-cells = <1>;
369 		reg-names = "target_data", "rt", "scfg";
376 		 * firmware on non-MPU processors
382 		compatible = "ti,j721e-cpsw-nuss";
383 		#address-cells = <2>;
384 		#size-cells = <2>;
386 		reg-names = "cpsw_nuss";
388 		dma-coherent;
390 		clock-names = "fck";
391 		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
402 		dma-names = "tx0", "tx1", "tx2", "tx3",
406 		ethernet-ports {
407 			#address-cells = <1>;
408 			#size-cells = <0>;
412 				ti,mac-only;
414 				ti,syscon-efuse = <&mcu_conf 0x200>;
420 			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
422 			#address-cells = <1>;
423 			#size-cells = <0>;
425 			clock-names = "fck";
430 			compatible = "ti,am65-cpts";
433 			clock-names = "cpts";
434 			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
435 			interrupt-names = "cpts";
436 			ti,cpts-ext-ts-inputs = <4>;
437 			ti,cpts-periodic-outputs = <2>;
442 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
445 		#address-cells = <1>;
446 		#size-cells = <0>;
447 		clock-names = "fck";
449 		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
454 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
457 		#address-cells = <1>;
458 		#size-cells = <0>;
459 		clock-names = "fck";
461 		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
466 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
469 		#address-cells = <1>;
470 		#size-cells = <0>;
471 		clock-names = "fck";
473 		power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
478 		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
481 		#address-cells = <1>;
482 		#size-cells = <0>;
483 		power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
489 		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
492 		#address-cells = <1>;
493 		#size-cells = <0>;
494 		power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
500 		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
503 		#address-cells = <1>;
504 		#size-cells = <0>;
505 		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
511 		compatible = "syscon", "simple-mfd";
513 		#address-cells = <2>;
514 		#size-cells = <2>;
517 		hbmc_mux: hbmc-mux {
518 			compatible = "mmio-mux";
519 			#mux-control-cells = <1>;
520 			mux-reg-masks = <0x4 0x2>; /* HBMC select */
524 			compatible = "ti,am654-hbmc";
527 			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
529 			assigned-clocks = <&k3_clks 102 5>;
530 			assigned-clock-rates = <333333333>;
531 			#address-cells = <2>;
532 			#size-cells = <1>;
533 			mux-controls = <&hbmc_mux 0>;
537 			compatible = "ti,am654-ospi", "cdns,qspi-nor";
541 			cdns,fifo-depth = <256>;
542 			cdns,fifo-width = <4>;
543 			cdns,trigger-address = <0x0>;
545 			assigned-clocks = <&k3_clks 103 0>;
546 			assigned-clock-parents = <&k3_clks 103 2>;
547 			assigned-clock-rates = <166666666>;
548 			power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
549 			#address-cells = <1>;
550 			#size-cells = <0>;
556 		compatible = "ti,am3359-tscadc";
559 		power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
561 		assigned-clocks = <&k3_clks 0 3>;
562 		assigned-clock-rates = <60000000>;
563 		clock-names = "fck";
566 		dma-names = "fifo0", "fifo1";
569 			#io-channel-cells = <1>;
570 			compatible = "ti,am3359-adc";
575 		compatible = "ti,j7200-r5fss";
576 		ti,cluster-mode = <1>;
577 		#address-cells = <1>;
578 		#size-cells = <1>;
581 		power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
584 			compatible = "ti,j7200-r5f";
587 			reg-names = "atcm", "btcm";
588 			ti,sci = <&dmsc>;
589 			ti,sci-dev-id = <250>;
590 			ti,sci-proc-ids = <0x01 0xff>;
592 			firmware-name = "j7200-mcu-r5f0_0-fw";
593 			ti,atcm-enable = <1>;
594 			ti,btcm-enable = <1>;
599 			compatible = "ti,j7200-r5f";
602 			reg-names = "atcm", "btcm";
603 			ti,sci = <&dmsc>;
604 			ti,sci-dev-id = <251>;
605 			ti,sci-proc-ids = <0x02 0xff>;
607 			firmware-name = "j7200-mcu-r5f0_1-fw";
608 			ti,atcm-enable = <1>;
609 			ti,btcm-enable = <1>;
615 		compatible = "ti,j721e-sa2ul";
617 		power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
618 		#address-cells = <2>;
619 		#size-cells = <2>;
623 		dma-names = "tx", "rx1", "rx2";
626 			compatible = "inside-secure,safexcel-eip76";
629 			status = "disabled"; /* Used by OP-TEE */
633 	wkup_vtm0: temperature-sensor@42040000 {
634 		compatible = "ti,j7200-vtm";
637 		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
638 		#thermal-sensor-cells = <1>;