Lines Matching +full:0 +full:x43000014
19 reg = <0x00 0x44083000 0x00 0x1000>;
40 reg = <0x00 0x40400000 0x00 0x400>;
53 reg = <0x00 0x40410000 0x00 0x400>;
57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
66 reg = <0x00 0x40420000 0x00 0x400>;
79 reg = <0x00 0x40430000 0x00 0x400>;
83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
92 reg = <0x00 0x40440000 0x00 0x400>;
105 reg = <0x00 0x40450000 0x00 0x400>;
109 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
118 reg = <0x00 0x40460000 0x00 0x400>;
131 reg = <0x00 0x40470000 0x00 0x400>;
135 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
144 reg = <0x00 0x40480000 0x00 0x400>;
157 reg = <0x00 0x40490000 0x00 0x400>;
161 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
169 reg = <0x00 0x40f00000 0x00 0x20000>;
172 ranges = <0x00 0x00 0x40f00000 0x20000>;
176 reg = <0x4040 0x4>;
183 reg = <0x00 0x43000014 0x00 0x4>;
189 reg = <0x0 0x40f04200 0x0 0x28>;
192 pinctrl-single,function-mask = <0x0000000F>;
199 reg = <0x0 0x40f04280 0x0 0x28>;
202 pinctrl-single,function-mask = <0x0000000F>;
208 /* Proxy 0 addressing */
209 reg = <0x00 0x4301c000 0x00 0x34>;
212 pinctrl-single,function-mask = <0xffffffff>;
217 /* Proxy 0 addressing */
218 reg = <0x00 0x4301c038 0x00 0x8>;
221 pinctrl-single,function-mask = <0xffffffff>;
226 /* Proxy 0 addressing */
227 reg = <0x00 0x4301c068 0x00 0xec>;
230 pinctrl-single,function-mask = <0xffffffff>;
235 /* Proxy 0 addressing */
236 reg = <0x00 0x4301c174 0x00 0x20>;
239 pinctrl-single,function-mask = <0xffffffff>;
244 reg = <0x00 0x41c00000 0x00 0x100000>;
245 ranges = <0x00 0x00 0x41c00000 0x100000>;
252 reg = <0x00 0x42300000 0x00 0x100>;
264 reg = <0x00 0x40a00000 0x00 0x100>;
276 reg = <0x00 0x42200000 0x00 0x400>;
288 reg = <0x00 0x42110000 0x00 0x100>;
296 ti,davinci-gpio-unbanked = <0>;
298 clocks = <&k3_clks 113 0>;
305 reg = <0x00 0x42100000 0x00 0x100>;
313 ti,davinci-gpio-unbanked = <0>;
315 clocks = <&k3_clks 114 0>;
324 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
331 reg = <0x00 0x2b800000 0x00 0x400000>,
332 <0x00 0x2b000000 0x00 0x400000>,
333 <0x00 0x28590000 0x00 0x100>,
334 <0x00 0x2a500000 0x00 0x40000>,
335 <0x00 0x28440000 0x00 0x40000>;
339 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
347 reg = <0x00 0x285c0000 0x00 0x100>,
348 <0x00 0x2a800000 0x00 0x40000>,
349 <0x00 0x2aa00000 0x00 0x40000>;
358 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
359 <0x0f>; /* TX_HCHAN */
360 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
361 <0x0b>; /* RX_HCHAN */
362 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
370 reg = <0x0 0x2a480000 0x0 0x80000>,
371 <0x0 0x2a380000 0x0 0x80000>,
372 <0x0 0x2a400000 0x0 0x80000>;
385 reg = <0x00 0x46000000 0x00 0x200000>;
387 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
393 dmas = <&mcu_udmap 0xf000>,
394 <&mcu_udmap 0xf001>,
395 <&mcu_udmap 0xf002>,
396 <&mcu_udmap 0xf003>,
397 <&mcu_udmap 0xf004>,
398 <&mcu_udmap 0xf005>,
399 <&mcu_udmap 0xf006>,
400 <&mcu_udmap 0xf007>,
401 <&mcu_udmap 0x7000>;
408 #size-cells = <0>;
414 ti,syscon-efuse = <&mcu_conf 0x200>;
421 reg = <0x00 0xf00 0x00 0x100>;
423 #size-cells = <0>;
431 reg = <0x00 0x3d000 0x00 0x400>;
443 reg = <0x00 0x40b00000 0x00 0x100>;
446 #size-cells = <0>;
455 reg = <0x00 0x40b10000 0x00 0x100>;
458 #size-cells = <0>;
467 reg = <0x00 0x42120000 0x00 0x100>;
470 #size-cells = <0>;
479 reg = <0x00 0x040300000 0x00 0x400>;
482 #size-cells = <0>;
490 reg = <0x00 0x040310000 0x00 0x400>;
493 #size-cells = <0>;
501 reg = <0x00 0x040320000 0x00 0x400>;
504 #size-cells = <0>;
512 reg = <0x00 0x47000000 0x00 0x100>;
520 mux-reg-masks = <0x4 0x2>; /* HBMC select */
525 reg = <0x00 0x47034000 0x00 0x100>,
526 <0x05 0x00000000 0x01 0x0000000>;
528 clocks = <&k3_clks 102 0>;
533 mux-controls = <&hbmc_mux 0>;
538 reg = <0x0 0x47040000 0x0 0x100>,
539 <0x5 0x00000000 0x1 0x0000000>;
543 cdns,trigger-address = <0x0>;
544 clocks = <&k3_clks 103 0>;
545 assigned-clocks = <&k3_clks 103 0>;
550 #size-cells = <0>;
557 reg = <0x00 0x40200000 0x00 0x1000>;
559 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
560 clocks = <&k3_clks 0 1>;
561 assigned-clocks = <&k3_clks 0 3>;
564 dmas = <&main_udmap 0x7400>,
565 <&main_udmap 0x7401>;
579 ranges = <0x41000000 0x00 0x41000000 0x20000>,
580 <0x41400000 0x00 0x41400000 0x20000>;
585 reg = <0x41000000 0x00010000>,
586 <0x41010000 0x00010000>;
590 ti,sci-proc-ids = <0x01 0xff>;
600 reg = <0x41400000 0x00008000>,
601 <0x41410000 0x00008000>;
605 ti,sci-proc-ids = <0x02 0xff>;
616 reg = <0x00 0x40900000 0x00 0x1200>;
620 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
621 dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
622 <&mcu_udmap 0x7503>;
627 reg = <0x00 0x40910000 0x00 0x7d>;
635 reg = <0x00 0x42040000 0x00 0x350>,
636 <0x00 0x42050000 0x00 0x350>;