Lines Matching +full:omap4 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 serdes_ln_ctrl: mux-controller@4080 {
36 compatible = "mmio-mux";
37 #mux-control-cells = <1>;
38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
43 compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
44 ti,qsgmii-main-ports = <1>;
46 #phy-cells = <1>;
49 usb_serdes_mux: mux-controller@4000 {
50 compatible = "mmio-mux";
51 #mux-control-cells = <1>;
52 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
56 gic500: interrupt-controller@1800000 {
57 compatible = "arm,gic-v3";
58 #address-cells = <2>;
59 #size-cells = <2>;
61 #interrupt-cells = <3>;
62 interrupt-controller;
72 gic_its: msi-controller@1820000 {
73 compatible = "arm,gic-v3-its";
75 socionext,synquacer-pre-its = <0x1000000 0x400000>;
76 msi-controller;
77 #msi-cells = <1>;
81 main_gpio_intr: interrupt-controller@a00000 {
82 compatible = "ti,sci-intr";
84 ti,intr-trigger-type = <1>;
85 interrupt-controller;
86 interrupt-parent = <&gic500>;
87 #interrupt-cells = <1>;
89 ti,sci-dev-id = <131>;
90 ti,interrupt-ranges = <8 392 56>;
94 compatible = "simple-mfd";
95 #address-cells = <2>;
96 #size-cells = <2>;
98 ti,sci-dev-id = <199>;
99 dma-coherent;
100 dma-ranges;
102 main_navss_intr: interrupt-controller@310e0000 {
103 compatible = "ti,sci-intr";
105 ti,intr-trigger-type = <4>;
106 interrupt-controller;
107 interrupt-parent = <&gic500>;
108 #interrupt-cells = <1>;
110 ti,sci-dev-id = <213>;
111 ti,interrupt-ranges = <0 64 64>,
116 main_udmass_inta: msi-controller@33d00000 {
117 compatible = "ti,sci-inta";
119 interrupt-controller;
120 #interrupt-cells = <0>;
121 interrupt-parent = <&main_navss_intr>;
122 msi-controller;
124 ti,sci-dev-id = <209>;
125 ti,interrupt-ranges = <0 0 256>;
129 compatible = "ti,am654-secure-proxy";
130 #mbox-cells = <1>;
131 reg-names = "target_data", "rt", "scfg";
135 interrupt-names = "rx_011";
140 compatible = "ti,am654-hwspinlock";
142 #hwlock-cells = <1>;
146 compatible = "ti,am654-mailbox";
148 #mbox-cells = <1>;
149 ti,mbox-num-users = <4>;
150 ti,mbox-num-fifos = <16>;
151 interrupt-parent = <&main_navss_intr>;
156 compatible = "ti,am654-mailbox";
158 #mbox-cells = <1>;
159 ti,mbox-num-users = <4>;
160 ti,mbox-num-fifos = <16>;
161 interrupt-parent = <&main_navss_intr>;
166 compatible = "ti,am654-mailbox";
168 #mbox-cells = <1>;
169 ti,mbox-num-users = <4>;
170 ti,mbox-num-fifos = <16>;
171 interrupt-parent = <&main_navss_intr>;
176 compatible = "ti,am654-mailbox";
178 #mbox-cells = <1>;
179 ti,mbox-num-users = <4>;
180 ti,mbox-num-fifos = <16>;
181 interrupt-parent = <&main_navss_intr>;
186 compatible = "ti,am654-mailbox";
188 #mbox-cells = <1>;
189 ti,mbox-num-users = <4>;
190 ti,mbox-num-fifos = <16>;
191 interrupt-parent = <&main_navss_intr>;
196 compatible = "ti,am654-mailbox";
198 #mbox-cells = <1>;
199 ti,mbox-num-users = <4>;
200 ti,mbox-num-fifos = <16>;
201 interrupt-parent = <&main_navss_intr>;
206 compatible = "ti,am654-mailbox";
208 #mbox-cells = <1>;
209 ti,mbox-num-users = <4>;
210 ti,mbox-num-fifos = <16>;
211 interrupt-parent = <&main_navss_intr>;
216 compatible = "ti,am654-mailbox";
218 #mbox-cells = <1>;
219 ti,mbox-num-users = <4>;
220 ti,mbox-num-fifos = <16>;
221 interrupt-parent = <&main_navss_intr>;
226 compatible = "ti,am654-mailbox";
228 #mbox-cells = <1>;
229 ti,mbox-num-users = <4>;
230 ti,mbox-num-fifos = <16>;
231 interrupt-parent = <&main_navss_intr>;
236 compatible = "ti,am654-mailbox";
238 #mbox-cells = <1>;
239 ti,mbox-num-users = <4>;
240 ti,mbox-num-fifos = <16>;
241 interrupt-parent = <&main_navss_intr>;
246 compatible = "ti,am654-mailbox";
248 #mbox-cells = <1>;
249 ti,mbox-num-users = <4>;
250 ti,mbox-num-fifos = <16>;
251 interrupt-parent = <&main_navss_intr>;
256 compatible = "ti,am654-mailbox";
258 #mbox-cells = <1>;
259 ti,mbox-num-users = <4>;
260 ti,mbox-num-fifos = <16>;
261 interrupt-parent = <&main_navss_intr>;
266 compatible = "ti,am654-navss-ringacc";
272 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
273 ti,num-rings = <1024>;
274 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
276 ti,sci-dev-id = <211>;
277 msi-parent = <&main_udmass_inta>;
280 main_udmap: dma-controller@31150000 {
281 compatible = "ti,j721e-navss-main-udmap";
285 reg-names = "gcfg", "rchanrt", "tchanrt";
286 msi-parent = <&main_udmass_inta>;
287 #dma-cells = <1>;
290 ti,sci-dev-id = <212>;
293 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
296 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
299 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
303 compatible = "ti,j721e-cpts";
305 reg-names = "cpts";
307 clock-names = "cpts";
308 interrupts-extended = <&main_navss_intr 391>;
309 interrupt-names = "cpts";
310 ti,cpts-periodic-outputs = <6>;
311 ti,cpts-ext-ts-inputs = <8>;
316 compatible = "ti,j7200-cpswxg-nuss";
317 #address-cells = <2>;
318 #size-cells = <2>;
320 reg-names = "cpsw_nuss";
323 clock-names = "fck";
324 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
335 dma-names = "tx0", "tx1", "tx2", "tx3",
341 ethernet-ports {
342 #address-cells = <1>;
343 #size-cells = <0>;
346 ti,mac-only;
353 ti,mac-only;
360 ti,mac-only;
367 ti,mac-only;
374 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
376 #address-cells = <1>;
377 #size-cells = <0>;
379 clock-names = "fck";
385 compatible = "ti,j721e-cpts";
388 clock-names = "cpts";
389 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-names = "cpts";
391 ti,cpts-ext-ts-inputs = <4>;
392 ti,cpts-periodic-outputs = <2>;
398 compatible = "ti,j7200-padconf", "pinctrl-single";
400 #pinctrl-cells = <1>;
401 pinctrl-single,register-width = <32>;
402 pinctrl-single,function-mask = <0x000001ff>;
407 compatible = "ti,j7200-padconf", "pinctrl-single";
409 #pinctrl-cells = <1>;
410 pinctrl-single,register-width = <32>;
411 pinctrl-single,function-mask = <0x0000001f>;
415 compatible = "ti,j7200-padconf", "pinctrl-single";
418 #pinctrl-cells = <1>;
419 pinctrl-single,register-width = <32>;
420 pinctrl-single,function-mask = <0xffffffff>;
424 compatible = "ti,j7200-padconf", "pinctrl-single";
427 #pinctrl-cells = <1>;
428 pinctrl-single,register-width = <32>;
429 pinctrl-single,function-mask = <0xffffffff>;
433 compatible = "ti,j7200-padconf", "pinctrl-single";
436 #pinctrl-cells = <1>;
437 pinctrl-single,register-width = <32>;
438 pinctrl-single,function-mask = <0xffffffff>;
442 compatible = "ti,j7200-padconf", "pinctrl-single";
445 #pinctrl-cells = <1>;
446 pinctrl-single,register-width = <32>;
447 pinctrl-single,function-mask = <0xffffffff>;
451 compatible = "ti,j721e-uart", "ti,am654-uart";
454 clock-frequency = <48000000>;
455 current-speed = <115200>;
456 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
458 clock-names = "fclk";
463 compatible = "ti,j721e-uart", "ti,am654-uart";
466 clock-frequency = <48000000>;
467 current-speed = <115200>;
468 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
470 clock-names = "fclk";
475 compatible = "ti,j721e-uart", "ti,am654-uart";
478 clock-frequency = <48000000>;
479 current-speed = <115200>;
480 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
482 clock-names = "fclk";
487 compatible = "ti,j721e-uart", "ti,am654-uart";
490 clock-frequency = <48000000>;
491 current-speed = <115200>;
492 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
494 clock-names = "fclk";
499 compatible = "ti,j721e-uart", "ti,am654-uart";
502 clock-frequency = <48000000>;
503 current-speed = <115200>;
504 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
506 clock-names = "fclk";
511 compatible = "ti,j721e-uart", "ti,am654-uart";
514 clock-frequency = <48000000>;
515 current-speed = <115200>;
516 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
518 clock-names = "fclk";
523 compatible = "ti,j721e-uart", "ti,am654-uart";
526 clock-frequency = <48000000>;
527 current-speed = <115200>;
528 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
530 clock-names = "fclk";
535 compatible = "ti,j721e-uart", "ti,am654-uart";
538 clock-frequency = <48000000>;
539 current-speed = <115200>;
540 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
542 clock-names = "fclk";
547 compatible = "ti,j721e-uart", "ti,am654-uart";
550 clock-frequency = <48000000>;
551 current-speed = <115200>;
552 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
554 clock-names = "fclk";
559 compatible = "ti,j721e-uart", "ti,am654-uart";
562 clock-frequency = <48000000>;
563 current-speed = <115200>;
564 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
566 clock-names = "fclk";
570 main_i2c0: i2c@2000000 {
571 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
574 #address-cells = <1>;
575 #size-cells = <0>;
576 clock-names = "fck";
578 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
582 main_i2c1: i2c@2010000 {
583 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
586 #address-cells = <1>;
587 #size-cells = <0>;
588 clock-names = "fck";
590 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
594 main_i2c2: i2c@2020000 {
595 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
598 #address-cells = <1>;
599 #size-cells = <0>;
600 clock-names = "fck";
602 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
606 main_i2c3: i2c@2030000 {
607 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
610 #address-cells = <1>;
611 #size-cells = <0>;
612 clock-names = "fck";
614 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
618 main_i2c4: i2c@2040000 {
619 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
622 #address-cells = <1>;
623 #size-cells = <0>;
624 clock-names = "fck";
626 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
630 main_i2c5: i2c@2050000 {
631 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
634 #address-cells = <1>;
635 #size-cells = <0>;
636 clock-names = "fck";
638 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
642 main_i2c6: i2c@2060000 {
643 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
646 #address-cells = <1>;
647 #size-cells = <0>;
648 clock-names = "fck";
650 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
655 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
658 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
659 clock-names = "clk_ahb", "clk_xin";
661 ti,otap-del-sel-legacy = <0x0>;
662 ti,otap-del-sel-mmc-hs = <0x0>;
663 ti,otap-del-sel-ddr52 = <0x6>;
664 ti,otap-del-sel-hs200 = <0x8>;
665 ti,otap-del-sel-hs400 = <0x5>;
666 ti,itap-del-sel-legacy = <0x10>;
667 ti,itap-del-sel-mmc-hs = <0xa>;
668 ti,strobe-sel = <0x77>;
669 ti,clkbuf-sel = <0x7>;
670 ti,trm-icp = <0x8>;
671 bus-width = <8>;
672 mmc-ddr-1_8v;
673 mmc-hs200-1_8v;
674 mmc-hs400-1_8v;
675 dma-coherent;
680 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
683 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
684 clock-names = "clk_ahb", "clk_xin";
686 ti,otap-del-sel-legacy = <0x0>;
687 ti,otap-del-sel-sd-hs = <0x0>;
688 ti,otap-del-sel-sdr12 = <0xf>;
689 ti,otap-del-sel-sdr25 = <0xf>;
690 ti,otap-del-sel-sdr50 = <0xc>;
691 ti,otap-del-sel-sdr104 = <0x5>;
692 ti,otap-del-sel-ddr50 = <0xc>;
693 ti,itap-del-sel-legacy = <0x0>;
694 ti,itap-del-sel-sd-hs = <0x0>;
695 ti,itap-del-sel-sdr12 = <0x0>;
696 ti,itap-del-sel-sdr25 = <0x0>;
697 ti,clkbuf-sel = <0x7>;
698 ti,trm-icp = <0x8>;
699 dma-coherent;
704 compatible = "ti,j721e-wiz-10g";
705 #address-cells = <1>;
706 #size-cells = <1>;
707 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
709 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
710 num-lanes = <4>;
711 #reset-cells = <1>;
714 assigned-clocks = <&k3_clks 292 85>;
715 assigned-clock-parents = <&k3_clks 292 89>;
717 wiz0_pll0_refclk: pll0-refclk {
719 clock-output-names = "wiz0_pll0_refclk";
720 #clock-cells = <0>;
721 assigned-clocks = <&wiz0_pll0_refclk>;
722 assigned-clock-parents = <&k3_clks 292 85>;
725 wiz0_pll1_refclk: pll1-refclk {
727 clock-output-names = "wiz0_pll1_refclk";
728 #clock-cells = <0>;
729 assigned-clocks = <&wiz0_pll1_refclk>;
730 assigned-clock-parents = <&k3_clks 292 85>;
733 wiz0_refclk_dig: refclk-dig {
735 clock-output-names = "wiz0_refclk_dig";
736 #clock-cells = <0>;
737 assigned-clocks = <&wiz0_refclk_dig>;
738 assigned-clock-parents = <&k3_clks 292 85>;
741 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
743 #clock-cells = <0>;
747 compatible = "ti,j721e-serdes-10g";
749 reg-names = "torrent_phy";
751 reset-names = "torrent_reset";
753 clock-names = "refclk";
754 #address-cells = <1>;
755 #size-cells = <0>;
760 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
765 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
766 interrupt-names = "link_state";
769 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
770 max-link-speed = <3>;
771 num-lanes = <4>;
772 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
774 clock-names = "fck";
775 #address-cells = <3>;
776 #size-cells = <2>;
777 bus-range = <0x0 0xff>;
778 cdns,no-bar-match-nbits = <64>;
779 vendor-id = <0x104c>;
780 device-id = <0xb00f>;
781 msi-map = <0x0 &gic_its 0x0 0x10000>;
782 dma-coherent;
785 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
788 pcie1_ep: pcie-ep@2910000 {
789 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
794 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
795 interrupt-names = "link_state";
797 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
798 max-link-speed = <3>;
799 num-lanes = <4>;
800 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
802 clock-names = "fck";
803 max-functions = /bits/ 8 <6>;
804 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
805 dma-coherent;
808 usbss0: cdns-usb@4104000 {
809 compatible = "ti,j721e-usb";
811 dma-coherent;
812 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
814 clock-names = "ref", "lpm";
815 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
816 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
817 #address-cells = <2>;
818 #size-cells = <2>;
826 reg-names = "otg", "xhci", "dev";
830 interrupt-names = "host",
833 maximum-speed = "super-speed";
835 cdns,phyrst-a-enable;
840 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
842 gpio-controller;
843 #gpio-cells = <2>;
844 interrupt-parent = <&main_gpio_intr>;
847 interrupt-controller;
848 #interrupt-cells = <2>;
850 ti,davinci-gpio-unbanked = <0>;
851 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
853 clock-names = "gpio";
858 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
860 gpio-controller;
861 #gpio-cells = <2>;
862 interrupt-parent = <&main_gpio_intr>;
865 interrupt-controller;
866 #interrupt-cells = <2>;
868 ti,davinci-gpio-unbanked = <0>;
869 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
871 clock-names = "gpio";
876 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
878 gpio-controller;
879 #gpio-cells = <2>;
880 interrupt-parent = <&main_gpio_intr>;
883 interrupt-controller;
884 #interrupt-cells = <2>;
886 ti,davinci-gpio-unbanked = <0>;
887 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
889 clock-names = "gpio";
894 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
896 gpio-controller;
897 #gpio-cells = <2>;
898 interrupt-parent = <&main_gpio_intr>;
901 interrupt-controller;
902 #interrupt-cells = <2>;
904 ti,davinci-gpio-unbanked = <0>;
905 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
907 clock-names = "gpio";
912 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
915 #address-cells = <1>;
916 #size-cells = <0>;
917 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
923 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
926 #address-cells = <1>;
927 #size-cells = <0>;
928 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
934 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
937 #address-cells = <1>;
938 #size-cells = <0>;
939 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
945 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
948 #address-cells = <1>;
949 #size-cells = <0>;
950 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
956 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
959 #address-cells = <1>;
960 #size-cells = <0>;
961 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
967 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
970 #address-cells = <1>;
971 #size-cells = <0>;
972 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
978 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
981 #address-cells = <1>;
982 #size-cells = <0>;
983 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
989 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
992 #address-cells = <1>;
993 #size-cells = <0>;
994 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
1000 compatible = "ti,j7-rti-wdt";
1003 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1004 assigned-clocks = <&k3_clks 252 1>;
1005 assigned-clock-parents = <&k3_clks 252 5>;
1009 compatible = "ti,j7-rti-wdt";
1012 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1013 assigned-clocks = <&k3_clks 253 1>;
1014 assigned-clock-parents = <&k3_clks 253 5>;
1018 compatible = "ti,am654-timer";
1022 clock-names = "fck";
1023 assigned-clocks = <&k3_clks 49 1>;
1024 assigned-clock-parents = <&k3_clks 49 2>;
1025 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1026 ti,timer-pwm;
1030 compatible = "ti,am654-timer";
1034 clock-names = "fck";
1035 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1036 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
1037 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1038 ti,timer-pwm;
1042 compatible = "ti,am654-timer";
1046 clock-names = "fck";
1047 assigned-clocks = <&k3_clks 51 1>;
1048 assigned-clock-parents = <&k3_clks 51 2>;
1049 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1050 ti,timer-pwm;
1054 compatible = "ti,am654-timer";
1058 clock-names = "fck";
1059 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1060 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
1061 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1062 ti,timer-pwm;
1066 compatible = "ti,am654-timer";
1070 clock-names = "fck";
1071 assigned-clocks = <&k3_clks 53 1>;
1072 assigned-clock-parents = <&k3_clks 53 2>;
1073 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1074 ti,timer-pwm;
1078 compatible = "ti,am654-timer";
1082 clock-names = "fck";
1083 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1084 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
1085 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1086 ti,timer-pwm;
1090 compatible = "ti,am654-timer";
1094 clock-names = "fck";
1095 assigned-clocks = <&k3_clks 55 1>;
1096 assigned-clock-parents = <&k3_clks 55 2>;
1097 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1098 ti,timer-pwm;
1102 compatible = "ti,am654-timer";
1106 clock-names = "fck";
1107 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1108 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
1109 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1110 ti,timer-pwm;
1114 compatible = "ti,am654-timer";
1118 clock-names = "fck";
1119 assigned-clocks = <&k3_clks 58 1>;
1120 assigned-clock-parents = <&k3_clks 58 2>;
1121 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1122 ti,timer-pwm;
1126 compatible = "ti,am654-timer";
1130 clock-names = "fck";
1131 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1132 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
1133 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1134 ti,timer-pwm;
1138 compatible = "ti,am654-timer";
1142 clock-names = "fck";
1143 assigned-clocks = <&k3_clks 60 1>;
1144 assigned-clock-parents = <&k3_clks 60 2>;
1145 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1146 ti,timer-pwm;
1150 compatible = "ti,am654-timer";
1154 clock-names = "fck";
1155 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1156 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
1157 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1158 ti,timer-pwm;
1162 compatible = "ti,am654-timer";
1166 clock-names = "fck";
1167 assigned-clocks = <&k3_clks 63 1>;
1168 assigned-clock-parents = <&k3_clks 63 2>;
1169 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1170 ti,timer-pwm;
1174 compatible = "ti,am654-timer";
1178 clock-names = "fck";
1179 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1180 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
1181 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1182 ti,timer-pwm;
1186 compatible = "ti,am654-timer";
1190 clock-names = "fck";
1191 assigned-clocks = <&k3_clks 65 1>;
1192 assigned-clock-parents = <&k3_clks 65 2>;
1193 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1194 ti,timer-pwm;
1198 compatible = "ti,am654-timer";
1202 clock-names = "fck";
1203 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1204 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
1205 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1206 ti,timer-pwm;
1210 compatible = "ti,am654-timer";
1214 clock-names = "fck";
1215 assigned-clocks = <&k3_clks 67 1>;
1216 assigned-clock-parents = <&k3_clks 67 2>;
1217 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1218 ti,timer-pwm;
1222 compatible = "ti,am654-timer";
1226 clock-names = "fck";
1227 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1228 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
1229 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1230 ti,timer-pwm;
1234 compatible = "ti,am654-timer";
1238 clock-names = "fck";
1239 assigned-clocks = <&k3_clks 69 1>;
1240 assigned-clock-parents = <&k3_clks 69 2>;
1241 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1242 ti,timer-pwm;
1246 compatible = "ti,am654-timer";
1250 clock-names = "fck";
1251 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1252 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
1253 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1254 ti,timer-pwm;
1258 compatible = "ti,j7200-r5fss";
1259 ti,cluster-mode = <1>;
1260 #address-cells = <1>;
1261 #size-cells = <1>;
1264 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1267 compatible = "ti,j7200-r5f";
1270 reg-names = "atcm", "btcm";
1272 ti,sci-dev-id = <245>;
1273 ti,sci-proc-ids = <0x06 0xff>;
1275 firmware-name = "j7200-main-r5f0_0-fw";
1276 ti,atcm-enable = <1>;
1277 ti,btcm-enable = <1>;
1282 compatible = "ti,j7200-r5f";
1285 reg-names = "atcm", "btcm";
1287 ti,sci-dev-id = <246>;
1288 ti,sci-proc-ids = <0x07 0xff>;
1290 firmware-name = "j7200-main-r5f0_1-fw";
1291 ti,atcm-enable = <1>;
1292 ti,btcm-enable = <1>;
1298 compatible = "ti,j721e-esm";
1300 ti,esm-pins = <656>, <657>;