Lines Matching +full:0 +full:x35000000
10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
24 reg = <0x00 0x20000>;
30 reg = <0x00 0x00100000 0x00 0x1c000>;
33 ranges = <0x00 0x00 0x00100000 0x1c000>;
38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
45 reg = <0x4044 0x10>;
52 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
63 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
64 <0x00 0x01900000 0x00 0x100000>, /* GICR */
65 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
66 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
67 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
74 reg = <0x00 0x01820000 0x00 0x10000>;
75 socionext,synquacer-pre-its = <0x1000000 0x400000>;
83 reg = <0x00 0x00a00000 0x00 0x800>;
97 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
104 reg = <0x00 0x310e0000 0x00 0x4000>;
111 ti,interrupt-ranges = <0 64 64>,
118 reg = <0x00 0x33d00000 0x00 0x100000>;
120 #interrupt-cells = <0>;
125 ti,interrupt-ranges = <0 0 256>;
132 reg = <0x00 0x32c00000 0x00 0x100000>,
133 <0x00 0x32400000 0x00 0x100000>,
134 <0x00 0x32800000 0x00 0x100000>;
141 reg = <0x00 0x30e00000 0x00 0x1000>;
147 reg = <0x00 0x31f80000 0x00 0x200>;
157 reg = <0x00 0x31f81000 0x00 0x200>;
167 reg = <0x00 0x31f82000 0x00 0x200>;
177 reg = <0x00 0x31f83000 0x00 0x200>;
187 reg = <0x00 0x31f84000 0x00 0x200>;
197 reg = <0x00 0x31f85000 0x00 0x200>;
207 reg = <0x00 0x31f86000 0x00 0x200>;
217 reg = <0x00 0x31f87000 0x00 0x200>;
227 reg = <0x00 0x31f88000 0x00 0x200>;
237 reg = <0x00 0x31f89000 0x00 0x200>;
247 reg = <0x00 0x31f8a000 0x00 0x200>;
257 reg = <0x00 0x31f8b000 0x00 0x200>;
267 reg = <0x00 0x3c000000 0x00 0x400000>,
268 <0x00 0x38000000 0x00 0x400000>,
269 <0x00 0x31120000 0x00 0x100>,
270 <0x00 0x33000000 0x00 0x40000>,
271 <0x00 0x31080000 0x00 0x40000>;
274 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
282 reg = <0x00 0x31150000 0x00 0x100>,
283 <0x00 0x34000000 0x00 0x100000>,
284 <0x00 0x35000000 0x00 0x100000>;
293 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
294 <0x0f>, /* TX_HCHAN */
295 <0x10>; /* TX_UHCHAN */
296 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
297 <0x0b>, /* RX_HCHAN */
298 <0x0c>; /* RX_UHCHAN */
299 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
304 reg = <0x00 0x310d0000 0x00 0x400>;
319 reg = <0x00 0xc000000 0x00 0x200000>;
321 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
326 dmas = <&main_udmap 0xca00>,
327 <&main_udmap 0xca01>,
328 <&main_udmap 0xca02>,
329 <&main_udmap 0xca03>,
330 <&main_udmap 0xca04>,
331 <&main_udmap 0xca05>,
332 <&main_udmap 0xca06>,
333 <&main_udmap 0xca07>,
334 <&main_udmap 0x4a00>;
343 #size-cells = <0>;
375 reg = <0x00 0xf00 0x00 0x100>;
377 #size-cells = <0>;
386 reg = <0x00 0x3d000 0x00 0x400>;
399 reg = <0x0 0x104200 0x0 0x50>;
402 pinctrl-single,function-mask = <0x000001ff>;
408 reg = <0x0 0x104280 0x0 0x20>;
411 pinctrl-single,function-mask = <0x0000001f>;
416 /* Proxy 0 addressing */
417 reg = <0x00 0x11c000 0x00 0x10c>;
420 pinctrl-single,function-mask = <0xffffffff>;
425 /* Proxy 0 addressing */
426 reg = <0x00 0x11c110 0x00 0x004>;
429 pinctrl-single,function-mask = <0xffffffff>;
434 /* Proxy 0 addressing */
435 reg = <0x00 0x11c11c 0x00 0x00c>;
438 pinctrl-single,function-mask = <0xffffffff>;
443 /* Proxy 0 addressing */
444 reg = <0x00 0x11c164 0x00 0x008>;
447 pinctrl-single,function-mask = <0xffffffff>;
452 reg = <0x00 0x02800000 0x00 0x100>;
464 reg = <0x00 0x02810000 0x00 0x100>;
476 reg = <0x00 0x02820000 0x00 0x100>;
488 reg = <0x00 0x02830000 0x00 0x100>;
500 reg = <0x00 0x02840000 0x00 0x100>;
512 reg = <0x00 0x02850000 0x00 0x100>;
524 reg = <0x00 0x02860000 0x00 0x100>;
536 reg = <0x00 0x02870000 0x00 0x100>;
548 reg = <0x00 0x02880000 0x00 0x100>;
560 reg = <0x00 0x02890000 0x00 0x100>;
572 reg = <0x00 0x2000000 0x00 0x100>;
575 #size-cells = <0>;
584 reg = <0x00 0x2010000 0x00 0x100>;
587 #size-cells = <0>;
596 reg = <0x00 0x2020000 0x00 0x100>;
599 #size-cells = <0>;
608 reg = <0x00 0x2030000 0x00 0x100>;
611 #size-cells = <0>;
620 reg = <0x00 0x2040000 0x00 0x100>;
623 #size-cells = <0>;
632 reg = <0x00 0x2050000 0x00 0x100>;
635 #size-cells = <0>;
644 reg = <0x00 0x2060000 0x00 0x100>;
647 #size-cells = <0>;
656 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
660 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
661 ti,otap-del-sel-legacy = <0x0>;
662 ti,otap-del-sel-mmc-hs = <0x0>;
663 ti,otap-del-sel-ddr52 = <0x6>;
664 ti,otap-del-sel-hs200 = <0x8>;
665 ti,otap-del-sel-hs400 = <0x5>;
666 ti,itap-del-sel-legacy = <0x10>;
667 ti,itap-del-sel-mmc-hs = <0xa>;
668 ti,strobe-sel = <0x77>;
669 ti,clkbuf-sel = <0x7>;
670 ti,trm-icp = <0x8>;
681 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
686 ti,otap-del-sel-legacy = <0x0>;
687 ti,otap-del-sel-sd-hs = <0x0>;
688 ti,otap-del-sel-sdr12 = <0xf>;
689 ti,otap-del-sel-sdr25 = <0xf>;
690 ti,otap-del-sel-sdr50 = <0xc>;
691 ti,otap-del-sel-sdr104 = <0x5>;
692 ti,otap-del-sel-ddr50 = <0xc>;
693 ti,itap-del-sel-legacy = <0x0>;
694 ti,itap-del-sel-sd-hs = <0x0>;
695 ti,itap-del-sel-sdr12 = <0x0>;
696 ti,itap-del-sel-sdr25 = <0x0>;
697 ti,clkbuf-sel = <0x7>;
698 ti,trm-icp = <0x8>;
712 ranges = <0x5060000 0x0 0x5060000 0x10000>;
720 #clock-cells = <0>;
728 #clock-cells = <0>;
736 #clock-cells = <0>;
743 #clock-cells = <0>;
748 reg = <0x05060000 0x00010000>;
750 resets = <&serdes_wiz0 0>;
755 #size-cells = <0>;
761 reg = <0x00 0x02910000 0x00 0x1000>,
762 <0x00 0x02917000 0x00 0x400>,
763 <0x00 0x0d800000 0x00 0x00800000>,
764 <0x00 0x18000000 0x00 0x00001000>;
769 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
777 bus-range = <0x0 0xff>;
779 vendor-id = <0x104c>;
780 device-id = <0xb00f>;
781 msi-map = <0x0 &gic_its 0x0 0x10000>;
783 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
784 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
785 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
790 reg = <0x00 0x02910000 0x00 0x1000>,
791 <0x00 0x02917000 0x00 0x400>,
792 <0x00 0x0d800000 0x00 0x00800000>,
793 <0x00 0x18000000 0x00 0x08000000>;
797 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
804 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
810 reg = <0x00 0x4104000 0x00 0x100>;
823 reg = <0x00 0x6000000 0x00 0x10000>,
824 <0x00 0x6010000 0x00 0x10000>,
825 <0x00 0x6020000 0x00 0x10000>;
827 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
829 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
841 reg = <0x00 0x00600000 0x00 0x100>;
850 ti,davinci-gpio-unbanked = <0>;
852 clocks = <&k3_clks 105 0>;
859 reg = <0x00 0x00610000 0x00 0x100>;
868 ti,davinci-gpio-unbanked = <0>;
870 clocks = <&k3_clks 107 0>;
877 reg = <0x00 0x00620000 0x00 0x100>;
886 ti,davinci-gpio-unbanked = <0>;
888 clocks = <&k3_clks 109 0>;
895 reg = <0x00 0x00630000 0x00 0x100>;
904 ti,davinci-gpio-unbanked = <0>;
906 clocks = <&k3_clks 111 0>;
913 reg = <0x00 0x02100000 0x00 0x400>;
916 #size-cells = <0>;
924 reg = <0x00 0x02110000 0x00 0x400>;
927 #size-cells = <0>;
935 reg = <0x00 0x02120000 0x00 0x400>;
938 #size-cells = <0>;
946 reg = <0x00 0x02130000 0x00 0x400>;
949 #size-cells = <0>;
957 reg = <0x00 0x02140000 0x00 0x400>;
960 #size-cells = <0>;
968 reg = <0x00 0x02150000 0x00 0x400>;
971 #size-cells = <0>;
979 reg = <0x00 0x02160000 0x00 0x400>;
982 #size-cells = <0>;
990 reg = <0x00 0x02170000 0x00 0x400>;
993 #size-cells = <0>;
1001 reg = <0x0 0x2200000 0x0 0x100>;
1010 reg = <0x0 0x2210000 0x0 0x100>;
1019 reg = <0x00 0x2400000 0x00 0x400>;
1031 reg = <0x00 0x2410000 0x00 0x400>;
1035 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1043 reg = <0x00 0x2420000 0x00 0x400>;
1055 reg = <0x00 0x2430000 0x00 0x400>;
1059 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1067 reg = <0x00 0x2440000 0x00 0x400>;
1079 reg = <0x00 0x2450000 0x00 0x400>;
1083 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1091 reg = <0x00 0x2460000 0x00 0x400>;
1103 reg = <0x00 0x2470000 0x00 0x400>;
1107 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1115 reg = <0x00 0x2480000 0x00 0x400>;
1127 reg = <0x00 0x2490000 0x00 0x400>;
1131 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1139 reg = <0x00 0x24a0000 0x00 0x400>;
1151 reg = <0x00 0x24b0000 0x00 0x400>;
1155 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1163 reg = <0x00 0x24c0000 0x00 0x400>;
1175 reg = <0x00 0x24d0000 0x00 0x400>;
1179 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1187 reg = <0x00 0x24e0000 0x00 0x400>;
1199 reg = <0x00 0x24f0000 0x00 0x400>;
1203 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1211 reg = <0x00 0x2500000 0x00 0x400>;
1223 reg = <0x00 0x2510000 0x00 0x400>;
1227 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1235 reg = <0x00 0x2520000 0x00 0x400>;
1247 reg = <0x00 0x2530000 0x00 0x400>;
1251 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1262 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1263 <0x5d00000 0x00 0x5d00000 0x20000>;
1268 reg = <0x5c00000 0x00010000>,
1269 <0x5c10000 0x00010000>;
1273 ti,sci-proc-ids = <0x06 0xff>;
1283 reg = <0x5d00000 0x00008000>,
1284 <0x5d10000 0x00008000>;
1288 ti,sci-proc-ids = <0x07 0xff>;
1299 reg = <0x0 0x700000 0x0 0x1000>;