Lines Matching +full:0 +full:x46000000
11 reg = <0x0 0x40f00000 0x0 0x20000>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
18 reg = <0x4040 0x4>;
26 reg = <0x0 0x40f04200 0x0 0x10>;
29 pinctrl-single,function-mask = <0x00000101>;
35 reg = <0x0 0x40f04280 0x0 0x8>;
38 pinctrl-single,function-mask = <0x00000003>;
43 reg = <0x00 0x40a00000 0x00 0x100>;
53 reg = <0x00 0x41c00000 0x00 0x80000>;
54 ranges = <0x0 0x00 0x41c00000 0x80000>;
61 reg = <0x0 0x40b00000 0x0 0x100>;
64 #size-cells = <0>;
73 reg = <0x0 0x40300000 0x0 0x400>;
78 #size-cells = <0>;
84 reg = <0x0 0x40310000 0x0 0x400>;
89 #size-cells = <0>;
95 reg = <0x0 0x40320000 0x0 0x400>;
100 #size-cells = <0>;
106 reg = <0x0 0x40200000 0x0 0x1000>;
108 clocks = <&k3_clks 0 2>;
109 assigned-clocks = <&k3_clks 0 2>;
112 dmas = <&mcu_udmap 0x7100>,
113 <&mcu_udmap 0x7101 >;
125 reg = <0x0 0x40210000 0x0 0x1000>;
131 dmas = <&mcu_udmap 0x7102>,
132 <&mcu_udmap 0x7103>;
149 reg = <0x00 0x40400000 0x00 0x400>;
150 clocks = <&k3_clks 35 0>;
159 reg = <0x00 0x40410000 0x00 0x400>;
160 clocks = <&k3_clks 36 0>;
169 reg = <0x00 0x40420000 0x00 0x400>;
170 clocks = <&k3_clks 37 0>;
179 reg = <0x00 0x40430000 0x00 0x400>;
180 clocks = <&k3_clks 38 0>;
191 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
199 reg = <0x0 0x2b800000 0x0 0x400000>,
200 <0x0 0x2b000000 0x0 0x400000>,
201 <0x0 0x28590000 0x0 0x100>,
202 <0x0 0x2a500000 0x0 0x40000>,
203 <0x0 0x28440000 0x0 0x40000>;
207 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
215 reg = <0x0 0x285c0000 0x0 0x100>,
216 <0x0 0x2a800000 0x0 0x40000>,
217 <0x0 0x2aa00000 0x0 0x40000>;
226 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
227 <0xd>; /* TX_CHAN */
228 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
229 <0xa>; /* RX_CHAN */
230 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
238 reg = <0x0 0x2a480000 0x0 0x80000>,
239 <0x0 0x2a380000 0x0 0x80000>,
240 <0x0 0x2a400000 0x0 0x80000>;
251 reg = <0x0 0x40528000 0x0 0x400>,
252 <0x0 0x40500000 0x0 0x4400>;
255 clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
261 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
267 reg = <0x0 0x40568000 0x0 0x400>,
268 <0x0 0x40540000 0x0 0x4400>;
271 clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
277 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
289 reg = <0x0 0x47040000 0x0 0x100>,
290 <0x5 0x00000000 0x1 0x0000000>;
294 cdns,trigger-address = <0x0>;
295 clocks = <&k3_clks 248 0>;
296 assigned-clocks = <&k3_clks 248 0>;
301 #size-cells = <0>;
307 reg = <0x0 0x47050000 0x0 0x100>,
308 <0x7 0x00000000 0x1 0x00000000>;
312 cdns,trigger-address = <0x0>;
316 #size-cells = <0>;
325 reg = <0x0 0x46000000 0x0 0x200000>;
327 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
333 dmas = <&mcu_udmap 0xf000>,
334 <&mcu_udmap 0xf001>,
335 <&mcu_udmap 0xf002>,
336 <&mcu_udmap 0xf003>,
337 <&mcu_udmap 0xf004>,
338 <&mcu_udmap 0xf005>,
339 <&mcu_udmap 0xf006>,
340 <&mcu_udmap 0xf007>,
341 <&mcu_udmap 0x7000>;
348 #size-cells = <0>;
354 ti,syscon-efuse = <&mcu_conf 0x200>;
361 reg = <0x0 0xf00 0x0 0x100>;
363 #size-cells = <0>;
372 reg = <0x0 0x3d000 0x0 0x400>;
381 #clock-cells = <0>;
397 ranges = <0x41000000 0x00 0x41000000 0x20000>,
398 <0x41400000 0x00 0x41400000 0x20000>;
403 reg = <0x41000000 0x00008000>,
404 <0x41010000 0x00008000>;
408 ti,sci-proc-ids = <0x01 0xff>;
418 reg = <0x41400000 0x00008000>,
419 <0x41410000 0x00008000>;
423 ti,sci-proc-ids = <0x02 0xff>;
434 reg = <0x0 0x40610000 0x0 0x100>;
435 clocks = <&k3_clks 135 0>;
437 assigned-clocks = <&k3_clks 135 0>;