Lines Matching +full:0 +full:x31080000
12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
50 reg = <0x00 0x01820000 0x00 0x10000>;
51 socionext,synquacer-pre-its = <0x1000000 0x400000>;
59 reg = <0x0 0x900000 0x0 0x2000>;
69 mux-controls = <&serdes_mux 0>;
74 reg = <0x0 0x910000 0x0 0x2000>;
89 reg = <0x00 0x02800000 0x00 0x100>;
99 reg = <0x00 0x02810000 0x00 0x100>;
108 reg = <0x00 0x02820000 0x00 0x100>;
117 reg = <0x0 0x4e00000 0x0 0x1200>;
121 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
123 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
124 <&main_udmap 0x4003>;
129 reg = <0x0 0x4e10000 0x0 0x7d>;
138 reg = <0x0 0x104200 0x0 0x30>;
141 pinctrl-single,function-mask = <0x0000001ff>;
147 reg = <0x0 0x104280 0x0 0x20>;
150 pinctrl-single,function-mask = <0x0000000f>;
155 reg = <0x0 0x11c000 0x0 0x2e4>;
158 pinctrl-single,function-mask = <0xffffffff>;
163 reg = <0x0 0x11c2e8 0x0 0x24>;
166 pinctrl-single,function-mask = <0xffffffff>;
171 reg = <0x0 0x2000000 0x0 0x100>;
174 #size-cells = <0>;
183 reg = <0x0 0x2010000 0x0 0x100>;
186 #size-cells = <0>;
195 reg = <0x0 0x2020000 0x0 0x100>;
198 #size-cells = <0>;
207 reg = <0x0 0x2030000 0x0 0x100>;
210 #size-cells = <0>;
220 reg = <0x0 0x03100000 0x0 0x60>;
222 clocks = <&k3_clks 39 0>;
229 reg = <0x0 0x2100000 0x0 0x400>;
234 #size-cells = <0>;
235 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
242 reg = <0x0 0x2110000 0x0 0x400>;
247 #size-cells = <0>;
255 reg = <0x0 0x2120000 0x0 0x400>;
260 #size-cells = <0>;
266 reg = <0x0 0x2130000 0x0 0x400>;
271 #size-cells = <0>;
277 reg = <0x0 0x2140000 0x0 0x400>;
282 #size-cells = <0>;
288 reg = <0x00 0x2400000 0x00 0x400>;
290 clocks = <&k3_clks 23 0>;
292 assigned-clocks = <&k3_clks 23 0>;
300 reg = <0x00 0x2410000 0x00 0x400>;
302 clocks = <&k3_clks 24 0>;
304 assigned-clocks = <&k3_clks 24 0>;
312 reg = <0x00 0x2420000 0x00 0x400>;
314 clocks = <&k3_clks 27 0>;
316 assigned-clocks = <&k3_clks 27 0>;
324 reg = <0x00 0x2430000 0x00 0x400>;
326 clocks = <&k3_clks 28 0>;
328 assigned-clocks = <&k3_clks 28 0>;
336 reg = <0x00 0x2440000 0x00 0x400>;
338 clocks = <&k3_clks 29 0>;
340 assigned-clocks = <&k3_clks 29 0>;
348 reg = <0x00 0x2450000 0x00 0x400>;
350 clocks = <&k3_clks 30 0>;
352 assigned-clocks = <&k3_clks 30 0>;
360 reg = <0x00 0x2460000 0x00 0x400>;
362 clocks = <&k3_clks 31 0>;
363 assigned-clocks = <&k3_clks 31 0>;
372 reg = <0x00 0x2470000 0x00 0x400>;
374 clocks = <&k3_clks 32 0>;
376 assigned-clocks = <&k3_clks 32 0>;
384 reg = <0x00 0x2480000 0x00 0x400>;
386 clocks = <&k3_clks 33 0>;
388 assigned-clocks = <&k3_clks 33 0>;
396 reg = <0x00 0x2490000 0x00 0x400>;
398 clocks = <&k3_clks 34 0>;
400 assigned-clocks = <&k3_clks 34 0>;
408 reg = <0x00 0x24a0000 0x00 0x400>;
410 clocks = <&k3_clks 25 0>;
412 assigned-clocks = <&k3_clks 25 0>;
420 reg = <0x00 0x24b0000 0x00 0x400>;
422 clocks = <&k3_clks 26 0>;
424 assigned-clocks = <&k3_clks 26 0>;
432 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
434 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
439 ti,otap-del-sel-legacy = <0x0>;
440 ti,otap-del-sel-mmc-hs = <0x0>;
441 ti,otap-del-sel-sd-hs = <0x0>;
442 ti,otap-del-sel-sdr12 = <0x0>;
443 ti,otap-del-sel-sdr25 = <0x0>;
444 ti,otap-del-sel-sdr50 = <0x8>;
445 ti,otap-del-sel-sdr104 = <0x7>;
446 ti,otap-del-sel-ddr50 = <0x5>;
447 ti,otap-del-sel-ddr52 = <0x5>;
448 ti,otap-del-sel-hs200 = <0x5>;
449 ti,otap-del-sel-hs400 = <0x0>;
450 ti,trm-icp = <0x8>;
456 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
458 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
461 ti,otap-del-sel-legacy = <0x0>;
462 ti,otap-del-sel-mmc-hs = <0x0>;
463 ti,otap-del-sel-sd-hs = <0x0>;
464 ti,otap-del-sel-sdr12 = <0x0>;
465 ti,otap-del-sel-sdr25 = <0x0>;
466 ti,otap-del-sel-sdr50 = <0x8>;
467 ti,otap-del-sel-sdr104 = <0x7>;
468 ti,otap-del-sel-ddr50 = <0x4>;
469 ti,otap-del-sel-ddr52 = <0x4>;
470 ti,otap-del-sel-hs200 = <0x7>;
471 ti,clkbuf-sel = <0x7>;
472 ti,trm-icp = <0x8>;
478 reg = <0 0x00100000 0 0x1c000>;
481 ranges = <0x0 0x0 0x00100000 0x1c000>;
485 reg = <0x00004080 0x4>;
490 reg = <0x00004090 0x4>;
496 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
497 <0x4090 0x3>; /* SERDES1 lane select */
502 reg = <0x000041e0 0x14>;
507 reg = <0x4140 0x18>;
514 reg = <0x0 0x4000000 0x0 0x4000>;
517 ranges = <0x0 0x0 0x4000000 0x20000>;
528 reg = <0x10000 0x10000>;
545 reg = <0x0 0x4100000 0x0 0x54>;
546 syscon-phy-power = <&scm_conf 0x4000>;
547 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
549 #phy-cells = <0>;
554 reg = <0x0 0x4020000 0x0 0x4000>;
557 ranges = <0x0 0x0 0x4020000 0x20000>;
567 reg = <0x10000 0x10000>;
583 reg = <0x0 0x4110000 0x0 0x54>;
584 syscon-phy-power = <&scm_conf 0x4020>;
585 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
587 #phy-cells = <0>;
592 reg = <0x0 0x00a00000 0x0 0x400>;
599 ti,interrupt-ranges = <0 392 32>;
606 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
614 reg = <0x0 0x310e0000 0x0 0x2000>;
621 ti,interrupt-ranges = <0 64 64>,
627 reg = <0x0 0x33d00000 0x0 0x100000>;
631 #interrupt-cells = <0>;
634 ti,interrupt-ranges = <0 0 256>;
641 reg = <0x00 0x32c00000 0x00 0x100000>,
642 <0x00 0x32400000 0x00 0x100000>,
643 <0x00 0x32800000 0x00 0x100000>;
650 reg = <0x00 0x30e00000 0x00 0x1000>;
656 reg = <0x00 0x31f80000 0x00 0x200>;
666 reg = <0x00 0x31f81000 0x00 0x200>;
676 reg = <0x00 0x31f82000 0x00 0x200>;
686 reg = <0x00 0x31f83000 0x00 0x200>;
696 reg = <0x00 0x31f84000 0x00 0x200>;
706 reg = <0x00 0x31f85000 0x00 0x200>;
716 reg = <0x00 0x31f86000 0x00 0x200>;
726 reg = <0x00 0x31f87000 0x00 0x200>;
736 reg = <0x00 0x31f88000 0x00 0x200>;
746 reg = <0x00 0x31f89000 0x00 0x200>;
756 reg = <0x00 0x31f8a000 0x00 0x200>;
766 reg = <0x00 0x31f8b000 0x00 0x200>;
776 reg = <0x0 0x3c000000 0x0 0x400000>,
777 <0x0 0x38000000 0x0 0x400000>,
778 <0x0 0x31120000 0x0 0x100>,
779 <0x0 0x33000000 0x0 0x40000>,
780 <0x0 0x31080000 0x0 0x40000>;
783 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
791 reg = <0x0 0x31150000 0x0 0x100>,
792 <0x0 0x34000000 0x0 0x100000>,
793 <0x0 0x35000000 0x0 0x100000>;
802 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
803 <0xd>; /* TX_CHAN */
804 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
805 <0xa>; /* RX_CHAN */
806 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
811 reg = <0x0 0x310d0000 0x0 0x400>;
821 #clock-cells = <0>;
834 reg = <0x0 0x600000 0x0 0x100>;
842 ti,davinci-gpio-unbanked = <0>;
843 clocks = <&k3_clks 57 0>;
849 reg = <0x0 0x601000 0x0 0x100>;
857 ti,davinci-gpio-unbanked = <0>;
858 clocks = <&k3_clks 58 0>;
864 …reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x…
869 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
870 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
871 ti,syscon-pcie-id = <&scm_conf 0x210>;
872 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
873 bus-range = <0x0 0xff>;
878 msi-map = <0x0 &gic_its 0x0 0x10000>;
885 …reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0…
888 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
899 …reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x…
904 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
905 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
906 ti,syscon-pcie-id = <&scm_conf 0x210>;
907 ti,syscon-pcie-mode = <&scm_conf 0x4070>;
908 bus-range = <0x0 0xff>;
913 msi-map = <0x0 &gic_its 0x10000 0x10000>;
920 …reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0…
923 ti,syscon-pcie-mode = <&scm_conf 0x4070>;
934 reg = <0x0 0x02b00000 0x0 0x2000>,
935 <0x0 0x02b08000 0x0 0x1000>;
941 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
944 clocks = <&k3_clks 104 0>;
952 reg = <0x0 0x02b10000 0x0 0x2000>,
953 <0x0 0x02b18000 0x0 0x1000>;
959 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
962 clocks = <&k3_clks 105 0>;
970 reg = <0x0 0x02b20000 0x0 0x2000>,
971 <0x0 0x02b28000 0x0 0x1000>;
977 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
980 clocks = <&k3_clks 106 0>;
988 reg = <0x0 0x06f03000 0x0 0x400>,
989 <0x0 0x06f03800 0x0 0x40>;
993 ti,camerrx-control = <&scm_conf 0x40c0>;
995 clocks = <&k3_clks 2 0>;
1000 #size-cells = <0>;
1002 csi2_0: port@0 {
1003 reg = <0>;
1010 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
1011 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
1012 <0x0 0x04a06000 0x0 0x1000>, /* vid */
1013 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
1014 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
1015 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
1016 <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */
1017 <0x0 0x04a01000 0x0 0x1000>; /* common1 */
1044 #size-cells = <0>;
1051 reg = <0x0 0x3000000 0x0 0x100>;
1053 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
1061 reg = <0x0 0x3010000 0x0 0x100>;
1063 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
1071 reg = <0x0 0x3020000 0x0 0x100>;
1073 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
1081 reg = <0x0 0x3030000 0x0 0x100>;
1083 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
1091 reg = <0x0 0x3040000 0x0 0x100>;
1093 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
1101 reg = <0x0 0x3050000 0x0 0x100>;
1103 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
1110 reg = <0x00 0xb000000 0x00 0x80000>;
1114 ranges = <0x0 0x00 0xb000000 0x80000>;
1116 icssg0_mem: memories@0 {
1117 reg = <0x0 0x2000>,
1118 <0x2000 0x2000>,
1119 <0x10000 0x10000>;
1126 reg = <0x26000 0x200>;
1129 ranges = <0x0 0x26000 0x2000>;
1133 #size-cells = <0>;
1136 reg = <0x3c>;
1137 #clock-cells = <0>;
1145 reg = <0x30>;
1146 #clock-cells = <0>;
1157 reg = <0x32000 0x100>;
1162 reg = <0x33000 0x1000>;
1167 reg = <0x20000 0x2000>;
1186 reg = <0x34000 0x4000>,
1187 <0x22000 0x100>,
1188 <0x22400 0x100>;
1195 reg = <0x4000 0x2000>,
1196 <0x23000 0x100>,
1197 <0x23400 0x100>;
1204 reg = <0xa000 0x1800>,
1205 <0x25000 0x100>,
1206 <0x25400 0x100>;
1213 reg = <0x38000 0x4000>,
1214 <0x24000 0x100>,
1215 <0x24400 0x100>;
1222 reg = <0x6000 0x2000>,
1223 <0x23800 0x100>,
1224 <0x23c00 0x100>;
1231 reg = <0xc000 0x1800>,
1232 <0x25800 0x100>,
1233 <0x25c00 0x100>;
1240 reg = <0x32400 0x100>;
1244 #size-cells = <0>;
1252 reg = <0x00 0xb100000 0x00 0x80000>;
1256 ranges = <0x0 0x00 0xb100000 0x80000>;
1258 icssg1_mem: memories@0 {
1259 reg = <0x0 0x2000>,
1260 <0x2000 0x2000>,
1261 <0x10000 0x10000>;
1268 reg = <0x26000 0x200>;
1271 ranges = <0x0 0x26000 0x2000>;
1275 #size-cells = <0>;
1278 reg = <0x3c>;
1279 #clock-cells = <0>;
1287 reg = <0x30>;
1288 #clock-cells = <0>;
1299 reg = <0x32000 0x100>;
1304 reg = <0x33000 0x1000>;
1309 reg = <0x20000 0x2000>;
1328 reg = <0x34000 0x4000>,
1329 <0x22000 0x100>,
1330 <0x22400 0x100>;
1337 reg = <0x4000 0x2000>,
1338 <0x23000 0x100>,
1339 <0x23400 0x100>;
1346 reg = <0xa000 0x1800>,
1347 <0x25000 0x100>,
1348 <0x25400 0x100>;
1355 reg = <0x38000 0x4000>,
1356 <0x24000 0x100>,
1357 <0x24400 0x100>;
1364 reg = <0x6000 0x2000>,
1365 <0x23800 0x100>,
1366 <0x23c00 0x100>;
1373 reg = <0xc000 0x1800>,
1374 <0x25800 0x100>,
1375 <0x25c00 0x100>;
1382 reg = <0x32400 0x100>;
1386 #size-cells = <0>;
1394 reg = <0x00 0xb200000 0x00 0x80000>;
1398 ranges = <0x0 0x00 0xb200000 0x80000>;
1400 icssg2_mem: memories@0 {
1401 reg = <0x0 0x2000>,
1402 <0x2000 0x2000>,
1403 <0x10000 0x10000>;
1410 reg = <0x26000 0x200>;
1413 ranges = <0x0 0x26000 0x2000>;
1417 #size-cells = <0>;
1420 reg = <0x3c>;
1421 #clock-cells = <0>;
1429 reg = <0x30>;
1430 #clock-cells = <0>;
1441 reg = <0x32000 0x100>;
1446 reg = <0x33000 0x1000>;
1451 reg = <0x20000 0x2000>;
1470 reg = <0x34000 0x4000>,
1471 <0x22000 0x100>,
1472 <0x22400 0x100>;
1479 reg = <0x4000 0x2000>,
1480 <0x23000 0x100>,
1481 <0x23400 0x100>;
1488 reg = <0xa000 0x1800>,
1489 <0x25000 0x100>,
1490 <0x25400 0x100>;
1497 reg = <0x38000 0x4000>,
1498 <0x24000 0x100>,
1499 <0x24400 0x100>;
1506 reg = <0x6000 0x2000>,
1507 <0x23800 0x100>,
1508 <0x23c00 0x100>;
1515 reg = <0xc000 0x1800>,
1516 <0x25800 0x100>,
1517 <0x25c00 0x100>;
1524 reg = <0x32400 0x100>;
1528 #size-cells = <0>;