Lines Matching +full:0 +full:x23800
13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
42 reg = <0x0 0x43000000 0x0 0x20000>;
45 ranges = <0x0 0x0 0x43000000 0x20000>;
49 reg = <0x00000014 0x4>;
55 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
60 reg = <0x4044 0x8>;
66 reg = <0x4130 0x4>;
78 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
79 <0x00 0x01840000 0x00 0xC0000>, /* GICR */
80 <0x01 0x00000000 0x00 0x2000>, /* GICC */
81 <0x01 0x00010000 0x00 0x1000>, /* GICH */
82 <0x01 0x00020000 0x00 0x2000>; /* GICV */
91 reg = <0x00 0x01820000 0x00 0x10000>;
92 socionext,synquacer-pre-its = <0x1000000 0x400000>;
103 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
111 reg = <0x00 0x4d000000 0x00 0x80000>,
112 <0x00 0x4a600000 0x00 0x80000>,
113 <0x00 0x4a400000 0x00 0x80000>;
120 reg = <0x00 0x48000000 0x00 0x100000>;
121 #interrupt-cells = <0>;
133 reg = <0x00 0x485c0100 0x00 0x100>,
134 <0x00 0x4c000000 0x00 0x20000>,
135 <0x00 0x4a820000 0x00 0x20000>,
136 <0x00 0x4aa40000 0x00 0x20000>,
137 <0x00 0x4bc00000 0x00 0x100000>;
144 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
145 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
146 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
151 reg = <0x00 0x485c0000 0x00 0x100>,
152 <0x00 0x4a800000 0x00 0x20000>,
153 <0x00 0x4aa00000 0x00 0x40000>,
154 <0x00 0x4b800000 0x00 0x400000>;
161 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
162 <0x24>, /* CPSW_TX_CHAN */
163 <0x25>, /* SAUL_TX_0_CHAN */
164 <0x26>, /* SAUL_TX_1_CHAN */
165 <0x27>, /* ICSSG_0_TX_CHAN */
166 <0x28>; /* ICSSG_1_TX_CHAN */
167 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
168 <0x11>, /* RING_CPSW_TX_CHAN */
169 <0x12>, /* RING_SAUL_TX_0_CHAN */
170 <0x13>, /* RING_SAUL_TX_1_CHAN */
171 <0x14>, /* RING_ICSSG_0_TX_CHAN */
172 <0x15>; /* RING_ICSSG_1_TX_CHAN */
173 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
174 <0x2b>, /* CPSW_RX_CHAN */
175 <0x2d>, /* SAUL_RX_0_CHAN */
176 <0x2f>, /* SAUL_RX_1_CHAN */
177 <0x31>, /* SAUL_RX_2_CHAN */
178 <0x33>, /* SAUL_RX_3_CHAN */
179 <0x35>, /* ICSSG_0_RX_CHAN */
180 <0x37>; /* ICSSG_1_RX_CHAN */
181 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
182 <0x2c>, /* FLOW_CPSW_RX_CHAN */
183 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
184 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
185 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
186 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
197 reg = <0x00 0x44043000 0x00 0xfe0>;
217 reg = <0x00 0xf4000 0x00 0x2d0>;
220 pinctrl-single,function-mask = <0xffffffff>;
225 reg = <0x00 0x2400000 0x00 0x400>;
237 reg = <0x00 0x2410000 0x00 0x400>;
249 reg = <0x00 0x2420000 0x00 0x400>;
261 reg = <0x00 0x2430000 0x00 0x400>;
273 reg = <0x00 0x2440000 0x00 0x400>;
285 reg = <0x00 0x2450000 0x00 0x400>;
297 reg = <0x00 0x2460000 0x00 0x400>;
309 reg = <0x00 0x2470000 0x00 0x400>;
321 reg = <0x00 0x2480000 0x00 0x400>;
333 reg = <0x00 0x2490000 0x00 0x400>;
345 reg = <0x00 0x24a0000 0x00 0x400>;
357 reg = <0x00 0x24b0000 0x00 0x400>;
369 reg = <0x00 0x420000 0x00 0x1000>;
375 reg = <0x00 0x02800000 0x00 0x100>;
379 clocks = <&k3_clks 146 0>;
386 reg = <0x00 0x02810000 0x00 0x100>;
390 clocks = <&k3_clks 152 0>;
397 reg = <0x00 0x02820000 0x00 0x100>;
401 clocks = <&k3_clks 153 0>;
408 reg = <0x00 0x02830000 0x00 0x100>;
412 clocks = <&k3_clks 154 0>;
419 reg = <0x00 0x02840000 0x00 0x100>;
423 clocks = <&k3_clks 155 0>;
430 reg = <0x00 0x02850000 0x00 0x100>;
434 clocks = <&k3_clks 156 0>;
441 reg = <0x00 0x02860000 0x00 0x100>;
445 clocks = <&k3_clks 158 0>;
452 reg = <0x00 0x20000000 0x00 0x100>;
455 #size-cells = <0>;
464 reg = <0x00 0x20010000 0x00 0x100>;
467 #size-cells = <0>;
476 reg = <0x00 0x20020000 0x00 0x100>;
479 #size-cells = <0>;
488 reg = <0x00 0x20030000 0x00 0x100>;
491 #size-cells = <0>;
500 reg = <0x00 0x20100000 0x00 0x400>;
503 #size-cells = <0>;
505 clocks = <&k3_clks 141 0>;
506 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
513 reg = <0x00 0x20110000 0x00 0x400>;
516 #size-cells = <0>;
518 clocks = <&k3_clks 142 0>;
524 reg = <0x00 0x20120000 0x00 0x400>;
527 #size-cells = <0>;
529 clocks = <&k3_clks 143 0>;
535 reg = <0x00 0x20130000 0x00 0x400>;
538 #size-cells = <0>;
540 clocks = <&k3_clks 144 0>;
546 reg = <0x00 0x20140000 0x00 0x400>;
549 #size-cells = <0>;
551 clocks = <&k3_clks 145 0>;
557 reg = <0x00 0x00a00000 0x00 0x800>;
564 ti,interrupt-ranges = <0 32 16>;
569 reg = <0x0 0x00600000 0x0 0x100>;
578 ti,davinci-gpio-unbanked = <0>;
580 clocks = <&k3_clks 77 0>;
586 reg = <0x0 0x00601000 0x0 0x100>;
595 ti,davinci-gpio-unbanked = <0>;
597 clocks = <&k3_clks 78 0>;
603 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
606 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
610 ti,trm-icp = <0x2>;
611 ti,otap-del-sel-legacy = <0x0>;
612 ti,otap-del-sel-mmc-hs = <0x0>;
613 ti,otap-del-sel-ddr52 = <0x6>;
614 ti,otap-del-sel-hs200 = <0x7>;
615 ti,itap-del-sel-legacy = <0x10>;
616 ti,itap-del-sel-mmc-hs = <0xa>;
617 ti,itap-del-sel-ddr52 = <0x3>;
623 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
628 ti,trm-icp = <0x2>;
629 ti,otap-del-sel-legacy = <0x0>;
630 ti,otap-del-sel-sd-hs = <0x0>;
631 ti,otap-del-sel-sdr12 = <0xf>;
632 ti,otap-del-sel-sdr25 = <0xf>;
633 ti,otap-del-sel-sdr50 = <0xc>;
634 ti,otap-del-sel-sdr104 = <0x6>;
635 ti,otap-del-sel-ddr50 = <0x9>;
636 ti,itap-del-sel-legacy = <0x0>;
637 ti,itap-del-sel-sd-hs = <0x0>;
638 ti,itap-del-sel-sdr12 = <0x0>;
639 ti,itap-del-sel-sdr25 = <0x0>;
640 ti,clkbuf-sel = <0x7>;
648 reg = <0x0 0x8000000 0x0 0x200000>;
650 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
651 clocks = <&k3_clks 13 0>;
657 dmas = <&main_pktdma 0xC500 15>,
658 <&main_pktdma 0xC501 15>,
659 <&main_pktdma 0xC502 15>,
660 <&main_pktdma 0xC503 15>,
661 <&main_pktdma 0xC504 15>,
662 <&main_pktdma 0xC505 15>,
663 <&main_pktdma 0xC506 15>,
664 <&main_pktdma 0xC507 15>,
665 <&main_pktdma 0x4500 15>;
671 #size-cells = <0>;
679 ti,syscon-efuse = <&main_conf 0x200>;
693 reg = <0x0 0xf00 0x0 0x100>;
695 #size-cells = <0>;
696 clocks = <&k3_clks 13 0>;
704 reg = <0x0 0x3d000 0x0 0x400>;
716 reg = <0x0 0x39000000 0x0 0x400>;
719 clocks = <&k3_clks 84 0>;
721 assigned-clocks = <&k3_clks 84 0>;
731 reg = <0x0 0xa40000 0x0 0x800>;
734 pinctrl-single,function-mask = <0x000107ff>;
739 reg = <0x00 0xf900000 0x00 0x100>;
750 reg = <0x00 0xf400000 0x00 0x10000>,
751 <0x00 0xf410000 0x00 0x10000>,
752 <0x00 0xf420000 0x00 0x10000>;
756 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
769 reg = <0x00 0x28001000 0x00 0x1000>;
771 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
772 clocks = <&k3_clks 0 0>;
773 assigned-clocks = <&k3_clks 0 0>;
774 assigned-clock-parents = <&k3_clks 0 3>;
787 reg = <0x00 0x0fc00000 0x00 0x70000>;
794 reg = <0x00 0x0fc40000 0x00 0x100>,
795 <0x05 0x00000000 0x01 0x00000000>;
799 cdns,trigger-address = <0x0>;
800 #address-cells = <0x1>;
801 #size-cells = <0x0>;
813 reg = <0x00 0x2a000000 0x00 0x1000>;
819 reg = <0x00 0x29020000 0x00 0x200>;
830 reg = <0x00 0x29030000 0x00 0x200>;
841 reg = <0x00 0x29040000 0x00 0x200>;
852 reg = <0x00 0x29050000 0x00 0x200>;
863 reg = <0x00 0x29060000 0x00 0x200>;
873 reg = <0x00 0x29070000 0x00 0x200>;
883 ti,cluster-mode = <0>;
886 ranges = <0x78000000 0x00 0x78000000 0x10000>,
887 <0x78100000 0x00 0x78100000 0x10000>,
888 <0x78200000 0x00 0x78200000 0x08000>,
889 <0x78300000 0x00 0x78300000 0x08000>;
894 reg = <0x78000000 0x00010000>,
895 <0x78100000 0x00010000>;
899 ti,sci-proc-ids = <0x01 0xff>;
909 reg = <0x78200000 0x00008000>,
910 <0x78300000 0x00008000>;
914 ti,sci-proc-ids = <0x02 0xff>;
925 ti,cluster-mode = <0>;
928 ranges = <0x78400000 0x00 0x78400000 0x10000>,
929 <0x78500000 0x00 0x78500000 0x10000>,
930 <0x78600000 0x00 0x78600000 0x08000>,
931 <0x78700000 0x00 0x78700000 0x08000>;
936 reg = <0x78400000 0x00010000>,
937 <0x78500000 0x00010000>;
941 ti,sci-proc-ids = <0x06 0xff>;
951 reg = <0x78600000 0x00008000>,
952 <0x78700000 0x00008000>;
956 ti,sci-proc-ids = <0x07 0xff>;
970 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
975 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
982 reg = <0x0f000000 0x00010000>;
984 resets = <&serdes_wiz0 0>;
996 #size-cells = <0>;
1003 reg = <0x00 0x0f102000 0x00 0x1000>,
1004 <0x00 0x0f100000 0x00 0x400>,
1005 <0x00 0x0d000000 0x00 0x00800000>,
1006 <0x00 0x68000000 0x00 0x00001000>;
1011 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
1015 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
1019 bus-range = <0x0 0xff>;
1021 vendor-id = <0x104c>;
1022 device-id = <0xb010>;
1023 msi-map = <0x0 &gic_its 0x0 0x10000>;
1024 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
1025 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
1026 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
1032 reg = <0x00 0x0f102000 0x00 0x1000>,
1033 <0x00 0x0f100000 0x00 0x400>,
1034 <0x00 0x0d000000 0x00 0x00800000>,
1035 <0x00 0x68000000 0x00 0x08000000>;
1039 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
1043 clocks = <&k3_clks 114 0>;
1052 reg = <0x0 0x23000000 0x0 0x100>;
1054 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
1062 reg = <0x0 0x23010000 0x0 0x100>;
1064 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
1072 reg = <0x0 0x23020000 0x0 0x100>;
1074 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
1082 reg = <0x0 0x23030000 0x0 0x100>;
1084 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
1092 reg = <0x0 0x23040000 0x0 0x100>;
1094 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
1102 reg = <0x0 0x23050000 0x0 0x100>;
1104 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
1112 reg = <0x0 0x23060000 0x0 0x100>;
1114 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
1122 reg = <0x0 0x23070000 0x0 0x100>;
1124 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
1132 reg = <0x0 0x23080000 0x0 0x100>;
1134 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
1142 reg = <0x0 0x23100000 0x0 0x60>;
1144 clocks = <&k3_clks 51 0>;
1152 reg = <0x0 0x23110000 0x0 0x60>;
1154 clocks = <&k3_clks 52 0>;
1162 reg = <0x0 0x23120000 0x0 0x60>;
1164 clocks = <&k3_clks 53 0>;
1171 reg = <0x00 0xe000000 0x00 0x100>;
1172 clocks = <&k3_clks 125 0>;
1174 assigned-clocks = <&k3_clks 125 0>;
1180 reg = <0x00 0xe010000 0x00 0x100>;
1181 clocks = <&k3_clks 126 0>;
1183 assigned-clocks = <&k3_clks 126 0>;
1189 reg = <0x00 0x30000000 0x00 0x80000>;
1193 ranges = <0x0 0x00 0x30000000 0x80000>;
1195 icssg0_mem: memories@0 {
1196 reg = <0x0 0x2000>,
1197 <0x2000 0x2000>,
1198 <0x10000 0x10000>;
1204 reg = <0x26000 0x200>;
1207 ranges = <0x0 0x26000 0x2000>;
1211 #size-cells = <0>;
1214 reg = <0x3c>;
1215 #clock-cells = <0>;
1216 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
1223 reg = <0x30>;
1224 #clock-cells = <0>;
1235 reg = <0x32000 0x100>;
1240 reg = <0x33000 0x1000>;
1245 reg = <0x20000 0x2000>;
1264 reg = <0x34000 0x3000>,
1265 <0x22000 0x100>,
1266 <0x22400 0x100>;
1273 reg = <0x4000 0x2000>,
1274 <0x23000 0x100>,
1275 <0x23400 0x100>;
1282 reg = <0xa000 0x1800>,
1283 <0x25000 0x100>,
1284 <0x25400 0x100>;
1291 reg = <0x38000 0x3000>,
1292 <0x24000 0x100>,
1293 <0x24400 0x100>;
1300 reg = <0x6000 0x2000>,
1301 <0x23800 0x100>,
1302 <0x23c00 0x100>;
1309 reg = <0xc000 0x1800>,
1310 <0x25800 0x100>,
1311 <0x25c00 0x100>;
1318 reg = <0x32400 0x100>;
1322 #size-cells = <0>;
1330 reg = <0x00 0x30080000 0x00 0x80000>;
1334 ranges = <0x0 0x00 0x30080000 0x80000>;
1336 icssg1_mem: memories@0 {
1337 reg = <0x0 0x2000>,
1338 <0x2000 0x2000>,
1339 <0x10000 0x10000>;
1345 reg = <0x26000 0x200>;
1348 ranges = <0x0 0x26000 0x2000>;
1352 #size-cells = <0>;
1355 reg = <0x3c>;
1356 #clock-cells = <0>;
1357 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
1364 reg = <0x30>;
1365 #clock-cells = <0>;
1376 reg = <0x32000 0x100>;
1381 reg = <0x33000 0x1000>;
1386 reg = <0x20000 0x2000>;
1405 reg = <0x34000 0x4000>,
1406 <0x22000 0x100>,
1407 <0x22400 0x100>;
1414 reg = <0x4000 0x2000>,
1415 <0x23000 0x100>,
1416 <0x23400 0x100>;
1423 reg = <0xa000 0x1800>,
1424 <0x25000 0x100>,
1425 <0x25400 0x100>;
1432 reg = <0x38000 0x4000>,
1433 <0x24000 0x100>,
1434 <0x24400 0x100>;
1441 reg = <0x6000 0x2000>,
1442 <0x23800 0x100>,
1443 <0x23c00 0x100>;
1450 reg = <0xc000 0x1800>,
1451 <0x25800 0x100>,
1452 <0x25c00 0x100>;
1459 reg = <0x32400 0x100>;
1461 #size-cells = <0>;
1462 clocks = <&k3_clks 82 0>;
1471 reg = <0x00 0x20701000 0x00 0x200>,
1472 <0x00 0x20708000 0x00 0x8000>;
1475 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>;
1480 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1486 reg = <0x00 0x20711000 0x00 0x200>,
1487 <0x00 0x20718000 0x00 0x8000>;
1490 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>;
1495 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1501 reg = <0x00 0x40900000 0x00 0x1200>;
1505 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
1506 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>,
1507 <&main_pktdma 0x4003 0>;
1512 reg = <0x00 0x40910000 0x00 0x7d>;
1521 clocks = <&k3_clks 80 0>;
1523 reg = <0x00 0x3b000000 0x00 0x400>,
1524 <0x00 0x50000000 0x00 0x8000000>;
1540 reg = <0x00 0x25010000 0x00 0x2000>;
1543 clocks = <&k3_clks 54 0>;
1550 reg = <0x00 0xb00000 0x00 0x400>,
1551 <0x00 0xb01000 0x00 0x400>;