dts/ti/k3-am625.dtsi

1 // SPDX-License-Identifier: GPL-2.0
7  * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62.dtsi"
16 		#address-cells = <1>;
17 		#size-cells = <0>;
19 		cpu-map {
40 			compatible = "arm,cortex-a53";
43 			enable-method = "psci";
44 			i-cache-size = <0x8000>;
45 			i-cache-line-size = <64>;
46 			i-cache-sets = <256>;
47 			d-cache-size = <0x8000>;
48 			d-cache-line-size = <64>;
49 			d-cache-sets = <128>;
50 			next-level-cache = <&L2_0>;
51 			operating-points-v2 = <&a53_opp_table>;
56 			compatible = "arm,cortex-a53";
59 			enable-method = "psci";
60 			i-cache-size = <0x8000>;
61 			i-cache-line-size = <64>;
62 			i-cache-sets = <256>;
63 			d-cache-size = <0x8000>;
64 			d-cache-line-size = <64>;
65 			d-cache-sets = <128>;
66 			next-level-cache = <&L2_0>;
67 			operating-points-v2 = <&a53_opp_table>;
72 			compatible = "arm,cortex-a53";
75 			enable-method = "psci";
76 			i-cache-size = <0x8000>;
77 			i-cache-line-size = <64>;
78 			i-cache-sets = <256>;
79 			d-cache-size = <0x8000>;
80 			d-cache-line-size = <64>;
81 			d-cache-sets = <128>;
82 			next-level-cache = <&L2_0>;
83 			operating-points-v2 = <&a53_opp_table>;
88 			compatible = "arm,cortex-a53";
91 			enable-method = "psci";
92 			i-cache-size = <0x8000>;
93 			i-cache-line-size = <64>;
94 			i-cache-sets = <256>;
95 			d-cache-size = <0x8000>;
96 			d-cache-line-size = <64>;
97 			d-cache-sets = <128>;
98 			next-level-cache = <&L2_0>;
99 			operating-points-v2 = <&a53_opp_table>;
104 	a53_opp_table: opp-table {
105 		compatible = "operating-points-v2-ti-cpu";
106 		opp-shared;
109 		opp-200000000 {
110 			opp-hz = /bits/ 64 <200000000>;
111 			opp-supported-hw = <0x01 0x0007>;
112 			clock-latency-ns = <6000000>;
115 		opp-400000000 {
116 			opp-hz = /bits/ 64 <400000000>;
117 			opp-supported-hw = <0x01 0x0007>;
118 			clock-latency-ns = <6000000>;
121 		opp-600000000 {
122 			opp-hz = /bits/ 64 <600000000>;
123 			opp-supported-hw = <0x01 0x0007>;
124 			clock-latency-ns = <6000000>;
127 		opp-800000000 {
128 			opp-hz = /bits/ 64 <800000000>;
129 			opp-supported-hw = <0x01 0x0007>;
130 			clock-latency-ns = <6000000>;
133 		opp-1000000000 {
134 			opp-hz = /bits/ 64 <1000000000>;
135 			opp-supported-hw = <0x01 0x0006>;
136 			clock-latency-ns = <6000000>;
139 		opp-1250000000 {
140 			opp-hz = /bits/ 64 <1250000000>;
141 			opp-supported-hw = <0x01 0x0004>;
142 			clock-latency-ns = <6000000>;
143 			opp-suspend;
147 	L2_0: l2-cache0 {
148 		compatible = "cache";
149 		cache-unified;
150 		cache-level = <2>;
151 		cache-size = <0x80000>;
152 		cache-line-size = <64>;
153 		cache-sets = <512>;