Lines Matching +full:exynos7 +full:- +full:i2s

1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <2>;
39 #size-cells = <0>;
41 cpu-map {
91 compatible = "arm,cortex-a72";
93 enable-method = "psci";
94 clock-frequency = <2400000000>;
95 cpu-idle-states = <&CPU_SLEEP>;
96 i-cache-size = <0xc000>;
97 i-cache-line-size = <64>;
98 i-cache-sets = <256>;
99 d-cache-size = <0x8000>;
100 d-cache-line-size = <64>;
101 d-cache-sets = <256>;
102 next-level-cache = <&cpucl_l2>;
107 compatible = "arm,cortex-a72";
109 enable-method = "psci";
110 clock-frequency = <2400000000>;
111 cpu-idle-states = <&CPU_SLEEP>;
112 i-cache-size = <0xc000>;
113 i-cache-line-size = <64>;
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000>;
116 d-cache-line-size = <64>;
117 d-cache-sets = <256>;
118 next-level-cache = <&cpucl_l2>;
123 compatible = "arm,cortex-a72";
125 enable-method = "psci";
126 clock-frequency = <2400000000>;
127 cpu-idle-states = <&CPU_SLEEP>;
128 i-cache-size = <0xc000>;
129 i-cache-line-size = <64>;
130 i-cache-sets = <256>;
131 d-cache-size = <0x8000>;
132 d-cache-line-size = <64>;
133 d-cache-sets = <256>;
134 next-level-cache = <&cpucl_l2>;
139 compatible = "arm,cortex-a72";
141 enable-method = "psci";
142 cpu-idle-states = <&CPU_SLEEP>;
143 i-cache-size = <0xc000>;
144 i-cache-line-size = <64>;
145 i-cache-sets = <256>;
146 d-cache-size = <0x8000>;
147 d-cache-line-size = <64>;
148 d-cache-sets = <256>;
149 next-level-cache = <&cpucl_l2>;
155 compatible = "arm,cortex-a72";
157 enable-method = "psci";
158 clock-frequency = <2400000000>;
159 cpu-idle-states = <&CPU_SLEEP>;
160 i-cache-size = <0xc000>;
161 i-cache-line-size = <64>;
162 i-cache-sets = <256>;
163 d-cache-size = <0x8000>;
164 d-cache-line-size = <64>;
165 d-cache-sets = <256>;
166 next-level-cache = <&cpucl_l2>;
171 compatible = "arm,cortex-a72";
173 enable-method = "psci";
174 clock-frequency = <2400000000>;
175 cpu-idle-states = <&CPU_SLEEP>;
176 i-cache-size = <0xc000>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <0x8000>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&cpucl_l2>;
187 compatible = "arm,cortex-a72";
189 enable-method = "psci";
190 clock-frequency = <2400000000>;
191 cpu-idle-states = <&CPU_SLEEP>;
192 i-cache-size = <0xc000>;
193 i-cache-line-size = <64>;
194 i-cache-sets = <256>;
195 d-cache-size = <0x8000>;
196 d-cache-line-size = <64>;
197 d-cache-sets = <256>;
198 next-level-cache = <&cpucl_l2>;
203 compatible = "arm,cortex-a72";
205 enable-method = "psci";
206 clock-frequency = <2400000000>;
207 cpu-idle-states = <&CPU_SLEEP>;
208 i-cache-size = <0xc000>;
209 i-cache-line-size = <64>;
210 i-cache-sets = <256>;
211 d-cache-size = <0x8000>;
212 d-cache-line-size = <64>;
213 d-cache-sets = <256>;
214 next-level-cache = <&cpucl_l2>;
220 compatible = "arm,cortex-a72";
222 enable-method = "psci";
223 clock-frequency = <2400000000>;
224 cpu-idle-states = <&CPU_SLEEP>;
225 i-cache-size = <0xc000>;
226 i-cache-line-size = <64>;
227 i-cache-sets = <256>;
228 d-cache-size = <0x8000>;
229 d-cache-line-size = <64>;
230 d-cache-sets = <256>;
231 next-level-cache = <&cpucl_l2>;
236 compatible = "arm,cortex-a72";
238 enable-method = "psci";
239 clock-frequency = <2400000000>;
240 cpu-idle-states = <&CPU_SLEEP>;
241 i-cache-size = <0xc000>;
242 i-cache-line-size = <64>;
243 i-cache-sets = <256>;
244 d-cache-size = <0x8000>;
245 d-cache-line-size = <64>;
246 d-cache-sets = <256>;
247 next-level-cache = <&cpucl_l2>;
252 compatible = "arm,cortex-a72";
254 enable-method = "psci";
255 clock-frequency = <2400000000>;
256 cpu-idle-states = <&CPU_SLEEP>;
257 i-cache-size = <0xc000>;
258 i-cache-line-size = <64>;
259 i-cache-sets = <256>;
260 d-cache-size = <0x8000>;
261 d-cache-line-size = <64>;
262 d-cache-sets = <256>;
263 next-level-cache = <&cpucl_l2>;
268 compatible = "arm,cortex-a72";
270 enable-method = "psci";
271 clock-frequency = <2400000000>;
272 cpu-idle-states = <&CPU_SLEEP>;
273 i-cache-size = <0xc000>;
274 i-cache-line-size = <64>;
275 i-cache-sets = <256>;
276 d-cache-size = <0x8000>;
277 d-cache-line-size = <64>;
278 d-cache-sets = <256>;
279 next-level-cache = <&cpucl_l2>;
282 cpucl_l2: l2-cache0 {
284 cache-level = <2>;
285 cache-unified;
286 cache-size = <0x400000>;
287 cache-line-size = <64>;
288 cache-sets = <4096>;
291 idle-states {
292 entry-method = "psci";
294 CPU_SLEEP: cpu-sleep {
295 idle-state-name = "c2";
296 compatible = "arm,idle-state";
297 local-timer-stop;
298 arm,psci-suspend-param = <0x0010000>;
299 entry-latency-us = <30>;
300 exit-latency-us = <75>;
301 min-residency-us = <300>;
306 arm-pmu {
307 compatible = "arm,armv8-pmuv3";
320 interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>,
327 compatible = "arm,psci-1.0";
332 compatible = "arm,armv8-timer";
340 compatible = "fixed-clock";
341 clock-output-names = "fin_pll";
342 #clock-cells = <0>;
346 compatible = "simple-bus";
347 #address-cells = <2>;
348 #size-cells = <2>;
350 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
352 gic: interrupt-controller@10400000 {
353 compatible = "arm,gic-v3";
354 #interrupt-cells = <3>;
355 interrupt-controller;
362 compatible = "arm,mmu-500";
364 #iommu-cells = <2>;
365 #global-interrupts = <7>;
367 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
369 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
374 /* Per context non-secure context interrupts, 0-3 interrupts */
382 compatible = "arm,mmu-500";
384 #iommu-cells = <2>;
385 #global-interrupts = <11>;
387 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
389 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
398 /* Per context non-secure context interrupts, 0-7 interrupts */
410 compatible = "arm,mmu-500";
412 #iommu-cells = <2>;
413 #global-interrupts = <5>;
415 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
417 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
420 /* Per context non-secure context interrupts, 0-1 interrupts */
426 compatible = "arm,mmu-500";
428 #iommu-cells = <2>;
429 #global-interrupts = <5>;
431 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
433 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
436 /* Per context non-secure context interrupts, 0-1 interrupts */
441 clock_imem: clock-controller@10010000 {
442 compatible = "tesla,fsd-clock-imem";
444 #clock-cells = <1>;
449 clock-names = "fin_pll",
455 clock_cmu: clock-controller@11c10000 {
456 compatible = "tesla,fsd-clock-cmu";
458 #clock-cells = <1>;
460 clock-names = "fin_pll";
463 clock_csi: clock-controller@12610000 {
464 compatible = "tesla,fsd-clock-cam_csi";
466 #clock-cells = <1>;
468 clock-names = "fin_pll";
471 sysreg_cam: system-controller@12630000 {
472 compatible = "tesla,fsd-cam-sysreg", "syscon";
476 clock_mfc: clock-controller@12810000 {
477 compatible = "tesla,fsd-clock-mfc";
479 #clock-cells = <1>;
481 clock-names = "fin_pll";
484 clock_peric: clock-controller@14010000 {
485 compatible = "tesla,fsd-clock-peric";
487 #clock-cells = <1>;
494 clock-names = "fin_pll",
502 sysreg_peric: system-controller@14030000 {
503 compatible = "tesla,fsd-peric-sysreg", "syscon";
507 clock_fsys0: clock-controller@15010000 {
508 compatible = "tesla,fsd-clock-fsys0";
510 #clock-cells = <1>;
515 clock-names = "fin_pll",
521 sysreg_fsys0: system-controller@15030000 {
522 compatible = "tesla,fsd-fsys0-sysreg", "syscon";
526 clock_fsys1: clock-controller@16810000 {
527 compatible = "tesla,fsd-clock-fsys1";
529 #clock-cells = <1>;
533 clock-names = "fin_pll",
538 sysreg_fsys1: system-controller@16830000 {
539 compatible = "tesla,fsd-fsys1-sysreg", "syscon";
543 mdma0: dma-controller@10100000 {
547 #dma-cells = <1>;
549 clock-names = "apb_pclk";
553 mdma1: dma-controller@10110000 {
557 #dma-cells = <1>;
559 clock-names = "apb_pclk";
563 pdma0: dma-controller@14280000 {
567 #dma-cells = <1>;
569 clock-names = "apb_pclk";
573 pdma1: dma-controller@14290000 {
577 #dma-cells = <1>;
579 clock-names = "apb_pclk";
584 compatible = "samsung,exynos4210-uart";
588 dma-names = "rx", "tx";
591 clock-names = "uart", "clk_uart_baud0";
596 compatible = "samsung,exynos4210-uart";
600 dma-names = "rx", "tx";
603 clock-names = "uart", "clk_uart_baud0";
607 pmu_system_controller: system-controller@11400000 {
608 compatible = "samsung,exynos7-pmu", "syscon";
613 compatible = "samsung,exynos7-wdt";
616 samsung,syscon-phandle = <&pmu_system_controller>;
618 clock-names = "watchdog";
622 compatible = "samsung,exynos7-wdt";
625 samsung,syscon-phandle = <&pmu_system_controller>;
627 clock-names = "watchdog";
631 compatible = "samsung,exynos7-wdt";
634 samsung,syscon-phandle = <&pmu_system_controller>;
636 clock-names = "watchdog";
640 compatible = "samsung,exynos4210-pwm";
642 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
643 #pwm-cells = <3>;
645 clock-names = "timers";
650 compatible = "samsung,exynos4210-pwm";
652 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
653 #pwm-cells = <3>;
655 clock-names = "timers";
660 compatible = "samsung,exynos7-hsi2c";
663 #address-cells = <1>;
664 #size-cells = <0>;
665 pinctrl-names = "default";
666 pinctrl-0 = <&hs_i2c0_bus>;
668 clock-names = "hsi2c";
673 compatible = "samsung,exynos7-hsi2c";
676 #address-cells = <1>;
677 #size-cells = <0>;
678 pinctrl-names = "default";
679 pinctrl-0 = <&hs_i2c1_bus>;
681 clock-names = "hsi2c";
686 compatible = "samsung,exynos7-hsi2c";
689 #address-cells = <1>;
690 #size-cells = <0>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&hs_i2c2_bus>;
694 clock-names = "hsi2c";
699 compatible = "samsung,exynos7-hsi2c";
702 #address-cells = <1>;
703 #size-cells = <0>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&hs_i2c3_bus>;
707 clock-names = "hsi2c";
712 compatible = "samsung,exynos7-hsi2c";
715 #address-cells = <1>;
716 #size-cells = <0>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&hs_i2c4_bus>;
720 clock-names = "hsi2c";
725 compatible = "samsung,exynos7-hsi2c";
728 #address-cells = <1>;
729 #size-cells = <0>;
730 pinctrl-names = "default";
731 pinctrl-0 = <&hs_i2c5_bus>;
733 clock-names = "hsi2c";
738 compatible = "samsung,exynos7-hsi2c";
741 #address-cells = <1>;
742 #size-cells = <0>;
743 pinctrl-names = "default";
744 pinctrl-0 = <&hs_i2c6_bus>;
746 clock-names = "hsi2c";
751 compatible = "samsung,exynos7-hsi2c";
754 #address-cells = <1>;
755 #size-cells = <0>;
756 pinctrl-names = "default";
757 pinctrl-0 = <&hs_i2c7_bus>;
759 clock-names = "hsi2c";
763 i2s_0: i2s@140e0000 {
764 compatible = "tesla,fsd-i2s";
768 dma-names = "tx", "rx", "tx-sec";
769 #clock-cells = <1>;
773 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
774 pinctrl-names = "default";
775 pinctrl-0 = <&i2s0_bus>;
776 #sound-dai-cells = <1>;
780 i2s_1: i2s@140f0000 {
781 compatible = "tesla,fsd-i2s";
785 dma-names = "tx", "rx", "tx-sec";
786 #clock-cells = <1>;
790 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
791 pinctrl-names = "default";
792 pinctrl-0 = <&i2s1_bus>;
793 #sound-dai-cells = <1>;
798 compatible = "tesla,fsd-pinctrl";
803 compatible = "tesla,fsd-pinctrl";
809 compatible = "tesla,fsd-pinctrl";
818 reg-names = "m_can", "message_ram";
821 interrupt-names = "int0", "int1";
822 pinctrl-names = "default";
823 pinctrl-0 = <&m_can0_bus>;
826 clock-names = "hclk", "cclk";
827 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
835 reg-names = "m_can", "message_ram";
838 interrupt-names = "int0", "int1";
839 pinctrl-names = "default";
840 pinctrl-0 = <&m_can1_bus>;
843 clock-names = "hclk", "cclk";
844 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
852 reg-names = "m_can", "message_ram";
855 interrupt-names = "int0", "int1";
856 pinctrl-names = "default";
857 pinctrl-0 = <&m_can2_bus>;
860 clock-names = "hclk", "cclk";
861 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
869 reg-names = "m_can", "message_ram";
872 interrupt-names = "int0", "int1";
873 pinctrl-names = "default";
874 pinctrl-0 = <&m_can3_bus>;
877 clock-names = "hclk", "cclk";
878 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
883 compatible = "tesla,fsd-spi";
887 dma-names = "tx", "rx";
888 #address-cells = <1>;
889 #size-cells = <0>;
892 clock-names = "spi", "spi_busclk0";
893 samsung,spi-src-clk = <0>;
894 pinctrl-names = "default";
895 pinctrl-0 = <&spi0_bus>;
896 num-cs = <1>;
901 compatible = "tesla,fsd-spi";
905 dma-names = "tx", "rx";
906 #address-cells = <1>;
907 #size-cells = <0>;
910 clock-names = "spi", "spi_busclk0";
911 samsung,spi-src-clk = <0>;
912 pinctrl-names = "default";
913 pinctrl-0 = <&spi1_bus>;
914 num-cs = <1>;
919 compatible = "tesla,fsd-spi";
923 dma-names = "tx", "rx";
924 #address-cells = <1>;
925 #size-cells = <0>;
928 clock-names = "spi", "spi_busclk0";
929 samsung,spi-src-clk = <0>;
930 pinctrl-names = "default";
931 pinctrl-0 = <&spi2_bus>;
932 num-cs = <1>;
937 compatible = "tesla,fsd-mct", "samsung,exynos4210-mct";
956 clock-names = "fin_pll", "mct";
960 compatible = "tesla,fsd-ufs";
965 reg-names = "hci", "vs_hci", "unipro", "ufsp";
969 clock-names = "core_clk", "sclk_unipro_main";
970 freq-table-hz = <0 0>, <0 0>;
971 pinctrl-names = "default";
972 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
974 phy-names = "ufs-phy";
978 ufs_phy: ufs-phy@15124000 {
979 compatible = "tesla,fsd-ufs-phy";
981 reg-names = "phy-pma";
982 samsung,pmu-syscon = <&pmu_system_controller>;
983 #phy-cells = <0>;
985 clock-names = "ref_clk";
990 #include "fsd-pinctrl.dtsi"