Lines Matching +full:uniphier +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
42 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 next-level-cache = <&l2>;
47 operating-points-v2 = <&cluster0_opp>;
48 #cooling-cells = <2>;
53 compatible = "arm,cortex-a53";
56 enable-method = "psci";
57 next-level-cache = <&l2>;
58 operating-points-v2 = <&cluster0_opp>;
59 #cooling-cells = <2>;
64 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 next-level-cache = <&l2>;
69 operating-points-v2 = <&cluster0_opp>;
70 #cooling-cells = <2>;
75 compatible = "arm,cortex-a53";
78 enable-method = "psci";
79 next-level-cache = <&l2>;
80 operating-points-v2 = <&cluster0_opp>;
81 #cooling-cells = <2>;
84 l2: l2-cache {
89 cluster0_opp: opp-table {
90 compatible = "operating-points-v2";
91 opp-shared;
93 opp-250000000 {
94 opp-hz = /bits/ 64 <250000000>;
95 clock-latency-ns = <300>;
97 opp-325000000 {
98 opp-hz = /bits/ 64 <325000000>;
99 clock-latency-ns = <300>;
101 opp-500000000 {
102 opp-hz = /bits/ 64 <500000000>;
103 clock-latency-ns = <300>;
105 opp-650000000 {
106 opp-hz = /bits/ 64 <650000000>;
107 clock-latency-ns = <300>;
109 opp-666667000 {
110 opp-hz = /bits/ 64 <666667000>;
111 clock-latency-ns = <300>;
113 opp-866667000 {
114 opp-hz = /bits/ 64 <866667000>;
115 clock-latency-ns = <300>;
117 opp-1000000000 {
118 opp-hz = /bits/ 64 <1000000000>;
119 clock-latency-ns = <300>;
121 opp-1300000000 {
122 opp-hz = /bits/ 64 <1300000000>;
123 clock-latency-ns = <300>;
128 compatible = "arm,psci-1.0";
134 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 clock-frequency = <25000000>;
140 emmc_pwrseq: emmc-pwrseq {
141 compatible = "mmc-pwrseq-emmc";
142 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
146 compatible = "arm,armv8-timer";
153 thermal-zones {
154 cpu-thermal {
155 polling-delay-passive = <250>; /* 250ms */
156 polling-delay = <1000>; /* 1000ms */
157 thermal-sensors = <&pvtctl>;
160 cpu_crit: cpu-crit {
165 cpu_alert: cpu-alert {
172 cooling-maps {
175 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
184 reserved-memory {
185 #address-cells = <2>;
186 #size-cells = <2>;
189 secure-memory@81000000 {
191 no-map;
196 compatible = "simple-bus";
197 #address-cells = <1>;
198 #size-cells = <1>;
202 compatible = "socionext,uniphier-scssi";
205 #address-cells = <1>;
206 #size-cells = <0>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_spi0>;
215 compatible = "socionext,uniphier-scssi";
218 #address-cells = <1>;
219 #size-cells = <0>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_spi1>;
228 compatible = "socionext,uniphier-uart";
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_uart0>;
239 compatible = "socionext,uniphier-uart";
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_uart1>;
250 compatible = "socionext,uniphier-uart";
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart2>;
261 compatible = "socionext,uniphier-uart";
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_uart3>;
271 gpio: gpio@55000000 { label
272 compatible = "socionext,uniphier-gpio";
274 interrupt-parent = <&aidet>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 gpio-controller;
278 #gpio-cells = <2>;
279 gpio-ranges = <&pinctrl 0 0 0>,
282 gpio-ranges-group-names = "gpio_range0",
286 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
291 compatible = "socionext,uniphier-fi2c";
294 #address-cells = <1>;
295 #size-cells = <0>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_i2c0>;
301 clock-frequency = <100000>;
305 compatible = "socionext,uniphier-fi2c";
308 #address-cells = <1>;
309 #size-cells = <0>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_i2c1>;
315 clock-frequency = <100000>;
319 compatible = "socionext,uniphier-fi2c";
322 #address-cells = <1>;
323 #size-cells = <0>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_i2c2>;
329 clock-frequency = <100000>;
333 compatible = "socionext,uniphier-fi2c";
336 #address-cells = <1>;
337 #size-cells = <0>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_i2c3>;
343 clock-frequency = <100000>;
346 /* chip-internal connection for HDMI */
348 compatible = "socionext,uniphier-fi2c";
350 #address-cells = <1>;
351 #size-cells = <0>;
355 clock-frequency = <400000>;
358 system_bus: system-bus@58c00000 {
359 compatible = "socionext,uniphier-system-bus";
362 #address-cells = <2>;
363 #size-cells = <1>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_system_bus>;
369 compatible = "socionext,uniphier-smpctrl";
374 compatible = "socionext,uniphier-pxs3-sdctrl",
375 "simple-mfd", "syscon";
378 sd_clk: clock-controller {
379 compatible = "socionext,uniphier-pxs3-sd-clock";
380 #clock-cells = <1>;
383 sd_rst: reset-controller {
384 compatible = "socionext,uniphier-pxs3-sd-reset";
385 #reset-cells = <1>;
390 compatible = "socionext,uniphier-pxs3-perictrl",
391 "simple-mfd", "syscon";
394 peri_clk: clock-controller {
395 compatible = "socionext,uniphier-pxs3-peri-clock";
396 #clock-cells = <1>;
399 peri_rst: reset-controller {
400 compatible = "socionext,uniphier-pxs3-peri-reset";
401 #reset-cells = <1>;
406 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_emmc>;
413 bus-width = <8>;
414 mmc-ddr-1_8v;
415 mmc-hs200-1_8v;
416 mmc-pwrseq = <&emmc_pwrseq>;
417 cdns,phy-input-delay-legacy = <9>;
418 cdns,phy-input-delay-mmc-highspeed = <2>;
419 cdns,phy-input-delay-mmc-ddr = <3>;
420 cdns,phy-dll-delay-sdclk = <21>;
421 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
425 compatible = "socionext,uniphier-sd-v3.1.1";
429 pinctrl-names = "default", "uhs";
430 pinctrl-0 = <&pinctrl_sd>;
431 pinctrl-1 = <&pinctrl_sd_uhs>;
433 reset-names = "host";
435 bus-width = <4>;
436 cap-sd-highspeed;
437 sd-uhs-sdr12;
438 sd-uhs-sdr25;
439 sd-uhs-sdr50;
440 socionext,syscon-uhs-mode = <&sdctrl 0>;
444 compatible = "socionext,uniphier-pxs3-soc-glue",
445 "simple-mfd", "syscon";
449 compatible = "socionext,uniphier-pxs3-pinctrl";
454 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
455 "simple-mfd", "syscon";
457 #address-cells = <1>;
458 #size-cells = <1>;
462 compatible = "socionext,uniphier-efuse";
467 compatible = "socionext,uniphier-efuse";
469 #address-cells = <1>;
470 #size-cells = <1>;
516 xdmac: dma-controller@5fc10000 {
517 compatible = "socionext,uniphier-xdmac";
520 dma-channels = <16>;
521 #dma-cells = <2>;
524 aidet: interrupt-controller@5fc20000 {
525 compatible = "socionext,uniphier-pxs3-aidet";
527 interrupt-controller;
528 #interrupt-cells = <2>;
531 gic: interrupt-controller@5fe00000 {
532 compatible = "arm,gic-v3";
535 interrupt-controller;
536 #interrupt-cells = <3>;
541 compatible = "socionext,uniphier-pxs3-sysctrl",
542 "simple-mfd", "syscon";
545 sys_clk: clock-controller {
546 compatible = "socionext,uniphier-pxs3-clock";
547 #clock-cells = <1>;
550 sys_rst: reset-controller {
551 compatible = "socionext,uniphier-pxs3-reset";
552 #reset-cells = <1>;
556 compatible = "socionext,uniphier-wdt";
559 pvtctl: thermal-sensor {
560 compatible = "socionext,uniphier-pxs3-thermal";
562 #thermal-sensor-cells = <0>;
563 socionext,tmod-calibration = <0x0f22 0x68ee>;
568 compatible = "socionext,uniphier-pxs3-ave4";
572 pinctrl-names = "default";
573 pinctrl-0 = <&pinctrl_ether_rgmii>;
574 clock-names = "ether";
576 reset-names = "ether";
578 phy-mode = "rgmii-id";
579 local-mac-address = [00 00 00 00 00 00];
580 socionext,syscon-phy-mode = <&soc_glue 0>;
583 #address-cells = <1>;
584 #size-cells = <0>;
589 compatible = "socionext,uniphier-pxs3-ave4";
593 pinctrl-names = "default";
594 pinctrl-0 = <&pinctrl_ether1_rgmii>;
595 clock-names = "ether";
597 reset-names = "ether";
599 phy-mode = "rgmii-id";
600 local-mac-address = [00 00 00 00 00 00];
601 socionext,syscon-phy-mode = <&soc_glue 1>;
604 #address-cells = <1>;
605 #size-cells = <0>;
610 compatible = "socionext,uniphier-pxs3-ahci",
611 "generic-ahci";
617 ports-implemented = <1>;
621 sata-controller@65700000 {
622 compatible = "socionext,uniphier-pxs3-ahci-glue",
623 "simple-mfd";
625 #address-cells = <1>;
626 #size-cells = <1>;
629 ahci0_rst: reset-controller@0 {
630 compatible = "socionext,uniphier-pxs3-ahci-reset";
632 clock-names = "link";
634 reset-names = "link";
636 #reset-cells = <1>;
639 ahci0_phy: sata-phy@10 {
640 compatible = "socionext,uniphier-pxs3-ahci-phy";
642 clock-names = "link", "phy";
644 reset-names = "link", "phy";
646 #phy-cells = <0>;
651 compatible = "socionext,uniphier-pxs3-ahci",
652 "generic-ahci";
658 ports-implemented = <1>;
662 sata-controller@65900000 {
663 compatible = "socionext,uniphier-pxs3-ahci-glue",
664 "simple-mfd";
666 #address-cells = <1>;
667 #size-cells = <1>;
670 ahci1_rst: reset-controller@0 {
671 compatible = "socionext,uniphier-pxs3-ahci-reset";
673 clock-names = "link";
675 reset-names = "link";
677 #reset-cells = <1>;
680 ahci1_phy: sata-phy@10 {
681 compatible = "socionext,uniphier-pxs3-ahci-phy";
683 clock-names = "link", "phy";
685 reset-names = "link", "phy";
687 #phy-cells = <0>;
692 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
695 interrupt-names = "dwc_usb3";
697 pinctrl-names = "default";
698 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
699 clock-names = "ref", "bus_early", "suspend";
707 usb-controller@65b00000 {
708 compatible = "socionext,uniphier-pxs3-dwc3-glue",
709 "simple-mfd";
711 #address-cells = <1>;
712 #size-cells = <1>;
715 usb0_rst: reset-controller@0 {
716 compatible = "socionext,uniphier-pxs3-usb3-reset";
718 #reset-cells = <1>;
719 clock-names = "link";
721 reset-names = "link";
726 compatible = "socionext,uniphier-pxs3-usb3-regulator";
728 clock-names = "link";
730 reset-names = "link";
735 compatible = "socionext,uniphier-pxs3-usb3-regulator";
737 clock-names = "link";
739 reset-names = "link";
744 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
746 #phy-cells = <0>;
747 clock-names = "link", "phy";
749 reset-names = "link", "phy";
751 vbus-supply = <&usb0_vbus0>;
752 nvmem-cell-names = "rterm", "sel_t", "hs_i";
753 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
758 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
760 #phy-cells = <0>;
761 clock-names = "link", "phy";
763 reset-names = "link", "phy";
765 vbus-supply = <&usb0_vbus1>;
766 nvmem-cell-names = "rterm", "sel_t", "hs_i";
767 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
772 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
774 #phy-cells = <0>;
775 clock-names = "link", "phy";
777 reset-names = "link", "phy";
779 vbus-supply = <&usb0_vbus0>;
783 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
785 #phy-cells = <0>;
786 clock-names = "link", "phy";
788 reset-names = "link", "phy";
790 vbus-supply = <&usb0_vbus1>;
795 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
798 interrupt-names = "dwc_usb3";
800 pinctrl-names = "default";
801 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
802 clock-names = "ref", "bus_early", "suspend";
810 usb-controller@65d00000 {
811 compatible = "socionext,uniphier-pxs3-dwc3-glue",
812 "simple-mfd";
814 #address-cells = <1>;
815 #size-cells = <1>;
818 usb1_rst: reset-controller@0 {
819 compatible = "socionext,uniphier-pxs3-usb3-reset";
821 #reset-cells = <1>;
822 clock-names = "link";
824 reset-names = "link";
829 compatible = "socionext,uniphier-pxs3-usb3-regulator";
831 clock-names = "link";
833 reset-names = "link";
838 compatible = "socionext,uniphier-pxs3-usb3-regulator";
840 clock-names = "link";
842 reset-names = "link";
847 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
849 #phy-cells = <0>;
850 clock-names = "link", "phy", "phy-ext";
853 reset-names = "link", "phy";
855 vbus-supply = <&usb1_vbus0>;
856 nvmem-cell-names = "rterm", "sel_t", "hs_i";
857 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
862 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
864 #phy-cells = <0>;
865 clock-names = "link", "phy", "phy-ext";
868 reset-names = "link", "phy";
870 vbus-supply = <&usb1_vbus1>;
871 nvmem-cell-names = "rterm", "sel_t", "hs_i";
872 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
877 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
879 #phy-cells = <0>;
880 clock-names = "link", "phy", "phy-ext";
883 reset-names = "link", "phy";
885 vbus-supply = <&usb1_vbus0>;
890 compatible = "socionext,uniphier-pcie";
892 reg-names = "dbi", "link", "config";
895 #address-cells = <3>;
896 #size-cells = <2>;
899 num-lanes = <1>;
900 num-viewport = <1>;
901 bus-range = <0x0 0xff>;
906 /* non-prefetchable memory */
908 #interrupt-cells = <1>;
909 interrupt-names = "dma", "msi";
912 interrupt-map-mask = <0 0 0 7>;
913 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
917 phy-names = "pcie-phy";
920 pcie_intc: legacy-interrupt-controller {
921 interrupt-controller;
922 #interrupt-cells = <1>;
923 interrupt-parent = <&gic>;
929 compatible = "socionext,uniphier-pxs3-pcie-phy";
931 #phy-cells = <0>;
932 clock-names = "link";
934 reset-names = "link";
939 nand: nand-controller@68000000 {
940 compatible = "socionext,uniphier-denali-nand-v5b";
942 reg-names = "nand_data", "denali_reg";
944 #address-cells = <1>;
945 #size-cells = <0>;
947 pinctrl-names = "default";
948 pinctrl-0 = <&pinctrl_nand>;
949 clock-names = "nand", "nand_x", "ecc";
951 reset-names = "nand", "reg";
957 #include "uniphier-pinctrl.dtsi"