Lines Matching +full:opp +full:- +full:1100000000
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-ld20";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
45 compatible = "arm,cortex-a72";
48 enable-method = "psci";
49 next-level-cache = <&a72_l2>;
50 operating-points-v2 = <&cluster0_opp>;
51 #cooling-cells = <2>;
56 compatible = "arm,cortex-a72";
59 enable-method = "psci";
60 next-level-cache = <&a72_l2>;
61 operating-points-v2 = <&cluster0_opp>;
62 #cooling-cells = <2>;
67 compatible = "arm,cortex-a53";
70 enable-method = "psci";
71 next-level-cache = <&a53_l2>;
72 operating-points-v2 = <&cluster1_opp>;
73 #cooling-cells = <2>;
78 compatible = "arm,cortex-a53";
81 enable-method = "psci";
82 next-level-cache = <&a53_l2>;
83 operating-points-v2 = <&cluster1_opp>;
84 #cooling-cells = <2>;
87 a72_l2: l2-cache0 {
91 a53_l2: l2-cache1 {
96 cluster0_opp: opp-table-0 {
97 compatible = "operating-points-v2";
98 opp-shared;
100 opp-250000000 {
101 opp-hz = /bits/ 64 <250000000>;
102 clock-latency-ns = <300>;
104 opp-275000000 {
105 opp-hz = /bits/ 64 <275000000>;
106 clock-latency-ns = <300>;
108 opp-500000000 {
109 opp-hz = /bits/ 64 <500000000>;
110 clock-latency-ns = <300>;
112 opp-550000000 {
113 opp-hz = /bits/ 64 <550000000>;
114 clock-latency-ns = <300>;
116 opp-666667000 {
117 opp-hz = /bits/ 64 <666667000>;
118 clock-latency-ns = <300>;
120 opp-733334000 {
121 opp-hz = /bits/ 64 <733334000>;
122 clock-latency-ns = <300>;
124 opp-1000000000 {
125 opp-hz = /bits/ 64 <1000000000>;
126 clock-latency-ns = <300>;
128 opp-1100000000 {
129 opp-hz = /bits/ 64 <1100000000>;
130 clock-latency-ns = <300>;
134 cluster1_opp: opp-table-1 {
135 compatible = "operating-points-v2";
136 opp-shared;
138 opp-250000000 {
139 opp-hz = /bits/ 64 <250000000>;
140 clock-latency-ns = <300>;
142 opp-275000000 {
143 opp-hz = /bits/ 64 <275000000>;
144 clock-latency-ns = <300>;
146 opp-500000000 {
147 opp-hz = /bits/ 64 <500000000>;
148 clock-latency-ns = <300>;
150 opp-550000000 {
151 opp-hz = /bits/ 64 <550000000>;
152 clock-latency-ns = <300>;
154 opp-666667000 {
155 opp-hz = /bits/ 64 <666667000>;
156 clock-latency-ns = <300>;
158 opp-733334000 {
159 opp-hz = /bits/ 64 <733334000>;
160 clock-latency-ns = <300>;
162 opp-1000000000 {
163 opp-hz = /bits/ 64 <1000000000>;
164 clock-latency-ns = <300>;
166 opp-1100000000 {
167 opp-hz = /bits/ 64 <1100000000>;
168 clock-latency-ns = <300>;
173 compatible = "arm,psci-1.0";
179 compatible = "fixed-clock";
180 #clock-cells = <0>;
181 clock-frequency = <25000000>;
185 emmc_pwrseq: emmc-pwrseq {
186 compatible = "mmc-pwrseq-emmc";
187 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
191 compatible = "arm,armv8-timer";
198 thermal-zones {
199 cpu-thermal {
200 polling-delay-passive = <250>; /* 250ms */
201 polling-delay = <1000>; /* 1000ms */
202 thermal-sensors = <&pvtctl>;
205 cpu_crit: cpu-crit {
210 cpu_alert: cpu-alert {
217 cooling-maps {
220 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
229 reserved-memory {
230 #address-cells = <2>;
231 #size-cells = <2>;
234 secure-memory@81000000 {
236 no-map;
241 compatible = "simple-bus";
242 #address-cells = <1>;
243 #size-cells = <1>;
247 compatible = "socionext,uniphier-scssi";
250 #address-cells = <1>;
251 #size-cells = <0>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_spi0>;
260 compatible = "socionext,uniphier-scssi";
263 #address-cells = <1>;
264 #size-cells = <0>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_spi1>;
273 compatible = "socionext,uniphier-scssi";
276 #address-cells = <1>;
277 #size-cells = <0>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_spi2>;
286 compatible = "socionext,uniphier-scssi";
289 #address-cells = <1>;
290 #size-cells = <0>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_spi3>;
299 compatible = "socionext,uniphier-uart";
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_uart0>;
310 compatible = "socionext,uniphier-uart";
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_uart1>;
321 compatible = "socionext,uniphier-uart";
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_uart2>;
332 compatible = "socionext,uniphier-uart";
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_uart3>;
343 compatible = "socionext,uniphier-gpio";
345 interrupt-parent = <&aidet>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 gpio-controller;
349 #gpio-cells = <2>;
350 gpio-ranges = <&pinctrl 0 0 0>,
353 gpio-ranges-group-names = "gpio_range0",
357 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
362 compatible = "socionext,uniphier-ld20-aio";
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_aout1>,
368 clock-names = "aio";
370 reset-names = "aio";
372 #sound-dai-cells = <1>;
387 dai-format = "i2s";
388 remote-endpoint = <&evea_line>;
399 dai-format = "i2s";
400 remote-endpoint = <&evea_hp>;
426 compatible = "socionext,uniphier-evea";
428 clock-names = "evea", "exiv";
430 reset-names = "evea", "exiv", "adamv";
432 #sound-dai-cells = <1>;
436 remote-endpoint = <&i2s_line>;
442 remote-endpoint = <&i2s_hp>;
448 compatible = "socionext,uniphier-ld20-adamv",
449 "simple-mfd", "syscon";
452 adamv_rst: reset-controller {
453 compatible = "socionext,uniphier-ld20-adamv-reset";
454 #reset-cells = <1>;
459 compatible = "socionext,uniphier-fi2c";
462 #address-cells = <1>;
463 #size-cells = <0>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_i2c0>;
469 clock-frequency = <100000>;
473 compatible = "socionext,uniphier-fi2c";
476 #address-cells = <1>;
477 #size-cells = <0>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&pinctrl_i2c1>;
483 clock-frequency = <100000>;
487 compatible = "socionext,uniphier-fi2c";
489 #address-cells = <1>;
490 #size-cells = <0>;
494 clock-frequency = <400000>;
498 compatible = "socionext,uniphier-fi2c";
501 #address-cells = <1>;
502 #size-cells = <0>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_i2c3>;
508 clock-frequency = <100000>;
512 compatible = "socionext,uniphier-fi2c";
515 #address-cells = <1>;
516 #size-cells = <0>;
518 pinctrl-names = "default";
519 pinctrl-0 = <&pinctrl_i2c4>;
522 clock-frequency = <100000>;
526 compatible = "socionext,uniphier-fi2c";
528 #address-cells = <1>;
529 #size-cells = <0>;
533 clock-frequency = <400000>;
536 system_bus: system-bus@58c00000 {
537 compatible = "socionext,uniphier-system-bus";
540 #address-cells = <2>;
541 #size-cells = <1>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_system_bus>;
547 compatible = "socionext,uniphier-smpctrl";
552 compatible = "socionext,uniphier-ld20-sdctrl",
553 "simple-mfd", "syscon";
556 sd_clk: clock-controller {
557 compatible = "socionext,uniphier-ld20-sd-clock";
558 #clock-cells = <1>;
561 sd_rst: reset-controller {
562 compatible = "socionext,uniphier-ld20-sd-reset";
563 #reset-cells = <1>;
568 compatible = "socionext,uniphier-ld20-perictrl",
569 "simple-mfd", "syscon";
572 peri_clk: clock-controller {
573 compatible = "socionext,uniphier-ld20-peri-clock";
574 #clock-cells = <1>;
577 peri_rst: reset-controller {
578 compatible = "socionext,uniphier-ld20-peri-reset";
579 #reset-cells = <1>;
584 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
587 pinctrl-names = "default";
588 pinctrl-0 = <&pinctrl_emmc>;
591 bus-width = <8>;
592 mmc-ddr-1_8v;
593 mmc-hs200-1_8v;
594 mmc-pwrseq = <&emmc_pwrseq>;
595 cdns,phy-input-delay-legacy = <9>;
596 cdns,phy-input-delay-mmc-highspeed = <2>;
597 cdns,phy-input-delay-mmc-ddr = <3>;
598 cdns,phy-dll-delay-sdclk = <21>;
599 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
603 compatible = "socionext,uniphier-sd-v3.1.1";
607 pinctrl-names = "default";
608 pinctrl-0 = <&pinctrl_sd>;
610 reset-names = "host";
612 bus-width = <4>;
613 cap-sd-highspeed;
614 socionext,syscon-uhs-mode = <&sdctrl 0>;
618 compatible = "socionext,uniphier-ld20-soc-glue",
619 "simple-mfd", "syscon";
623 compatible = "socionext,uniphier-ld20-pinctrl";
628 compatible = "socionext,uniphier-ld20-soc-glue-debug",
629 "simple-mfd", "syscon";
631 #address-cells = <1>;
632 #size-cells = <1>;
636 compatible = "socionext,uniphier-efuse";
641 compatible = "socionext,uniphier-efuse";
643 #address-cells = <1>;
644 #size-cells = <1>;
690 xdmac: dma-controller@5fc10000 {
691 compatible = "socionext,uniphier-xdmac";
694 dma-channels = <16>;
695 #dma-cells = <2>;
698 aidet: interrupt-controller@5fc20000 {
699 compatible = "socionext,uniphier-ld20-aidet";
701 interrupt-controller;
702 #interrupt-cells = <2>;
705 gic: interrupt-controller@5fe00000 {
706 compatible = "arm,gic-v3";
709 interrupt-controller;
710 #interrupt-cells = <3>;
715 compatible = "socionext,uniphier-ld20-sysctrl",
716 "simple-mfd", "syscon";
719 sys_clk: clock-controller {
720 compatible = "socionext,uniphier-ld20-clock";
721 #clock-cells = <1>;
724 sys_rst: reset-controller {
725 compatible = "socionext,uniphier-ld20-reset";
726 #reset-cells = <1>;
730 compatible = "socionext,uniphier-wdt";
733 pvtctl: thermal-sensor {
734 compatible = "socionext,uniphier-ld20-thermal";
736 #thermal-sensor-cells = <0>;
737 socionext,tmod-calibration = <0x0f22 0x68ee>;
742 compatible = "socionext,uniphier-ld20-ave4";
746 pinctrl-names = "default";
747 pinctrl-0 = <&pinctrl_ether_rgmii>;
748 clock-names = "ether";
750 reset-names = "ether";
752 phy-mode = "rgmii-id";
753 local-mac-address = [00 00 00 00 00 00];
754 socionext,syscon-phy-mode = <&soc_glue 0>;
757 #address-cells = <1>;
758 #size-cells = <0>;
763 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
766 interrupt-names = "host";
768 pinctrl-names = "default";
769 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
771 clock-names = "ref", "bus_early", "suspend";
780 usb-controller@65b00000 {
781 compatible = "socionext,uniphier-ld20-dwc3-glue",
782 "simple-mfd";
784 #address-cells = <1>;
785 #size-cells = <1>;
788 usb_rst: reset-controller@0 {
789 compatible = "socionext,uniphier-ld20-usb3-reset";
791 #reset-cells = <1>;
792 clock-names = "link";
794 reset-names = "link";
799 compatible = "socionext,uniphier-ld20-usb3-regulator";
801 clock-names = "link";
803 reset-names = "link";
808 compatible = "socionext,uniphier-ld20-usb3-regulator";
810 clock-names = "link";
812 reset-names = "link";
817 compatible = "socionext,uniphier-ld20-usb3-regulator";
819 clock-names = "link";
821 reset-names = "link";
826 compatible = "socionext,uniphier-ld20-usb3-regulator";
828 clock-names = "link";
830 reset-names = "link";
835 compatible = "socionext,uniphier-ld20-usb3-hsphy";
837 #phy-cells = <0>;
838 clock-names = "link", "phy";
840 reset-names = "link", "phy";
842 vbus-supply = <&usb_vbus0>;
843 nvmem-cell-names = "rterm", "sel_t", "hs_i";
844 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
849 compatible = "socionext,uniphier-ld20-usb3-hsphy";
851 #phy-cells = <0>;
852 clock-names = "link", "phy";
854 reset-names = "link", "phy";
856 vbus-supply = <&usb_vbus1>;
857 nvmem-cell-names = "rterm", "sel_t", "hs_i";
858 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
863 compatible = "socionext,uniphier-ld20-usb3-hsphy";
865 #phy-cells = <0>;
866 clock-names = "link", "phy";
868 reset-names = "link", "phy";
870 vbus-supply = <&usb_vbus2>;
871 nvmem-cell-names = "rterm", "sel_t", "hs_i";
872 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
877 compatible = "socionext,uniphier-ld20-usb3-hsphy";
879 #phy-cells = <0>;
880 clock-names = "link", "phy";
882 reset-names = "link", "phy";
884 vbus-supply = <&usb_vbus3>;
885 nvmem-cell-names = "rterm", "sel_t", "hs_i";
886 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
891 compatible = "socionext,uniphier-ld20-usb3-ssphy";
893 #phy-cells = <0>;
894 clock-names = "link", "phy";
896 reset-names = "link", "phy";
898 vbus-supply = <&usb_vbus0>;
902 compatible = "socionext,uniphier-ld20-usb3-ssphy";
904 #phy-cells = <0>;
905 clock-names = "link", "phy";
907 reset-names = "link", "phy";
909 vbus-supply = <&usb_vbus1>;
914 compatible = "socionext,uniphier-pcie";
916 reg-names = "dbi", "link", "config";
919 #address-cells = <3>;
920 #size-cells = <2>;
923 num-lanes = <1>;
924 num-viewport = <1>;
925 bus-range = <0x0 0xff>;
930 /* non-prefetchable memory */
932 #interrupt-cells = <1>;
933 interrupt-names = "dma", "msi";
936 interrupt-map-mask = <0 0 0 7>;
937 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
941 phy-names = "pcie-phy";
944 pcie_intc: legacy-interrupt-controller {
945 interrupt-controller;
946 #interrupt-cells = <1>;
947 interrupt-parent = <&gic>;
953 compatible = "socionext,uniphier-ld20-pcie-phy";
955 #phy-cells = <0>;
956 clock-names = "link";
958 reset-names = "link";
963 nand: nand-controller@68000000 {
964 compatible = "socionext,uniphier-denali-nand-v5b";
966 reg-names = "nand_data", "denali_reg";
968 #address-cells = <1>;
969 #size-cells = <0>;
971 pinctrl-names = "default";
972 pinctrl-0 = <&pinctrl_nand>;
973 clock-names = "nand", "nand_x", "ecc";
975 reset-names = "nand", "reg";
981 #include "uniphier-pinctrl.dtsi"
984 drive-strength = <4>; /* default: 3.5mA */
988 drive-strength = <5>; /* 5mA */
993 drive-strength = <4>; /* default: 3.5mA */
997 drive-strength = <11>; /* 11mA */