Lines Matching +full:sdmmc +full:- +full:3 +full:v3
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
60 compatible = "arm,cortex-a55";
62 enable-method = "psci";
63 capacity-dmips-mhz = <530>;
65 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
66 assigned-clock-rates = <816000000>;
67 cpu-idle-states = <&CPU_SLEEP>;
68 i-cache-size = <32768>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <128>;
71 d-cache-size = <32768>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&l2_cache_l0>;
75 dynamic-power-coefficient = <228>;
76 #cooling-cells = <2>;
81 compatible = "arm,cortex-a55";
83 enable-method = "psci";
84 capacity-dmips-mhz = <530>;
86 cpu-idle-states = <&CPU_SLEEP>;
87 i-cache-size = <32768>;
88 i-cache-line-size = <64>;
89 i-cache-sets = <128>;
90 d-cache-size = <32768>;
91 d-cache-line-size = <64>;
92 d-cache-sets = <128>;
93 next-level-cache = <&l2_cache_l1>;
94 dynamic-power-coefficient = <228>;
95 #cooling-cells = <2>;
100 compatible = "arm,cortex-a55";
102 enable-method = "psci";
103 capacity-dmips-mhz = <530>;
105 cpu-idle-states = <&CPU_SLEEP>;
106 i-cache-size = <32768>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <128>;
109 d-cache-size = <32768>;
110 d-cache-line-size = <64>;
111 d-cache-sets = <128>;
112 next-level-cache = <&l2_cache_l2>;
113 dynamic-power-coefficient = <228>;
114 #cooling-cells = <2>;
119 compatible = "arm,cortex-a55";
121 enable-method = "psci";
122 capacity-dmips-mhz = <530>;
124 cpu-idle-states = <&CPU_SLEEP>;
125 i-cache-size = <32768>;
126 i-cache-line-size = <64>;
127 i-cache-sets = <128>;
128 d-cache-size = <32768>;
129 d-cache-line-size = <64>;
130 d-cache-sets = <128>;
131 next-level-cache = <&l2_cache_l3>;
132 dynamic-power-coefficient = <228>;
133 #cooling-cells = <2>;
138 compatible = "arm,cortex-a76";
140 enable-method = "psci";
141 capacity-dmips-mhz = <1024>;
143 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
144 assigned-clock-rates = <816000000>;
145 cpu-idle-states = <&CPU_SLEEP>;
146 i-cache-size = <65536>;
147 i-cache-line-size = <64>;
148 i-cache-sets = <256>;
149 d-cache-size = <65536>;
150 d-cache-line-size = <64>;
151 d-cache-sets = <256>;
152 next-level-cache = <&l2_cache_b0>;
153 dynamic-power-coefficient = <416>;
154 #cooling-cells = <2>;
159 compatible = "arm,cortex-a76";
161 enable-method = "psci";
162 capacity-dmips-mhz = <1024>;
164 cpu-idle-states = <&CPU_SLEEP>;
165 i-cache-size = <65536>;
166 i-cache-line-size = <64>;
167 i-cache-sets = <256>;
168 d-cache-size = <65536>;
169 d-cache-line-size = <64>;
170 d-cache-sets = <256>;
171 next-level-cache = <&l2_cache_b1>;
172 dynamic-power-coefficient = <416>;
173 #cooling-cells = <2>;
178 compatible = "arm,cortex-a76";
180 enable-method = "psci";
181 capacity-dmips-mhz = <1024>;
183 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
184 assigned-clock-rates = <816000000>;
185 cpu-idle-states = <&CPU_SLEEP>;
186 i-cache-size = <65536>;
187 i-cache-line-size = <64>;
188 i-cache-sets = <256>;
189 d-cache-size = <65536>;
190 d-cache-line-size = <64>;
191 d-cache-sets = <256>;
192 next-level-cache = <&l2_cache_b2>;
193 dynamic-power-coefficient = <416>;
194 #cooling-cells = <2>;
199 compatible = "arm,cortex-a76";
201 enable-method = "psci";
202 capacity-dmips-mhz = <1024>;
204 cpu-idle-states = <&CPU_SLEEP>;
205 i-cache-size = <65536>;
206 i-cache-line-size = <64>;
207 i-cache-sets = <256>;
208 d-cache-size = <65536>;
209 d-cache-line-size = <64>;
210 d-cache-sets = <256>;
211 next-level-cache = <&l2_cache_b3>;
212 dynamic-power-coefficient = <416>;
213 #cooling-cells = <2>;
216 idle-states {
217 entry-method = "psci";
218 CPU_SLEEP: cpu-sleep {
219 compatible = "arm,idle-state";
220 local-timer-stop;
221 arm,psci-suspend-param = <0x0010000>;
222 entry-latency-us = <100>;
223 exit-latency-us = <120>;
224 min-residency-us = <1000>;
228 l2_cache_l0: l2-cache-l0 {
230 cache-size = <131072>;
231 cache-line-size = <64>;
232 cache-sets = <512>;
233 cache-level = <2>;
234 cache-unified;
235 next-level-cache = <&l3_cache>;
238 l2_cache_l1: l2-cache-l1 {
240 cache-size = <131072>;
241 cache-line-size = <64>;
242 cache-sets = <512>;
243 cache-level = <2>;
244 cache-unified;
245 next-level-cache = <&l3_cache>;
248 l2_cache_l2: l2-cache-l2 {
250 cache-size = <131072>;
251 cache-line-size = <64>;
252 cache-sets = <512>;
253 cache-level = <2>;
254 cache-unified;
255 next-level-cache = <&l3_cache>;
258 l2_cache_l3: l2-cache-l3 {
260 cache-size = <131072>;
261 cache-line-size = <64>;
262 cache-sets = <512>;
263 cache-level = <2>;
264 cache-unified;
265 next-level-cache = <&l3_cache>;
268 l2_cache_b0: l2-cache-b0 {
270 cache-size = <524288>;
271 cache-line-size = <64>;
272 cache-sets = <1024>;
273 cache-level = <2>;
274 cache-unified;
275 next-level-cache = <&l3_cache>;
278 l2_cache_b1: l2-cache-b1 {
280 cache-size = <524288>;
281 cache-line-size = <64>;
282 cache-sets = <1024>;
283 cache-level = <2>;
284 cache-unified;
285 next-level-cache = <&l3_cache>;
288 l2_cache_b2: l2-cache-b2 {
290 cache-size = <524288>;
291 cache-line-size = <64>;
292 cache-sets = <1024>;
293 cache-level = <2>;
294 cache-unified;
295 next-level-cache = <&l3_cache>;
298 l2_cache_b3: l2-cache-b3 {
300 cache-size = <524288>;
301 cache-line-size = <64>;
302 cache-sets = <1024>;
303 cache-level = <2>;
304 cache-unified;
305 next-level-cache = <&l3_cache>;
308 l3_cache: l3-cache {
310 cache-size = <3145728>;
311 cache-line-size = <64>;
312 cache-sets = <4096>;
313 cache-level = <3>;
314 cache-unified;
320 compatible = "linaro,optee-tz";
325 compatible = "arm,scmi-smc";
326 arm,smc-id = <0x82000010>;
328 #address-cells = <1>;
329 #size-cells = <0>;
333 #clock-cells = <1>;
338 #reset-cells = <1>;
343 pmu-a55 {
344 compatible = "arm,cortex-a55-pmu";
348 pmu-a76 {
349 compatible = "arm,cortex-a76-pmu";
354 compatible = "arm,psci-1.0";
358 spll: clock-0 {
359 compatible = "fixed-clock";
360 clock-frequency = <702000000>;
361 clock-output-names = "spll";
362 #clock-cells = <0>;
366 compatible = "arm,armv8-timer";
372 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
375 xin24m: clock-1 {
376 compatible = "fixed-clock";
377 clock-frequency = <24000000>;
378 clock-output-names = "xin24m";
379 #clock-cells = <0>;
382 xin32k: clock-2 {
383 compatible = "fixed-clock";
384 clock-frequency = <32768>;
385 clock-output-names = "xin32k";
386 #clock-cells = <0>;
390 compatible = "mmio-sram";
393 #address-cells = <1>;
394 #size-cells = <1>;
397 compatible = "arm,scmi-shmem";
403 compatible = "rockchip,rk3588-ehci", "generic-ehci";
408 phy-names = "usb";
409 power-domains = <&power RK3588_PD_USB>;
414 compatible = "rockchip,rk3588-ohci", "generic-ohci";
419 phy-names = "usb";
420 power-domains = <&power RK3588_PD_USB>;
425 compatible = "rockchip,rk3588-ehci", "generic-ehci";
430 phy-names = "usb";
431 power-domains = <&power RK3588_PD_USB>;
436 compatible = "rockchip,rk3588-ohci", "generic-ohci";
441 phy-names = "usb";
442 power-domains = <&power RK3588_PD_USB>;
447 compatible = "rockchip,rk3588-sys-grf", "syscon";
452 compatible = "rockchip,rk3588-php-grf", "syscon";
457 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
462 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
467 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
469 #address-cells = <1>;
470 #size-cells = <1>;
472 u2phy2: usb2-phy@8000 {
473 compatible = "rockchip,rk3588-usb2phy";
477 reset-names = "phy", "apb";
479 clock-names = "phyclk";
480 clock-output-names = "usb480m_phy2";
481 #clock-cells = <0>;
484 u2phy2_host: host-port {
485 #phy-cells = <0>;
492 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
494 #address-cells = <1>;
495 #size-cells = <1>;
497 u2phy3: usb2-phy@c000 {
498 compatible = "rockchip,rk3588-usb2phy";
502 reset-names = "phy", "apb";
504 clock-names = "phyclk";
505 clock-output-names = "usb480m_phy3";
506 #clock-cells = <0>;
509 u2phy3_host: host-port {
510 #phy-cells = <0>;
517 compatible = "rockchip,rk3588-ioc", "syscon";
522 compatible = "mmio-sram";
525 #address-cells = <1>;
526 #size-cells = <1>;
529 cru: clock-controller@fd7c0000 {
530 compatible = "rockchip,rk3588-cru";
532 assigned-clocks =
542 assigned-clock-rates =
553 #clock-cells = <1>;
554 #reset-cells = <1>;
558 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
562 clock-names = "i2c", "pclk";
563 pinctrl-0 = <&i2c0m0_xfer>;
564 pinctrl-names = "default";
565 #address-cells = <1>;
566 #size-cells = <0>;
571 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
575 clock-names = "baudclk", "apb_pclk";
577 dma-names = "tx", "rx";
578 pinctrl-0 = <&uart0m1_xfer>;
579 pinctrl-names = "default";
580 reg-shift = <2>;
581 reg-io-width = <4>;
586 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
589 clock-names = "pwm", "pclk";
590 pinctrl-0 = <&pwm0m0_pins>;
591 pinctrl-names = "default";
592 #pwm-cells = <3>;
597 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
600 clock-names = "pwm", "pclk";
601 pinctrl-0 = <&pwm1m0_pins>;
602 pinctrl-names = "default";
603 #pwm-cells = <3>;
608 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
611 clock-names = "pwm", "pclk";
612 pinctrl-0 = <&pwm2m0_pins>;
613 pinctrl-names = "default";
614 #pwm-cells = <3>;
619 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
622 clock-names = "pwm", "pclk";
623 pinctrl-0 = <&pwm3m0_pins>;
624 pinctrl-names = "default";
625 #pwm-cells = <3>;
629 pmu: power-management@fd8d8000 {
630 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
633 power: power-controller {
634 compatible = "rockchip,rk3588-power-controller";
635 #address-cells = <1>;
636 #power-domain-cells = <1>;
637 #size-cells = <0>;
641 power-domain@RK3588_PD_NPU {
643 #power-domain-cells = <0>;
644 #address-cells = <1>;
645 #size-cells = <0>;
647 power-domain@RK3588_PD_NPUTOP {
656 #power-domain-cells = <0>;
657 #address-cells = <1>;
658 #size-cells = <0>;
660 power-domain@RK3588_PD_NPU1 {
666 #power-domain-cells = <0>;
668 power-domain@RK3588_PD_NPU2 {
674 #power-domain-cells = <0>;
679 power-domain@RK3588_PD_GPU {
688 #power-domain-cells = <0>;
691 power-domain@RK3588_PD_VCODEC {
693 #address-cells = <1>;
694 #size-cells = <0>;
695 #power-domain-cells = <0>;
697 power-domain@RK3588_PD_RKVDEC0 {
705 #power-domain-cells = <0>;
707 power-domain@RK3588_PD_RKVDEC1 {
714 #power-domain-cells = <0>;
716 power-domain@RK3588_PD_VENC0 {
723 #address-cells = <1>;
724 #size-cells = <0>;
725 #power-domain-cells = <0>;
727 power-domain@RK3588_PD_VENC1 {
736 #power-domain-cells = <0>;
741 power-domain@RK3588_PD_VDPU {
769 #address-cells = <1>;
770 #size-cells = <0>;
771 #power-domain-cells = <0>;
774 power-domain@RK3588_PD_AV1 {
780 #power-domain-cells = <0>;
782 power-domain@RK3588_PD_RKVDEC0 {
789 #power-domain-cells = <0>;
791 power-domain@RK3588_PD_RKVDEC1 {
797 #power-domain-cells = <0>;
799 power-domain@RK3588_PD_RGA30 {
804 #power-domain-cells = <0>;
807 power-domain@RK3588_PD_VOP {
814 #address-cells = <1>;
815 #size-cells = <0>;
816 #power-domain-cells = <0>;
818 power-domain@RK3588_PD_VO0 {
828 #power-domain-cells = <0>;
831 power-domain@RK3588_PD_VO1 {
842 #power-domain-cells = <0>;
844 power-domain@RK3588_PD_VI {
856 #address-cells = <1>;
857 #size-cells = <0>;
858 #power-domain-cells = <0>;
860 power-domain@RK3588_PD_ISP1 {
868 #power-domain-cells = <0>;
870 power-domain@RK3588_PD_FEC {
879 #power-domain-cells = <0>;
882 power-domain@RK3588_PD_RGA31 {
887 #power-domain-cells = <0>;
889 power-domain@RK3588_PD_USB {
903 #power-domain-cells = <0>;
905 power-domain@RK3588_PD_GMAC {
910 #power-domain-cells = <0>;
912 power-domain@RK3588_PD_PCIE {
917 #power-domain-cells = <0>;
919 power-domain@RK3588_PD_SDIO {
924 #power-domain-cells = <0>;
926 power-domain@RK3588_PD_AUDIO {
930 #power-domain-cells = <0>;
932 power-domain@RK3588_PD_SDMMC {
935 #power-domain-cells = <0>;
941 compatible = "rockchip,rk3588-i2s-tdm";
945 clock-names = "mclk_tx", "mclk_rx", "hclk";
946 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
947 assigned-clock-parents = <&cru PLL_AUPLL>;
949 dma-names = "tx";
950 power-domains = <&power RK3588_PD_VO0>;
952 reset-names = "tx-m";
953 #sound-dai-cells = <0>;
958 compatible = "rockchip,rk3588-i2s-tdm";
962 clock-names = "mclk_tx", "mclk_rx", "hclk";
963 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
964 assigned-clock-parents = <&cru PLL_AUPLL>;
966 dma-names = "tx";
967 power-domains = <&power RK3588_PD_VO1>;
969 reset-names = "tx-m";
970 #sound-dai-cells = <0>;
975 compatible = "rockchip,rk3588-i2s-tdm";
979 clock-names = "mclk_tx", "mclk_rx", "hclk";
980 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
981 assigned-clock-parents = <&cru PLL_AUPLL>;
983 dma-names = "rx";
984 power-domains = <&power RK3588_PD_VO1>;
986 reset-names = "rx-m";
987 #sound-dai-cells = <0>;
992 compatible = "rockchip,rk3588-qos", "syscon";
997 compatible = "rockchip,rk3588-qos", "syscon";
1002 compatible = "rockchip,rk3588-qos", "syscon";
1007 compatible = "rockchip,rk3588-qos", "syscon";
1012 compatible = "rockchip,rk3588-qos", "syscon";
1017 compatible = "rockchip,rk3588-qos", "syscon";
1022 compatible = "rockchip,rk3588-qos", "syscon";
1027 compatible = "rockchip,rk3588-qos", "syscon";
1032 compatible = "rockchip,rk3588-qos", "syscon";
1037 compatible = "rockchip,rk3588-qos", "syscon";
1042 compatible = "rockchip,rk3588-qos", "syscon";
1047 compatible = "rockchip,rk3588-qos", "syscon";
1052 compatible = "rockchip,rk3588-qos", "syscon";
1057 compatible = "rockchip,rk3588-qos", "syscon";
1062 compatible = "rockchip,rk3588-qos", "syscon";
1067 compatible = "rockchip,rk3588-qos", "syscon";
1072 compatible = "rockchip,rk3588-qos", "syscon";
1077 compatible = "rockchip,rk3588-qos", "syscon";
1082 compatible = "rockchip,rk3588-qos", "syscon";
1087 compatible = "rockchip,rk3588-qos", "syscon";
1092 compatible = "rockchip,rk3588-qos", "syscon";
1097 compatible = "rockchip,rk3588-qos", "syscon";
1102 compatible = "rockchip,rk3588-qos", "syscon";
1107 compatible = "rockchip,rk3588-qos", "syscon";
1112 compatible = "rockchip,rk3588-qos", "syscon";
1117 compatible = "rockchip,rk3588-qos", "syscon";
1122 compatible = "rockchip,rk3588-qos", "syscon";
1127 compatible = "rockchip,rk3588-qos", "syscon";
1132 compatible = "rockchip,rk3588-qos", "syscon";
1137 compatible = "rockchip,rk3588-qos", "syscon";
1142 compatible = "rockchip,rk3588-qos", "syscon";
1147 compatible = "rockchip,rk3588-qos", "syscon";
1152 compatible = "rockchip,rk3588-qos", "syscon";
1157 compatible = "rockchip,rk3588-qos", "syscon";
1162 compatible = "rockchip,rk3588-qos", "syscon";
1167 compatible = "rockchip,rk3588-qos", "syscon";
1172 compatible = "rockchip,rk3588-qos", "syscon";
1177 compatible = "rockchip,rk3588-qos", "syscon";
1182 compatible = "rockchip,rk3588-qos", "syscon";
1187 compatible = "rockchip,rk3588-qos", "syscon";
1192 compatible = "rockchip,rk3588-qos", "syscon";
1197 compatible = "rockchip,rk3588-qos", "syscon";
1202 compatible = "rockchip,rk3588-qos", "syscon";
1207 compatible = "rockchip,rk3588-qos", "syscon";
1212 compatible = "rockchip,rk3588-qos", "syscon";
1217 compatible = "rockchip,rk3588-qos", "syscon";
1222 compatible = "rockchip,rk3588-qos", "syscon";
1227 compatible = "rockchip,rk3588-qos", "syscon";
1232 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1233 bus-range = <0x30 0x3f>;
1237 clock-names = "aclk_mst", "aclk_slv",
1246 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1247 #interrupt-cells = <1>;
1248 interrupt-map-mask = <0 0 0 7>;
1249 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1251 <0 0 0 3 &pcie2x1l1_intc 2>,
1252 <0 0 0 4 &pcie2x1l1_intc 3>;
1253 linux,pci-domain = <3>;
1254 max-link-speed = <2>;
1255 msi-map = <0x3000 &its0 0x3000 0x1000>;
1256 num-lanes = <1>;
1258 phy-names = "pcie-phy";
1259 power-domains = <&power RK3588_PD_PCIE>;
1266 reg-names = "dbi", "apb", "config";
1268 reset-names = "pwr", "pipe";
1269 #address-cells = <3>;
1270 #size-cells = <2>;
1273 pcie2x1l1_intc: legacy-interrupt-controller {
1274 interrupt-controller;
1275 #address-cells = <0>;
1276 #interrupt-cells = <1>;
1277 interrupt-parent = <&gic>;
1283 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1284 bus-range = <0x40 0x4f>;
1288 clock-names = "aclk_mst", "aclk_slv",
1297 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1298 #interrupt-cells = <1>;
1299 interrupt-map-mask = <0 0 0 7>;
1300 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1302 <0 0 0 3 &pcie2x1l2_intc 2>,
1303 <0 0 0 4 &pcie2x1l2_intc 3>;
1304 linux,pci-domain = <4>;
1305 max-link-speed = <2>;
1306 msi-map = <0x4000 &its0 0x4000 0x1000>;
1307 num-lanes = <1>;
1309 phy-names = "pcie-phy";
1310 power-domains = <&power RK3588_PD_PCIE>;
1317 reg-names = "dbi", "apb", "config";
1319 reset-names = "pwr", "pipe";
1320 #address-cells = <3>;
1321 #size-cells = <2>;
1324 pcie2x1l2_intc: legacy-interrupt-controller {
1325 interrupt-controller;
1326 #address-cells = <0>;
1327 #interrupt-cells = <1>;
1328 interrupt-parent = <&gic>;
1334 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1338 interrupt-names = "macirq", "eth_wake_irq";
1342 clock-names = "stmmaceth", "clk_mac_ref",
1345 power-domains = <&power RK3588_PD_GMAC>;
1347 reset-names = "stmmaceth";
1349 rockchip,php-grf = <&php_grf>;
1350 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1351 snps,mixed-burst;
1352 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1353 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1358 compatible = "snps,dwmac-mdio";
1359 #address-cells = <0x1>;
1360 #size-cells = <0x0>;
1363 gmac1_stmmac_axi_setup: stmmac-axi-config {
1369 gmac1_mtl_rx_setup: rx-queues-config {
1370 snps,rx-queues-to-use = <2>;
1375 gmac1_mtl_tx_setup: tx-queues-config {
1376 snps,tx-queues-to-use = <2>;
1383 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1389 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1390 ports-implemented = <0x1>;
1391 #address-cells = <1>;
1392 #size-cells = <0>;
1395 sata-port@0 {
1397 hba-port-cap = <HBA_PORT_FBSCP>;
1399 phy-names = "sata-phy";
1400 snps,rx-ts-max = <32>;
1401 snps,tx-ts-max = <32>;
1406 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1412 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1413 ports-implemented = <0x1>;
1414 #address-cells = <1>;
1415 #size-cells = <0>;
1418 sata-port@0 {
1420 hba-port-cap = <HBA_PORT_FBSCP>;
1422 phy-names = "sata-phy";
1423 snps,rx-ts-max = <32>;
1424 snps,tx-ts-max = <32>;
1428 sdmmc: mmc@fe2c0000 { label
1429 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1434 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1435 fifo-depth = <0x100>;
1436 max-frequency = <200000000>;
1437 pinctrl-names = "default";
1438 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1439 power-domains = <&power RK3588_PD_SDMMC>;
1444 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1449 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1450 fifo-depth = <0x100>;
1451 max-frequency = <200000000>;
1452 pinctrl-names = "default";
1453 pinctrl-0 = <&sdiom1_pins>;
1454 power-domains = <&power RK3588_PD_SDIO>;
1459 compatible = "rockchip,rk3588-dwcmshc";
1462 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1463 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1467 clock-names = "core", "bus", "axi", "block", "timer";
1468 max-frequency = <200000000>;
1469 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1471 pinctrl-names = "default";
1475 reset-names = "core", "bus", "axi", "block", "timer";
1480 compatible = "rockchip,rk3588-i2s-tdm";
1484 clock-names = "mclk_tx", "mclk_rx", "hclk";
1485 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1486 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1488 dma-names = "tx", "rx";
1489 power-domains = <&power RK3588_PD_AUDIO>;
1491 reset-names = "tx-m", "rx-m";
1492 rockchip,trcm-sync-tx-only;
1493 pinctrl-names = "default";
1494 pinctrl-0 = <&i2s0_lrck
1504 #sound-dai-cells = <0>;
1509 compatible = "rockchip,rk3588-i2s-tdm";
1513 clock-names = "mclk_tx", "mclk_rx", "hclk";
1514 dmas = <&dmac0 2>, <&dmac0 3>;
1515 dma-names = "tx", "rx";
1517 reset-names = "tx-m", "rx-m";
1518 rockchip,trcm-sync-tx-only;
1519 pinctrl-names = "default";
1520 pinctrl-0 = <&i2s1m0_lrck
1530 #sound-dai-cells = <0>;
1535 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1539 clock-names = "i2s_clk", "i2s_hclk";
1540 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1541 assigned-clock-parents = <&cru PLL_AUPLL>;
1543 dma-names = "tx", "rx";
1544 power-domains = <&power RK3588_PD_AUDIO>;
1545 pinctrl-names = "default";
1546 pinctrl-0 = <&i2s2m1_lrck
1550 #sound-dai-cells = <0>;
1555 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1559 clock-names = "i2s_clk", "i2s_hclk";
1560 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
1561 assigned-clock-parents = <&cru PLL_AUPLL>;
1562 dmas = <&dmac1 2>, <&dmac1 3>;
1563 dma-names = "tx", "rx";
1564 power-domains = <&power RK3588_PD_AUDIO>;
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&i2s3_lrck
1570 #sound-dai-cells = <0>;
1574 gic: interrupt-controller@fe600000 {
1575 compatible = "arm,gic-v3";
1579 interrupt-controller;
1580 mbi-alias = <0x0 0xfe610000>;
1581 mbi-ranges = <424 56>;
1582 msi-controller;
1584 #address-cells = <2>;
1585 #interrupt-cells = <4>;
1586 #size-cells = <2>;
1588 its0: msi-controller@fe640000 {
1589 compatible = "arm,gic-v3-its";
1591 msi-controller;
1592 #msi-cells = <1>;
1595 its1: msi-controller@fe660000 {
1596 compatible = "arm,gic-v3-its";
1598 msi-controller;
1599 #msi-cells = <1>;
1602 ppi-partitions {
1603 ppi_partition0: interrupt-partition-0 {
1607 ppi_partition1: interrupt-partition-1 {
1613 dmac0: dma-controller@fea10000 {
1618 arm,pl330-periph-burst;
1620 clock-names = "apb_pclk";
1621 #dma-cells = <1>;
1624 dmac1: dma-controller@fea30000 {
1629 arm,pl330-periph-burst;
1631 clock-names = "apb_pclk";
1632 #dma-cells = <1>;
1636 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1639 clock-names = "i2c", "pclk";
1641 pinctrl-0 = <&i2c1m0_xfer>;
1642 pinctrl-names = "default";
1643 #address-cells = <1>;
1644 #size-cells = <0>;
1649 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1652 clock-names = "i2c", "pclk";
1654 pinctrl-0 = <&i2c2m0_xfer>;
1655 pinctrl-names = "default";
1656 #address-cells = <1>;
1657 #size-cells = <0>;
1662 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1665 clock-names = "i2c", "pclk";
1667 pinctrl-0 = <&i2c3m0_xfer>;
1668 pinctrl-names = "default";
1669 #address-cells = <1>;
1670 #size-cells = <0>;
1675 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1678 clock-names = "i2c", "pclk";
1680 pinctrl-0 = <&i2c4m0_xfer>;
1681 pinctrl-names = "default";
1682 #address-cells = <1>;
1683 #size-cells = <0>;
1688 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1691 clock-names = "i2c", "pclk";
1693 pinctrl-0 = <&i2c5m0_xfer>;
1694 pinctrl-names = "default";
1695 #address-cells = <1>;
1696 #size-cells = <0>;
1701 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
1705 clock-names = "pclk", "timer";
1709 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
1712 clock-names = "tclk", "pclk";
1717 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1721 clock-names = "spiclk", "apb_pclk";
1723 dma-names = "tx", "rx";
1724 num-cs = <2>;
1725 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1726 pinctrl-names = "default";
1727 #address-cells = <1>;
1728 #size-cells = <0>;
1733 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1737 clock-names = "spiclk", "apb_pclk";
1739 dma-names = "tx", "rx";
1740 num-cs = <2>;
1741 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1742 pinctrl-names = "default";
1743 #address-cells = <1>;
1744 #size-cells = <0>;
1749 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1753 clock-names = "spiclk", "apb_pclk";
1755 dma-names = "tx", "rx";
1756 num-cs = <2>;
1757 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
1758 pinctrl-names = "default";
1759 #address-cells = <1>;
1760 #size-cells = <0>;
1765 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1769 clock-names = "spiclk", "apb_pclk";
1771 dma-names = "tx", "rx";
1772 num-cs = <2>;
1773 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1774 pinctrl-names = "default";
1775 #address-cells = <1>;
1776 #size-cells = <0>;
1781 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1785 clock-names = "baudclk", "apb_pclk";
1787 dma-names = "tx", "rx";
1788 pinctrl-0 = <&uart1m1_xfer>;
1789 pinctrl-names = "default";
1790 reg-io-width = <4>;
1791 reg-shift = <2>;
1796 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1800 clock-names = "baudclk", "apb_pclk";
1802 dma-names = "tx", "rx";
1803 pinctrl-0 = <&uart2m1_xfer>;
1804 pinctrl-names = "default";
1805 reg-io-width = <4>;
1806 reg-shift = <2>;
1811 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1815 clock-names = "baudclk", "apb_pclk";
1817 dma-names = "tx", "rx";
1818 pinctrl-0 = <&uart3m1_xfer>;
1819 pinctrl-names = "default";
1820 reg-io-width = <4>;
1821 reg-shift = <2>;
1826 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1830 clock-names = "baudclk", "apb_pclk";
1832 dma-names = "tx", "rx";
1833 pinctrl-0 = <&uart4m1_xfer>;
1834 pinctrl-names = "default";
1835 reg-io-width = <4>;
1836 reg-shift = <2>;
1841 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1845 clock-names = "baudclk", "apb_pclk";
1847 dma-names = "tx", "rx";
1848 pinctrl-0 = <&uart5m1_xfer>;
1849 pinctrl-names = "default";
1850 reg-io-width = <4>;
1851 reg-shift = <2>;
1856 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1860 clock-names = "baudclk", "apb_pclk";
1862 dma-names = "tx", "rx";
1863 pinctrl-0 = <&uart6m1_xfer>;
1864 pinctrl-names = "default";
1865 reg-io-width = <4>;
1866 reg-shift = <2>;
1871 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1875 clock-names = "baudclk", "apb_pclk";
1877 dma-names = "tx", "rx";
1878 pinctrl-0 = <&uart7m1_xfer>;
1879 pinctrl-names = "default";
1880 reg-io-width = <4>;
1881 reg-shift = <2>;
1886 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1890 clock-names = "baudclk", "apb_pclk";
1892 dma-names = "tx", "rx";
1893 pinctrl-0 = <&uart8m1_xfer>;
1894 pinctrl-names = "default";
1895 reg-io-width = <4>;
1896 reg-shift = <2>;
1901 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1905 clock-names = "baudclk", "apb_pclk";
1907 dma-names = "tx", "rx";
1908 pinctrl-0 = <&uart9m1_xfer>;
1909 pinctrl-names = "default";
1910 reg-io-width = <4>;
1911 reg-shift = <2>;
1916 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1919 clock-names = "pwm", "pclk";
1920 pinctrl-0 = <&pwm4m0_pins>;
1921 pinctrl-names = "default";
1922 #pwm-cells = <3>;
1927 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1930 clock-names = "pwm", "pclk";
1931 pinctrl-0 = <&pwm5m0_pins>;
1932 pinctrl-names = "default";
1933 #pwm-cells = <3>;
1938 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1941 clock-names = "pwm", "pclk";
1942 pinctrl-0 = <&pwm6m0_pins>;
1943 pinctrl-names = "default";
1944 #pwm-cells = <3>;
1949 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1952 clock-names = "pwm", "pclk";
1953 pinctrl-0 = <&pwm7m0_pins>;
1954 pinctrl-names = "default";
1955 #pwm-cells = <3>;
1960 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1963 clock-names = "pwm", "pclk";
1964 pinctrl-0 = <&pwm8m0_pins>;
1965 pinctrl-names = "default";
1966 #pwm-cells = <3>;
1971 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1974 clock-names = "pwm", "pclk";
1975 pinctrl-0 = <&pwm9m0_pins>;
1976 pinctrl-names = "default";
1977 #pwm-cells = <3>;
1982 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1985 clock-names = "pwm", "pclk";
1986 pinctrl-0 = <&pwm10m0_pins>;
1987 pinctrl-names = "default";
1988 #pwm-cells = <3>;
1993 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1996 clock-names = "pwm", "pclk";
1997 pinctrl-0 = <&pwm11m0_pins>;
1998 pinctrl-names = "default";
1999 #pwm-cells = <3>;
2004 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2007 clock-names = "pwm", "pclk";
2008 pinctrl-0 = <&pwm12m0_pins>;
2009 pinctrl-names = "default";
2010 #pwm-cells = <3>;
2015 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2018 clock-names = "pwm", "pclk";
2019 pinctrl-0 = <&pwm13m0_pins>;
2020 pinctrl-names = "default";
2021 #pwm-cells = <3>;
2026 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2029 clock-names = "pwm", "pclk";
2030 pinctrl-0 = <&pwm14m0_pins>;
2031 pinctrl-names = "default";
2032 #pwm-cells = <3>;
2037 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2040 clock-names = "pwm", "pclk";
2041 pinctrl-0 = <&pwm15m0_pins>;
2042 pinctrl-names = "default";
2043 #pwm-cells = <3>;
2048 compatible = "rockchip,rk3588-tsadc";
2052 clock-names = "tsadc", "apb_pclk";
2053 assigned-clocks = <&cru CLK_TSADC>;
2054 assigned-clock-rates = <2000000>;
2056 reset-names = "tsadc-apb", "tsadc";
2057 rockchip,hw-tshut-temp = <120000>;
2058 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2059 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2060 pinctrl-0 = <&tsadc_gpio_func>;
2061 pinctrl-1 = <&tsadc_shut>;
2062 pinctrl-names = "gpio", "otpout";
2063 #thermal-sensor-cells = <1>;
2068 compatible = "rockchip,rk3588-saradc";
2071 #io-channel-cells = <1>;
2073 clock-names = "saradc", "apb_pclk";
2075 reset-names = "saradc-apb";
2080 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2083 clock-names = "i2c", "pclk";
2085 pinctrl-0 = <&i2c6m0_xfer>;
2086 pinctrl-names = "default";
2087 #address-cells = <1>;
2088 #size-cells = <0>;
2093 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2096 clock-names = "i2c", "pclk";
2098 pinctrl-0 = <&i2c7m0_xfer>;
2099 pinctrl-names = "default";
2100 #address-cells = <1>;
2101 #size-cells = <0>;
2106 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2109 clock-names = "i2c", "pclk";
2111 pinctrl-0 = <&i2c8m0_xfer>;
2112 pinctrl-names = "default";
2113 #address-cells = <1>;
2114 #size-cells = <0>;
2119 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2123 clock-names = "spiclk", "apb_pclk";
2125 dma-names = "tx", "rx";
2126 num-cs = <2>;
2127 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2128 pinctrl-names = "default";
2129 #address-cells = <1>;
2130 #size-cells = <0>;
2135 compatible = "rockchip,rk3588-otp";
2139 clock-names = "otp", "apb_pclk", "phy", "arb";
2142 reset-names = "otp", "apb", "arb";
2143 #address-cells = <1>;
2144 #size-cells = <1>;
2146 cpu_code: cpu-code@2 {
2154 cpub0_leakage: cpu-leakage@17 {
2158 cpub1_leakage: cpu-leakage@18 {
2162 cpul_leakage: cpu-leakage@19 {
2166 log_leakage: log-leakage@1a {
2170 gpu_leakage: gpu-leakage@1b {
2174 otp_cpu_version: cpu-version@1c {
2176 bits = <3 3>;
2179 npu_leakage: npu-leakage@28 {
2183 codec_leakage: codec-leakage@29 {
2188 dmac2: dma-controller@fed10000 {
2193 arm,pl330-periph-burst;
2195 clock-names = "apb_pclk";
2196 #dma-cells = <1>;
2200 compatible = "rockchip,rk3588-naneng-combphy";
2204 clock-names = "ref", "apb", "pipe";
2205 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2206 assigned-clock-rates = <100000000>;
2207 #phy-cells = <1>;
2209 reset-names = "phy", "apb";
2210 rockchip,pipe-grf = <&php_grf>;
2211 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2216 compatible = "rockchip,rk3588-naneng-combphy";
2220 clock-names = "ref", "apb", "pipe";
2221 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2222 assigned-clock-rates = <100000000>;
2223 #phy-cells = <1>;
2225 reset-names = "phy", "apb";
2226 rockchip,pipe-grf = <&php_grf>;
2227 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2232 compatible = "mmio-sram";
2235 #address-cells = <1>;
2236 #size-cells = <1>;
2240 compatible = "rockchip,rk3588-pinctrl";
2243 #address-cells = <2>;
2244 #size-cells = <2>;
2247 compatible = "rockchip,gpio-bank";
2251 gpio-controller;
2252 gpio-ranges = <&pinctrl 0 0 32>;
2253 interrupt-controller;
2254 #gpio-cells = <2>;
2255 #interrupt-cells = <2>;
2259 compatible = "rockchip,gpio-bank";
2263 gpio-controller;
2264 gpio-ranges = <&pinctrl 0 32 32>;
2265 interrupt-controller;
2266 #gpio-cells = <2>;
2267 #interrupt-cells = <2>;
2271 compatible = "rockchip,gpio-bank";
2275 gpio-controller;
2276 gpio-ranges = <&pinctrl 0 64 32>;
2277 interrupt-controller;
2278 #gpio-cells = <2>;
2279 #interrupt-cells = <2>;
2283 compatible = "rockchip,gpio-bank";
2287 gpio-controller;
2288 gpio-ranges = <&pinctrl 0 96 32>;
2289 interrupt-controller;
2290 #gpio-cells = <2>;
2291 #interrupt-cells = <2>;
2295 compatible = "rockchip,gpio-bank";
2299 gpio-controller;
2300 gpio-ranges = <&pinctrl 0 128 32>;
2301 interrupt-controller;
2302 #gpio-cells = <2>;
2303 #interrupt-cells = <2>;
2308 #include "rk3588s-pinctrl.dtsi"