Lines Matching +full:rk3288 +full:- +full:mipi +full:- +full:dsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a55";
57 #cooling-cells = <2>;
58 enable-method = "psci";
59 operating-points-v2 = <&cpu0_opp_table>;
64 compatible = "arm,cortex-a55";
66 #cooling-cells = <2>;
67 enable-method = "psci";
68 operating-points-v2 = <&cpu0_opp_table>;
73 compatible = "arm,cortex-a55";
75 #cooling-cells = <2>;
76 enable-method = "psci";
77 operating-points-v2 = <&cpu0_opp_table>;
82 compatible = "arm,cortex-a55";
84 #cooling-cells = <2>;
85 enable-method = "psci";
86 operating-points-v2 = <&cpu0_opp_table>;
90 cpu0_opp_table: opp-table-0 {
91 compatible = "operating-points-v2";
92 opp-shared;
94 opp-408000000 {
95 opp-hz = /bits/ 64 <408000000>;
96 opp-microvolt = <900000 900000 1150000>;
97 clock-latency-ns = <40000>;
100 opp-600000000 {
101 opp-hz = /bits/ 64 <600000000>;
102 opp-microvolt = <900000 900000 1150000>;
105 opp-816000000 {
106 opp-hz = /bits/ 64 <816000000>;
107 opp-microvolt = <900000 900000 1150000>;
108 opp-suspend;
111 opp-1104000000 {
112 opp-hz = /bits/ 64 <1104000000>;
113 opp-microvolt = <900000 900000 1150000>;
116 opp-1416000000 {
117 opp-hz = /bits/ 64 <1416000000>;
118 opp-microvolt = <900000 900000 1150000>;
121 opp-1608000000 {
122 opp-hz = /bits/ 64 <1608000000>;
123 opp-microvolt = <975000 975000 1150000>;
126 opp-1800000000 {
127 opp-hz = /bits/ 64 <1800000000>;
128 opp-microvolt = <1050000 1050000 1150000>;
132 display_subsystem: display-subsystem {
133 compatible = "rockchip,display-subsystem";
139 compatible = "arm,scmi-smc";
140 arm,smc-id = <0x82000010>;
142 #address-cells = <1>;
143 #size-cells = <0>;
147 #clock-cells = <1>;
152 gpu_opp_table: opp-table-1 {
153 compatible = "operating-points-v2";
155 opp-200000000 {
156 opp-hz = /bits/ 64 <200000000>;
157 opp-microvolt = <825000>;
160 opp-300000000 {
161 opp-hz = /bits/ 64 <300000000>;
162 opp-microvolt = <825000>;
165 opp-400000000 {
166 opp-hz = /bits/ 64 <400000000>;
167 opp-microvolt = <825000>;
170 opp-600000000 {
171 opp-hz = /bits/ 64 <600000000>;
172 opp-microvolt = <825000>;
175 opp-700000000 {
176 opp-hz = /bits/ 64 <700000000>;
177 opp-microvolt = <900000>;
180 opp-800000000 {
181 opp-hz = /bits/ 64 <800000000>;
182 opp-microvolt = <1000000>;
186 hdmi_sound: hdmi-sound {
187 compatible = "simple-audio-card";
188 simple-audio-card,name = "HDMI";
189 simple-audio-card,format = "i2s";
190 simple-audio-card,mclk-fs = <256>;
193 simple-audio-card,codec {
194 sound-dai = <&hdmi>;
197 simple-audio-card,cpu {
198 sound-dai = <&i2s0_8ch>;
203 compatible = "arm,cortex-a55-pmu";
208 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
212 compatible = "arm,psci-1.0";
217 compatible = "arm,armv8-timer";
222 arm,no-tick-in-suspend;
226 compatible = "fixed-clock";
227 clock-frequency = <24000000>;
228 clock-output-names = "xin24m";
229 #clock-cells = <0>;
233 compatible = "fixed-clock";
234 clock-frequency = <32768>;
235 clock-output-names = "xin32k";
236 pinctrl-0 = <&clk32k_out0>;
237 pinctrl-names = "default";
238 #clock-cells = <0>;
242 compatible = "mmio-sram";
244 #address-cells = <1>;
245 #size-cells = <1>;
249 compatible = "arm,scmi-shmem";
255 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
259 clock-names = "sata", "pmalive", "rxoob";
262 phy-names = "sata-phy";
263 ports-implemented = <0x1>;
264 power-domains = <&power RK3568_PD_PIPE>;
269 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
273 clock-names = "sata", "pmalive", "rxoob";
276 phy-names = "sata-phy";
277 ports-implemented = <0x1>;
278 power-domains = <&power RK3568_PD_PIPE>;
283 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
288 clock-names = "ref_clk", "suspend_clk",
292 power-domains = <&power RK3568_PD_PIPE>;
299 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
304 clock-names = "ref_clk", "suspend_clk",
308 phy-names = "usb2-phy", "usb3-phy";
310 power-domains = <&power RK3568_PD_PIPE>;
316 gic: interrupt-controller@fd400000 {
317 compatible = "arm,gic-v3";
321 interrupt-controller;
322 #interrupt-cells = <3>;
323 mbi-alias = <0x0 0xfd410000>;
324 mbi-ranges = <296 24>;
325 msi-controller;
329 compatible = "generic-ehci";
335 phy-names = "usb";
340 compatible = "generic-ohci";
346 phy-names = "usb";
351 compatible = "generic-ehci";
357 phy-names = "usb";
362 compatible = "generic-ohci";
368 phy-names = "usb";
373 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
376 pmu_io_domains: io-domains {
377 compatible = "rockchip,rk3568-pmu-io-voltage-domain";
387 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
392 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
397 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
402 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
407 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
411 pmucru: clock-controller@fdd00000 {
412 compatible = "rockchip,rk3568-pmucru";
414 #clock-cells = <1>;
415 #reset-cells = <1>;
418 cru: clock-controller@fdd20000 {
419 compatible = "rockchip,rk3568-cru";
422 clock-names = "xin24m";
423 #clock-cells = <1>;
424 #reset-cells = <1>;
425 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
426 assigned-clock-rates = <32768>, <1200000000>, <200000000>;
427 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
432 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
436 clock-names = "i2c", "pclk";
437 pinctrl-0 = <&i2c0_xfer>;
438 pinctrl-names = "default";
439 #address-cells = <1>;
440 #size-cells = <0>;
445 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
449 clock-names = "baudclk", "apb_pclk";
451 pinctrl-0 = <&uart0_xfer>;
452 pinctrl-names = "default";
453 reg-io-width = <4>;
454 reg-shift = <2>;
459 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
462 clock-names = "pwm", "pclk";
463 pinctrl-0 = <&pwm0m0_pins>;
464 pinctrl-names = "default";
465 #pwm-cells = <3>;
470 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
473 clock-names = "pwm", "pclk";
474 pinctrl-0 = <&pwm1m0_pins>;
475 pinctrl-names = "default";
476 #pwm-cells = <3>;
481 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
484 clock-names = "pwm", "pclk";
485 pinctrl-0 = <&pwm2m0_pins>;
486 pinctrl-names = "default";
487 #pwm-cells = <3>;
492 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
495 clock-names = "pwm", "pclk";
496 pinctrl-0 = <&pwm3_pins>;
497 pinctrl-names = "default";
498 #pwm-cells = <3>;
502 pmu: power-management@fdd90000 {
503 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
506 power: power-controller {
507 compatible = "rockchip,rk3568-power-controller";
508 #power-domain-cells = <1>;
509 #address-cells = <1>;
510 #size-cells = <0>;
513 power-domain@RK3568_PD_GPU {
518 #power-domain-cells = <0>;
522 power-domain@RK3568_PD_VI {
529 #power-domain-cells = <0>;
532 power-domain@RK3568_PD_VO {
540 #power-domain-cells = <0>;
543 power-domain@RK3568_PD_RGA {
553 #power-domain-cells = <0>;
556 power-domain@RK3568_PD_VPU {
560 #power-domain-cells = <0>;
563 power-domain@RK3568_PD_RKVDEC {
567 #power-domain-cells = <0>;
570 power-domain@RK3568_PD_RKVENC {
576 #power-domain-cells = <0>;
582 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
587 interrupt-names = "job", "mmu", "gpu";
589 clock-names = "gpu", "bus";
590 #cooling-cells = <2>;
591 operating-points-v2 = <&gpu_opp_table>;
592 power-domains = <&power RK3568_PD_GPU>;
596 vpu: video-codec@fdea0400 {
597 compatible = "rockchip,rk3568-vpu";
600 interrupt-names = "vdpu";
602 clock-names = "aclk", "hclk";
604 power-domains = <&power RK3568_PD_VPU>;
608 compatible = "rockchip,rk3568-iommu";
611 clock-names = "aclk", "iface";
613 power-domains = <&power RK3568_PD_VPU>;
614 #iommu-cells = <0>;
618 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
622 clock-names = "aclk", "hclk", "sclk";
624 reset-names = "core", "axi", "ahb";
625 power-domains = <&power RK3568_PD_RGA>;
628 vepu: video-codec@fdee0000 {
629 compatible = "rockchip,rk3568-vepu";
633 clock-names = "aclk", "hclk";
635 power-domains = <&power RK3568_PD_RGA>;
639 compatible = "rockchip,rk3568-iommu";
643 clock-names = "aclk", "iface";
644 power-domains = <&power RK3568_PD_RGA>;
645 #iommu-cells = <0>;
649 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
654 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
655 fifo-depth = <0x100>;
656 max-frequency = <150000000>;
658 reset-names = "reset";
663 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
667 interrupt-names = "macirq", "eth_wake_irq";
672 clock-names = "stmmaceth", "mac_clk_rx",
677 reset-names = "stmmaceth";
679 snps,axi-config = <&gmac1_stmmac_axi_setup>;
680 snps,mixed-burst;
681 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
682 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
687 compatible = "snps,dwmac-mdio";
688 #address-cells = <0x1>;
689 #size-cells = <0x0>;
692 gmac1_stmmac_axi_setup: stmmac-axi-config {
698 gmac1_mtl_rx_setup: rx-queues-config {
699 snps,rx-queues-to-use = <1>;
703 gmac1_mtl_tx_setup: tx-queues-config {
704 snps,tx-queues-to-use = <1>;
711 reg-names = "vop", "gamma-lut";
715 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
717 power-domains = <&power RK3568_PD_VO>;
722 #address-cells = <1>;
723 #size-cells = <0>;
727 #address-cells = <1>;
728 #size-cells = <0>;
733 #address-cells = <1>;
734 #size-cells = <0>;
739 #address-cells = <1>;
740 #size-cells = <0>;
746 compatible = "rockchip,rk3568-iommu";
750 clock-names = "aclk", "iface";
751 #iommu-cells = <0>;
752 power-domains = <&power RK3568_PD_VO>;
756 dsi0: dsi@fe060000 {
757 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
760 clock-names = "pclk";
762 phy-names = "dphy";
764 power-domains = <&power RK3568_PD_VO>;
765 reset-names = "apb";
771 #address-cells = <1>;
772 #size-cells = <0>;
784 dsi1: dsi@fe070000 {
785 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
788 clock-names = "pclk";
790 phy-names = "dphy";
792 power-domains = <&power RK3568_PD_VO>;
793 reset-names = "apb";
799 #address-cells = <1>;
800 #size-cells = <0>;
813 compatible = "rockchip,rk3568-dw-hdmi";
821 clock-names = "iahb", "isfr", "cec", "ref";
822 pinctrl-names = "default";
823 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
824 power-domains = <&power RK3568_PD_VO>;
825 reg-io-width = <4>;
827 #sound-dai-cells = <0>;
831 #address-cells = <1>;
832 #size-cells = <0>;
845 compatible = "rockchip,rk3568-qos", "syscon";
850 compatible = "rockchip,rk3568-qos", "syscon";
855 compatible = "rockchip,rk3568-qos", "syscon";
860 compatible = "rockchip,rk3568-qos", "syscon";
865 compatible = "rockchip,rk3568-qos", "syscon";
870 compatible = "rockchip,rk3568-qos", "syscon";
875 compatible = "rockchip,rk3568-qos", "syscon";
880 compatible = "rockchip,rk3568-qos", "syscon";
885 compatible = "rockchip,rk3568-qos", "syscon";
890 compatible = "rockchip,rk3568-qos", "syscon";
895 compatible = "rockchip,rk3568-qos", "syscon";
900 compatible = "rockchip,rk3568-qos", "syscon";
905 compatible = "rockchip,rk3568-qos", "syscon";
910 compatible = "rockchip,rk3568-qos", "syscon";
915 compatible = "rockchip,rk3568-qos", "syscon";
920 compatible = "rockchip,rk3568-qos", "syscon";
925 compatible = "rockchip,rk3568-qos", "syscon";
930 compatible = "rockchip,rk3568-qos", "syscon";
935 compatible = "rockchip,rk3568-qos", "syscon";
940 compatible = "rockchip,rk3568-qos", "syscon";
945 compatible = "rockchip,rk3568-qos", "syscon";
950 compatible = "rockchip,rk3568-qos", "syscon";
955 compatible = "rockchip,rk3568-qos", "syscon";
960 compatible = "rockchip,rk3568-qos", "syscon";
965 compatible = "rockchip,rk3568-pcie";
969 reg-names = "dbi", "apb", "config";
975 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
976 bus-range = <0x0 0xf>;
980 clock-names = "aclk_mst", "aclk_slv",
983 #interrupt-cells = <1>;
984 interrupt-map-mask = <0 0 0 7>;
985 interrupt-map = <0 0 0 1 &pcie_intc 0>,
989 linux,pci-domain = <0>;
990 num-ib-windows = <6>;
991 num-ob-windows = <2>;
992 max-link-speed = <2>;
993 msi-map = <0x0 &gic 0x0 0x1000>;
994 num-lanes = <1>;
996 phy-names = "pcie-phy";
997 power-domains = <&power RK3568_PD_PIPE>;
1002 reset-names = "pipe";
1003 #address-cells = <3>;
1004 #size-cells = <2>;
1007 pcie_intc: legacy-interrupt-controller {
1008 #address-cells = <0>;
1009 #interrupt-cells = <1>;
1010 interrupt-controller;
1011 interrupt-parent = <&gic>;
1017 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1022 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1023 fifo-depth = <0x100>;
1024 max-frequency = <150000000>;
1026 reset-names = "reset";
1031 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1036 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1037 fifo-depth = <0x100>;
1038 max-frequency = <150000000>;
1040 reset-names = "reset";
1049 clock-names = "clk_sfc", "hclk_sfc";
1050 pinctrl-0 = <&fspi_pins>;
1051 pinctrl-names = "default";
1056 compatible = "rockchip,rk3568-dwcmshc";
1059 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1060 assigned-clock-rates = <200000000>, <24000000>;
1064 clock-names = "core", "bus", "axi", "block", "timer";
1069 compatible = "rockchip,rk3568-i2s-tdm";
1072 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1073 assigned-clock-rates = <1188000000>, <1188000000>;
1075 clock-names = "mclk_tx", "mclk_rx", "hclk";
1077 dma-names = "tx";
1079 reset-names = "tx-m", "rx-m";
1081 #sound-dai-cells = <0>;
1086 compatible = "rockchip,rk3568-i2s-tdm";
1089 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1090 assigned-clock-rates = <1188000000>, <1188000000>;
1093 clock-names = "mclk_tx", "mclk_rx", "hclk";
1095 dma-names = "rx", "tx";
1097 reset-names = "tx-m", "rx-m";
1099 pinctrl-names = "default";
1100 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1106 #sound-dai-cells = <0>;
1111 compatible = "rockchip,rk3568-i2s-tdm";
1114 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1115 assigned-clock-rates = <1188000000>;
1117 clock-names = "mclk_tx", "mclk_rx", "hclk";
1119 dma-names = "tx", "rx";
1121 reset-names = "tx-m";
1123 pinctrl-names = "default";
1124 pinctrl-0 = <&i2s2m0_sclktx
1128 #sound-dai-cells = <0>;
1133 compatible = "rockchip,rk3568-i2s-tdm";
1138 clock-names = "mclk_tx", "mclk_rx", "hclk";
1140 dma-names = "tx", "rx";
1142 reset-names = "tx-m", "rx-m";
1144 #sound-dai-cells = <0>;
1149 compatible = "rockchip,rk3568-pdm";
1153 clock-names = "pdm_clk", "pdm_hclk";
1155 dma-names = "rx";
1156 pinctrl-0 = <&pdmm0_clk
1162 pinctrl-names = "default";
1164 reset-names = "pdm-m";
1165 #sound-dai-cells = <0>;
1170 compatible = "rockchip,rk3568-spdif";
1173 clock-names = "mclk", "hclk";
1176 dma-names = "tx";
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&spdifm0_tx>;
1179 #sound-dai-cells = <0>;
1183 dmac0: dma-controller@fe530000 {
1188 arm,pl330-periph-burst;
1190 clock-names = "apb_pclk";
1191 #dma-cells = <1>;
1194 dmac1: dma-controller@fe550000 {
1199 arm,pl330-periph-burst;
1201 clock-names = "apb_pclk";
1202 #dma-cells = <1>;
1206 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1210 clock-names = "i2c", "pclk";
1211 pinctrl-0 = <&i2c1_xfer>;
1212 pinctrl-names = "default";
1213 #address-cells = <1>;
1214 #size-cells = <0>;
1219 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1223 clock-names = "i2c", "pclk";
1224 pinctrl-0 = <&i2c2m0_xfer>;
1225 pinctrl-names = "default";
1226 #address-cells = <1>;
1227 #size-cells = <0>;
1232 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1236 clock-names = "i2c", "pclk";
1237 pinctrl-0 = <&i2c3m0_xfer>;
1238 pinctrl-names = "default";
1239 #address-cells = <1>;
1240 #size-cells = <0>;
1245 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1249 clock-names = "i2c", "pclk";
1250 pinctrl-0 = <&i2c4m0_xfer>;
1251 pinctrl-names = "default";
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1258 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1262 clock-names = "i2c", "pclk";
1263 pinctrl-0 = <&i2c5m0_xfer>;
1264 pinctrl-names = "default";
1265 #address-cells = <1>;
1266 #size-cells = <0>;
1271 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1275 clock-names = "tclk", "pclk";
1279 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1283 clock-names = "spiclk", "apb_pclk";
1285 dma-names = "tx", "rx";
1286 pinctrl-names = "default";
1287 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1294 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1298 clock-names = "spiclk", "apb_pclk";
1300 dma-names = "tx", "rx";
1301 pinctrl-names = "default";
1302 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1309 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1313 clock-names = "spiclk", "apb_pclk";
1315 dma-names = "tx", "rx";
1316 pinctrl-names = "default";
1317 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1318 #address-cells = <1>;
1319 #size-cells = <0>;
1324 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1328 clock-names = "spiclk", "apb_pclk";
1330 dma-names = "tx", "rx";
1331 pinctrl-names = "default";
1332 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1339 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1343 clock-names = "baudclk", "apb_pclk";
1345 pinctrl-0 = <&uart1m0_xfer>;
1346 pinctrl-names = "default";
1347 reg-io-width = <4>;
1348 reg-shift = <2>;
1353 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1357 clock-names = "baudclk", "apb_pclk";
1359 pinctrl-0 = <&uart2m0_xfer>;
1360 pinctrl-names = "default";
1361 reg-io-width = <4>;
1362 reg-shift = <2>;
1367 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1371 clock-names = "baudclk", "apb_pclk";
1373 pinctrl-0 = <&uart3m0_xfer>;
1374 pinctrl-names = "default";
1375 reg-io-width = <4>;
1376 reg-shift = <2>;
1381 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1385 clock-names = "baudclk", "apb_pclk";
1387 pinctrl-0 = <&uart4m0_xfer>;
1388 pinctrl-names = "default";
1389 reg-io-width = <4>;
1390 reg-shift = <2>;
1395 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1399 clock-names = "baudclk", "apb_pclk";
1401 pinctrl-0 = <&uart5m0_xfer>;
1402 pinctrl-names = "default";
1403 reg-io-width = <4>;
1404 reg-shift = <2>;
1409 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1413 clock-names = "baudclk", "apb_pclk";
1415 pinctrl-0 = <&uart6m0_xfer>;
1416 pinctrl-names = "default";
1417 reg-io-width = <4>;
1418 reg-shift = <2>;
1423 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1427 clock-names = "baudclk", "apb_pclk";
1429 pinctrl-0 = <&uart7m0_xfer>;
1430 pinctrl-names = "default";
1431 reg-io-width = <4>;
1432 reg-shift = <2>;
1437 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1441 clock-names = "baudclk", "apb_pclk";
1443 pinctrl-0 = <&uart8m0_xfer>;
1444 pinctrl-names = "default";
1445 reg-io-width = <4>;
1446 reg-shift = <2>;
1451 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1455 clock-names = "baudclk", "apb_pclk";
1457 pinctrl-0 = <&uart9m0_xfer>;
1458 pinctrl-names = "default";
1459 reg-io-width = <4>;
1460 reg-shift = <2>;
1464 thermal_zones: thermal-zones {
1465 cpu_thermal: cpu-thermal {
1466 polling-delay-passive = <100>;
1467 polling-delay = <1000>;
1469 thermal-sensors = <&tsadc 0>;
1489 cooling-maps {
1492 cooling-device =
1501 gpu_thermal: gpu-thermal {
1502 polling-delay-passive = <20>; /* milliseconds */
1503 polling-delay = <1000>; /* milliseconds */
1505 thermal-sensors = <&tsadc 1>;
1508 gpu_threshold: gpu-threshold {
1513 gpu_target: gpu-target {
1518 gpu_crit: gpu-crit {
1525 cooling-maps {
1528 cooling-device =
1536 compatible = "rockchip,rk3568-tsadc";
1539 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1540 assigned-clock-rates = <17000000>, <700000>;
1542 clock-names = "tsadc", "apb_pclk";
1546 rockchip,hw-tshut-temp = <95000>;
1547 pinctrl-names = "init", "default", "sleep";
1548 pinctrl-0 = <&tsadc_pin>;
1549 pinctrl-1 = <&tsadc_shutorg>;
1550 pinctrl-2 = <&tsadc_pin>;
1551 #thermal-sensor-cells = <1>;
1556 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1560 clock-names = "saradc", "apb_pclk";
1562 reset-names = "saradc-apb";
1563 #io-channel-cells = <1>;
1568 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1571 clock-names = "pwm", "pclk";
1572 pinctrl-0 = <&pwm4_pins>;
1573 pinctrl-names = "default";
1574 #pwm-cells = <3>;
1579 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1582 clock-names = "pwm", "pclk";
1583 pinctrl-0 = <&pwm5_pins>;
1584 pinctrl-names = "default";
1585 #pwm-cells = <3>;
1590 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1593 clock-names = "pwm", "pclk";
1594 pinctrl-0 = <&pwm6_pins>;
1595 pinctrl-names = "default";
1596 #pwm-cells = <3>;
1601 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1604 clock-names = "pwm", "pclk";
1605 pinctrl-0 = <&pwm7_pins>;
1606 pinctrl-names = "default";
1607 #pwm-cells = <3>;
1612 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1615 clock-names = "pwm", "pclk";
1616 pinctrl-0 = <&pwm8m0_pins>;
1617 pinctrl-names = "default";
1618 #pwm-cells = <3>;
1623 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1626 clock-names = "pwm", "pclk";
1627 pinctrl-0 = <&pwm9m0_pins>;
1628 pinctrl-names = "default";
1629 #pwm-cells = <3>;
1634 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1637 clock-names = "pwm", "pclk";
1638 pinctrl-0 = <&pwm10m0_pins>;
1639 pinctrl-names = "default";
1640 #pwm-cells = <3>;
1645 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1648 clock-names = "pwm", "pclk";
1649 pinctrl-0 = <&pwm11m0_pins>;
1650 pinctrl-names = "default";
1651 #pwm-cells = <3>;
1656 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1659 clock-names = "pwm", "pclk";
1660 pinctrl-0 = <&pwm12m0_pins>;
1661 pinctrl-names = "default";
1662 #pwm-cells = <3>;
1667 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1670 clock-names = "pwm", "pclk";
1671 pinctrl-0 = <&pwm13m0_pins>;
1672 pinctrl-names = "default";
1673 #pwm-cells = <3>;
1678 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1681 clock-names = "pwm", "pclk";
1682 pinctrl-0 = <&pwm14m0_pins>;
1683 pinctrl-names = "default";
1684 #pwm-cells = <3>;
1689 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1692 clock-names = "pwm", "pclk";
1693 pinctrl-0 = <&pwm15m0_pins>;
1694 pinctrl-names = "default";
1695 #pwm-cells = <3>;
1700 compatible = "rockchip,rk3568-naneng-combphy";
1705 clock-names = "ref", "apb", "pipe";
1706 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1707 assigned-clock-rates = <100000000>;
1709 rockchip,pipe-grf = <&pipegrf>;
1710 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1711 #phy-cells = <1>;
1716 compatible = "rockchip,rk3568-naneng-combphy";
1721 clock-names = "ref", "apb", "pipe";
1722 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1723 assigned-clock-rates = <100000000>;
1725 rockchip,pipe-grf = <&pipegrf>;
1726 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1727 #phy-cells = <1>;
1732 compatible = "rockchip,rk3568-csi-dphy";
1735 clock-names = "pclk";
1736 #phy-cells = <0>;
1738 reset-names = "apb";
1743 dsi_dphy0: mipi-dphy@fe850000 {
1744 compatible = "rockchip,rk3568-dsi-dphy";
1746 clock-names = "ref", "pclk";
1748 #phy-cells = <0>;
1749 power-domains = <&power RK3568_PD_VO>;
1750 reset-names = "apb";
1755 dsi_dphy1: mipi-dphy@fe860000 {
1756 compatible = "rockchip,rk3568-dsi-dphy";
1758 clock-names = "ref", "pclk";
1760 #phy-cells = <0>;
1761 power-domains = <&power RK3568_PD_VO>;
1762 reset-names = "apb";
1768 compatible = "rockchip,rk3568-usb2phy";
1771 clock-names = "phyclk";
1772 clock-output-names = "clk_usbphy0_480m";
1775 #clock-cells = <0>;
1778 usb2phy0_host: host-port {
1779 #phy-cells = <0>;
1783 usb2phy0_otg: otg-port {
1784 #phy-cells = <0>;
1790 compatible = "rockchip,rk3568-usb2phy";
1793 clock-names = "phyclk";
1794 clock-output-names = "clk_usbphy1_480m";
1797 #clock-cells = <0>;
1800 usb2phy1_host: host-port {
1801 #phy-cells = <0>;
1805 usb2phy1_otg: otg-port {
1806 #phy-cells = <0>;
1812 compatible = "rockchip,rk3568-pinctrl";
1815 #address-cells = <2>;
1816 #size-cells = <2>;
1820 compatible = "rockchip,gpio-bank";
1824 gpio-controller;
1825 gpio-ranges = <&pinctrl 0 0 32>;
1826 #gpio-cells = <2>;
1827 interrupt-controller;
1828 #interrupt-cells = <2>;
1832 compatible = "rockchip,gpio-bank";
1836 gpio-controller;
1837 gpio-ranges = <&pinctrl 0 32 32>;
1838 #gpio-cells = <2>;
1839 interrupt-controller;
1840 #interrupt-cells = <2>;
1844 compatible = "rockchip,gpio-bank";
1848 gpio-controller;
1849 gpio-ranges = <&pinctrl 0 64 32>;
1850 #gpio-cells = <2>;
1851 interrupt-controller;
1852 #interrupt-cells = <2>;
1856 compatible = "rockchip,gpio-bank";
1860 gpio-controller;
1861 gpio-ranges = <&pinctrl 0 96 32>;
1862 #gpio-cells = <2>;
1863 interrupt-controller;
1864 #interrupt-cells = <2>;
1868 compatible = "rockchip,gpio-bank";
1872 gpio-controller;
1873 gpio-ranges = <&pinctrl 0 128 32>;
1874 #gpio-cells = <2>;
1875 interrupt-controller;
1876 #interrupt-cells = <2>;
1881 #include "rk3568-pinctrl.dtsi"