dts/rockchip/rk3566-soquartz-cm4.dts

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3566-soquartz.dtsi"
8 	model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
9 	compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566";
12 	vcc12v_dcin: vcc12v-dcin-regulator {
13 		compatible = "regulator-fixed";
14 		regulator-name = "vcc12v_dcin";
15 		regulator-always-on;
16 		regulator-boot-on;
17 		regulator-min-microvolt = <12000000>;
18 		regulator-max-microvolt = <12000000>;
22 	vcc_5v: vcc-5v-regulator {
23 		compatible = "regulator-fixed";
24 		regulator-name = "vcc_5v";
25 		regulator-always-on;
26 		regulator-boot-on;
27 		regulator-min-microvolt = <5000000>;
28 		regulator-max-microvolt = <5000000>;
29 		vin-supply = <&vcc12v_dcin>;
32 	vcc_sd_pwr: vcc-sd-pwr-regulator {
33 		compatible = "regulator-fixed";
34 		regulator-name = "vcc_sd_pwr";
35 		regulator-always-on;
36 		regulator-boot-on;
37 		regulator-min-microvolt = <3300000>;
38 		regulator-max-microvolt = <3300000>;
39 		vin-supply = <&vcc3v3_sys>;
45 	phy-supply = <&vcc3v3_sys>;
55  * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
56  * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
72  * i2c2 is exposed on CM1 / Module1A - to PI40
73  * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
74  * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
81  * i2c3 is exposed on CM1 / Module1A - to PI40
82  * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
83  * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
90  * i2c4 is exposed on CM2 / Module1B - to PI40
91  * pin 45 - GPIO24 - i2c4_scl_m1
92  * pin 47 - GPIO23 - i2c4_sda_m1
99  * i2s1_8ch is exposed on CM1 / Module1A - to PI40
100  * pin 24 - GPIO26 - i2s1_sdi1_m1
101  * pin 25 - GPIO21 - i2s1_sdo0_m1
102  * pin 26 - GPIO19 - i2s1_lrck_tx_m1
103  * pin 27 - GPIO20 - i2s1_sdi0_m1
104  * pin 29 - GPIO16 - i2s1_sdi3_m1
105  * pin 30 - GPIO6  - i2s1_sdi2_m1
106  * pin 40 - GPIO9  - i2s1_sdo1_m1, shared with spi3
107  * pin 41 - GPIO25 - i2s1_sdo2_m1
108  * pin 49 - GPIO18 - i2s1_sclk_tx_m1
109  * pin 50 - GPIO17 - i2s1_mclk_m1
110  * pin 56 - GPIO3  - i2s1_sdo3_m1, shared with i2c2
125 	vpcie3v3-supply = <&vcc_3v3>;
134  * saradc is exposed on CM1 / Module1A - to J2
135  * pin 94 - AIN1 - saradc_vin3
136  * pin 96 - AIN0 - saradc_vin2
143 	vmmc-supply = <&vcc_sd_pwr>;
148  *  spi3 is exposed on CM1 / Module1A - to PI40
149  * pin 37 - GPIO7  - spi3_cs1_m0
150  * pin 38 - GPIO11 - spi3_clk_m0
151  * pin 39 - GPIO8  - spi3_cs0_m0
152  * pin 40 - GPIO9  - spi3_miso_m0, shared with i2s1_8ch
153  * pin 44 - GPIO10 - spi3_mosi_m0
160  * uart2 is exposed on CM1 / Module1A - to PI40
161  * pin 51 - GPIO15 - uart2_rx_m0
162  * pin 55 - GPIO14 - uart2_tx_m0
169  * uart7 is exposed on CM1 / Module1A - to PI40
170  * pin 46 - GPIO22 - uart7_tx_m2
171  * pin 47 - GPIO23 - uart7_rx_m2
182 	phy-supply = <&vcc_5v>;
191 	vin-supply = <&vcc_5v>;