Lines Matching +full:tsadc +full:- +full:apb
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
40 #address-cells = <2>;
41 #size-cells = <0>;
43 cpu-map {
71 compatible = "arm,cortex-a53";
73 enable-method = "psci";
74 capacity-dmips-mhz = <485>;
76 #cooling-cells = <2>; /* min followed by max */
77 dynamic-power-coefficient = <100>;
78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 capacity-dmips-mhz = <485>;
88 #cooling-cells = <2>; /* min followed by max */
89 dynamic-power-coefficient = <100>;
90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
95 compatible = "arm,cortex-a53";
97 enable-method = "psci";
98 capacity-dmips-mhz = <485>;
100 #cooling-cells = <2>; /* min followed by max */
101 dynamic-power-coefficient = <100>;
102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
107 compatible = "arm,cortex-a53";
109 enable-method = "psci";
110 capacity-dmips-mhz = <485>;
112 #cooling-cells = <2>; /* min followed by max */
113 dynamic-power-coefficient = <100>;
114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
119 compatible = "arm,cortex-a72";
121 enable-method = "psci";
122 capacity-dmips-mhz = <1024>;
124 #cooling-cells = <2>; /* min followed by max */
125 dynamic-power-coefficient = <436>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
128 thermal-idle {
129 #cooling-cells = <2>;
130 duration-us = <10000>;
131 exit-latency-us = <500>;
137 compatible = "arm,cortex-a72";
139 enable-method = "psci";
140 capacity-dmips-mhz = <1024>;
142 #cooling-cells = <2>; /* min followed by max */
143 dynamic-power-coefficient = <436>;
144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
146 thermal-idle {
147 #cooling-cells = <2>;
148 duration-us = <10000>;
149 exit-latency-us = <500>;
153 idle-states {
154 entry-method = "psci";
156 CPU_SLEEP: cpu-sleep {
157 compatible = "arm,idle-state";
158 local-timer-stop;
159 arm,psci-suspend-param = <0x0010000>;
160 entry-latency-us = <120>;
161 exit-latency-us = <250>;
162 min-residency-us = <900>;
165 CLUSTER_SLEEP: cluster-sleep {
166 compatible = "arm,idle-state";
167 local-timer-stop;
168 arm,psci-suspend-param = <0x1010000>;
169 entry-latency-us = <400>;
170 exit-latency-us = <500>;
171 min-residency-us = <2000>;
176 display-subsystem {
177 compatible = "rockchip,display-subsystem";
181 dmc: memory-controller {
182 compatible = "rockchip,rk3399-dmc";
184 devfreq-events = <&dfi>;
186 clock-names = "dmc_clk";
191 compatible = "arm,cortex-a53-pmu";
196 compatible = "arm,cortex-a72-pmu";
201 compatible = "arm,psci-1.0";
206 compatible = "arm,armv8-timer";
211 arm,no-tick-in-suspend;
215 compatible = "fixed-clock";
216 clock-frequency = <24000000>;
217 clock-output-names = "xin24m";
218 #clock-cells = <0>;
222 compatible = "rockchip,rk3399-pcie";
225 reg-names = "axi-base", "apb-base";
227 #address-cells = <3>;
228 #size-cells = <2>;
229 #interrupt-cells = <1>;
230 aspm-no-l0s;
231 bus-range = <0x0 0x1f>;
234 clock-names = "aclk", "aclk-perf",
239 interrupt-names = "sys", "legacy", "client";
240 interrupt-map-mask = <0 0 0 7>;
241 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
245 max-link-speed = <1>;
246 msi-map = <0x0 &its 0x0 0x1000>;
249 phy-names = "pcie-phy-0", "pcie-phy-1",
250 "pcie-phy-2", "pcie-phy-3";
257 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
261 pcie0_intc: interrupt-controller {
262 interrupt-controller;
263 #address-cells = <0>;
264 #interrupt-cells = <1>;
268 pcie0_ep: pcie-ep@f8000000 {
269 compatible = "rockchip,rk3399-pcie-ep";
272 reg-names = "apb-base", "mem-base";
275 clock-names = "aclk", "aclk-perf",
277 max-functions = /bits/ 8 <8>;
278 num-lanes = <4>;
283 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
287 phy-names = "pcie-phy-0", "pcie-phy-1",
288 "pcie-phy-2", "pcie-phy-3";
289 rockchip,max-outbound-regions = <32>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pcie_clkreqnb_cpm>;
296 compatible = "rockchip,rk3399-gmac";
299 interrupt-names = "macirq";
304 clock-names = "stmmaceth", "mac_clk_rx",
308 power-domains = <&power RK3399_PD_GMAC>;
310 reset-names = "stmmaceth";
317 compatible = "rockchip,rk3399-dw-mshc",
318 "rockchip,rk3288-dw-mshc";
321 max-frequency = <150000000>;
324 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
325 fifo-depth = <0x100>;
326 power-domains = <&power RK3399_PD_SDIOAUDIO>;
328 reset-names = "reset";
333 compatible = "rockchip,rk3399-dw-mshc",
334 "rockchip,rk3288-dw-mshc";
337 max-frequency = <150000000>;
338 assigned-clocks = <&cru HCLK_SD>;
339 assigned-clock-rates = <200000000>;
342 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
343 fifo-depth = <0x100>;
344 power-domains = <&power RK3399_PD_SD>;
346 reset-names = "reset";
351 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
354 arasan,soc-ctl-syscon = <&grf>;
355 assigned-clocks = <&cru SCLK_EMMC>;
356 assigned-clock-rates = <200000000>;
358 clock-names = "clk_xin", "clk_ahb";
359 clock-output-names = "emmc_cardclock";
360 #clock-cells = <0>;
362 phy-names = "phy_arasan";
363 power-domains = <&power RK3399_PD_EMMC>;
364 disable-cqe-dcmd;
369 compatible = "generic-ehci";
375 phy-names = "usb";
380 compatible = "generic-ohci";
386 phy-names = "usb";
391 compatible = "generic-ehci";
397 phy-names = "usb";
402 compatible = "generic-ohci";
408 phy-names = "usb";
413 compatible = "arm,coresight-cpu-debug", "arm,primecell";
416 clock-names = "apb_pclk";
421 compatible = "arm,coresight-cpu-debug", "arm,primecell";
424 clock-names = "apb_pclk";
429 compatible = "arm,coresight-cpu-debug", "arm,primecell";
432 clock-names = "apb_pclk";
437 compatible = "arm,coresight-cpu-debug", "arm,primecell";
440 clock-names = "apb_pclk";
445 compatible = "arm,coresight-cpu-debug", "arm,primecell";
448 clock-names = "apb_pclk";
453 compatible = "arm,coresight-cpu-debug", "arm,primecell";
456 clock-names = "apb_pclk";
461 compatible = "rockchip,rk3399-dwc3";
462 #address-cells = <2>;
463 #size-cells = <2>;
468 clock-names = "ref_clk", "suspend_clk",
472 reset-names = "usb3-otg";
481 clock-names = "ref", "bus_early", "suspend";
484 phy-names = "usb2-phy", "usb3-phy";
487 snps,dis-u2-freeclk-exists-quirk;
489 snps,dis-del-phy-power-chg-quirk;
490 snps,dis-tx-ipgap-linecheck-quirk;
491 power-domains = <&power RK3399_PD_USB3>;
497 compatible = "rockchip,rk3399-dwc3";
498 #address-cells = <2>;
499 #size-cells = <2>;
504 clock-names = "ref_clk", "suspend_clk",
508 reset-names = "usb3-otg";
517 clock-names = "ref", "bus_early", "suspend";
520 phy-names = "usb2-phy", "usb3-phy";
523 snps,dis-u2-freeclk-exists-quirk;
525 snps,dis-del-phy-power-chg-quirk;
526 snps,dis-tx-ipgap-linecheck-quirk;
527 power-domains = <&power RK3399_PD_USB3>;
533 compatible = "rockchip,rk3399-cdn-dp";
536 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
537 assigned-clock-rates = <100000000>, <200000000>;
540 clock-names = "core-clk", "pclk", "spdif", "grf";
542 power-domains = <&power RK3399_PD_HDCP>;
545 reset-names = "spdif", "dptx", "apb", "core";
547 #sound-dai-cells = <1>;
552 #address-cells = <1>;
553 #size-cells = <0>;
557 remote-endpoint = <&vopb_out_dp>;
562 remote-endpoint = <&vopl_out_dp>;
568 gic: interrupt-controller@fee00000 {
569 compatible = "arm,gic-v3";
570 #interrupt-cells = <4>;
571 #address-cells = <2>;
572 #size-cells = <2>;
574 interrupt-controller;
582 its: msi-controller@fee20000 {
583 compatible = "arm,gic-v3-its";
584 msi-controller;
585 #msi-cells = <1>;
589 ppi-partitions {
590 ppi_cluster0: interrupt-partition-0 {
594 ppi_cluster1: interrupt-partition-1 {
601 compatible = "rockchip,rk3399-saradc";
604 #io-channel-cells = <1>;
606 clock-names = "saradc", "apb_pclk";
608 reset-names = "saradc-apb";
613 compatible = "rockchip,rk3399-crypto";
617 clock-names = "hclk_master", "hclk_slave", "sclk";
619 reset-names = "master", "slave", "crypto-rst";
623 compatible = "rockchip,rk3399-crypto";
627 clock-names = "hclk_master", "hclk_slave", "sclk";
629 reset-names = "master", "slave", "crypto-rst";
633 compatible = "rockchip,rk3399-i2c";
635 assigned-clocks = <&cru SCLK_I2C1>;
636 assigned-clock-rates = <200000000>;
638 clock-names = "i2c", "pclk";
640 pinctrl-names = "default";
641 pinctrl-0 = <&i2c1_xfer>;
642 #address-cells = <1>;
643 #size-cells = <0>;
648 compatible = "rockchip,rk3399-i2c";
650 assigned-clocks = <&cru SCLK_I2C2>;
651 assigned-clock-rates = <200000000>;
653 clock-names = "i2c", "pclk";
655 pinctrl-names = "default";
656 pinctrl-0 = <&i2c2_xfer>;
657 #address-cells = <1>;
658 #size-cells = <0>;
663 compatible = "rockchip,rk3399-i2c";
665 assigned-clocks = <&cru SCLK_I2C3>;
666 assigned-clock-rates = <200000000>;
668 clock-names = "i2c", "pclk";
670 pinctrl-names = "default";
671 pinctrl-0 = <&i2c3_xfer>;
672 #address-cells = <1>;
673 #size-cells = <0>;
678 compatible = "rockchip,rk3399-i2c";
680 assigned-clocks = <&cru SCLK_I2C5>;
681 assigned-clock-rates = <200000000>;
683 clock-names = "i2c", "pclk";
685 pinctrl-names = "default";
686 pinctrl-0 = <&i2c5_xfer>;
687 #address-cells = <1>;
688 #size-cells = <0>;
693 compatible = "rockchip,rk3399-i2c";
695 assigned-clocks = <&cru SCLK_I2C6>;
696 assigned-clock-rates = <200000000>;
698 clock-names = "i2c", "pclk";
700 pinctrl-names = "default";
701 pinctrl-0 = <&i2c6_xfer>;
702 #address-cells = <1>;
703 #size-cells = <0>;
708 compatible = "rockchip,rk3399-i2c";
710 assigned-clocks = <&cru SCLK_I2C7>;
711 assigned-clock-rates = <200000000>;
713 clock-names = "i2c", "pclk";
715 pinctrl-names = "default";
716 pinctrl-0 = <&i2c7_xfer>;
717 #address-cells = <1>;
718 #size-cells = <0>;
723 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
726 clock-names = "baudclk", "apb_pclk";
728 reg-shift = <2>;
729 reg-io-width = <4>;
730 pinctrl-names = "default";
731 pinctrl-0 = <&uart0_xfer>;
736 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
739 clock-names = "baudclk", "apb_pclk";
741 reg-shift = <2>;
742 reg-io-width = <4>;
743 pinctrl-names = "default";
744 pinctrl-0 = <&uart1_xfer>;
749 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
752 clock-names = "baudclk", "apb_pclk";
754 reg-shift = <2>;
755 reg-io-width = <4>;
756 pinctrl-names = "default";
757 pinctrl-0 = <&uart2c_xfer>;
762 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
765 clock-names = "baudclk", "apb_pclk";
767 reg-shift = <2>;
768 reg-io-width = <4>;
769 pinctrl-names = "default";
770 pinctrl-0 = <&uart3_xfer>;
775 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
778 clock-names = "spiclk", "apb_pclk";
781 dma-names = "tx", "rx";
782 pinctrl-names = "default";
783 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
784 #address-cells = <1>;
785 #size-cells = <0>;
790 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
793 clock-names = "spiclk", "apb_pclk";
796 dma-names = "tx", "rx";
797 pinctrl-names = "default";
798 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
799 #address-cells = <1>;
800 #size-cells = <0>;
805 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
808 clock-names = "spiclk", "apb_pclk";
811 dma-names = "tx", "rx";
812 pinctrl-names = "default";
813 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
814 #address-cells = <1>;
815 #size-cells = <0>;
820 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
823 clock-names = "spiclk", "apb_pclk";
826 dma-names = "tx", "rx";
827 pinctrl-names = "default";
828 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
829 #address-cells = <1>;
830 #size-cells = <0>;
835 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
838 clock-names = "spiclk", "apb_pclk";
841 dma-names = "tx", "rx";
842 pinctrl-names = "default";
843 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
844 power-domains = <&power RK3399_PD_SDIOAUDIO>;
845 #address-cells = <1>;
846 #size-cells = <0>;
850 thermal_zones: thermal-zones {
851 cpu_thermal: cpu-thermal {
852 polling-delay-passive = <100>;
853 polling-delay = <1000>;
855 thermal-sensors = <&tsadc 0>;
875 cooling-maps {
878 cooling-device =
884 cooling-device =
895 gpu_thermal: gpu-thermal {
896 polling-delay-passive = <100>;
897 polling-delay = <1000>;
899 thermal-sensors = <&tsadc 1>;
914 cooling-maps {
917 cooling-device =
924 tsadc: tsadc@ff260000 { label
925 compatible = "rockchip,rk3399-tsadc";
928 assigned-clocks = <&cru SCLK_TSADC>;
929 assigned-clock-rates = <750000>;
931 clock-names = "tsadc", "apb_pclk";
933 reset-names = "tsadc-apb";
935 rockchip,hw-tshut-temp = <95000>;
936 pinctrl-names = "init", "default", "sleep";
937 pinctrl-0 = <&otp_pin>;
938 pinctrl-1 = <&otp_out>;
939 pinctrl-2 = <&otp_pin>;
940 #thermal-sensor-cells = <1>;
945 compatible = "rockchip,rk3399-qos", "syscon";
950 compatible = "rockchip,rk3399-qos", "syscon";
955 compatible = "rockchip,rk3399-qos", "syscon";
960 compatible = "rockchip,rk3399-qos", "syscon";
965 compatible = "rockchip,rk3399-qos", "syscon";
970 compatible = "rockchip,rk3399-qos", "syscon";
975 compatible = "rockchip,rk3399-qos", "syscon";
980 compatible = "rockchip,rk3399-qos", "syscon";
985 compatible = "rockchip,rk3399-qos", "syscon";
990 compatible = "rockchip,rk3399-qos", "syscon";
995 compatible = "rockchip,rk3399-qos", "syscon";
1000 compatible = "rockchip,rk3399-qos", "syscon";
1005 compatible = "rockchip,rk3399-qos", "syscon";
1010 compatible = "rockchip,rk3399-qos", "syscon";
1015 compatible = "rockchip,rk3399-qos", "syscon";
1020 compatible = "rockchip,rk3399-qos", "syscon";
1025 compatible = "rockchip,rk3399-qos", "syscon";
1030 compatible = "rockchip,rk3399-qos", "syscon";
1035 compatible = "rockchip,rk3399-qos", "syscon";
1040 compatible = "rockchip,rk3399-qos", "syscon";
1045 compatible = "rockchip,rk3399-qos", "syscon";
1050 compatible = "rockchip,rk3399-qos", "syscon";
1055 compatible = "rockchip,rk3399-qos", "syscon";
1060 compatible = "rockchip,rk3399-qos", "syscon";
1065 compatible = "rockchip,rk3399-qos", "syscon";
1069 pmu: power-management@ff310000 {
1070 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
1080 power: power-controller {
1081 compatible = "rockchip,rk3399-power-controller";
1082 #power-domain-cells = <1>;
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1087 power-domain@RK3399_PD_IEP {
1092 #power-domain-cells = <0>;
1094 power-domain@RK3399_PD_RGA {
1100 #power-domain-cells = <0>;
1102 power-domain@RK3399_PD_VCODEC {
1107 #power-domain-cells = <0>;
1109 power-domain@RK3399_PD_VDU {
1117 #power-domain-cells = <0>;
1121 power-domain@RK3399_PD_GPU {
1125 #power-domain-cells = <0>;
1129 power-domain@RK3399_PD_EDP {
1132 #power-domain-cells = <0>;
1134 power-domain@RK3399_PD_EMMC {
1138 #power-domain-cells = <0>;
1140 power-domain@RK3399_PD_GMAC {
1145 #power-domain-cells = <0>;
1147 power-domain@RK3399_PD_SD {
1152 #power-domain-cells = <0>;
1154 power-domain@RK3399_PD_SDIOAUDIO {
1158 #power-domain-cells = <0>;
1160 power-domain@RK3399_PD_TCPD0 {
1164 #power-domain-cells = <0>;
1166 power-domain@RK3399_PD_TCPD1 {
1170 #power-domain-cells = <0>;
1172 power-domain@RK3399_PD_USB3 {
1177 #power-domain-cells = <0>;
1179 power-domain@RK3399_PD_VIO {
1181 #power-domain-cells = <1>;
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1185 power-domain@RK3399_PD_HDCP {
1191 #power-domain-cells = <0>;
1193 power-domain@RK3399_PD_ISP0 {
1199 #power-domain-cells = <0>;
1201 power-domain@RK3399_PD_ISP1 {
1207 #power-domain-cells = <0>;
1209 power-domain@RK3399_PD_VO {
1211 #power-domain-cells = <1>;
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1215 power-domain@RK3399_PD_VOPB {
1221 #power-domain-cells = <0>;
1223 power-domain@RK3399_PD_VOPL {
1228 #power-domain-cells = <0>;
1236 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1239 pmu_io_domains: io-domains {
1240 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1246 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1249 clock-names = "spiclk", "apb_pclk";
1251 pinctrl-names = "default";
1252 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1259 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1262 clock-names = "baudclk", "apb_pclk";
1264 reg-shift = <2>;
1265 reg-io-width = <4>;
1266 pinctrl-names = "default";
1267 pinctrl-0 = <&uart4_xfer>;
1272 compatible = "rockchip,rk3399-i2c";
1274 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1275 assigned-clock-rates = <200000000>;
1277 clock-names = "i2c", "pclk";
1279 pinctrl-names = "default";
1280 pinctrl-0 = <&i2c0_xfer>;
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1287 compatible = "rockchip,rk3399-i2c";
1289 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1290 assigned-clock-rates = <200000000>;
1292 clock-names = "i2c", "pclk";
1294 pinctrl-names = "default";
1295 pinctrl-0 = <&i2c4_xfer>;
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1302 compatible = "rockchip,rk3399-i2c";
1304 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1305 assigned-clock-rates = <200000000>;
1307 clock-names = "i2c", "pclk";
1309 pinctrl-names = "default";
1310 pinctrl-0 = <&i2c8_xfer>;
1311 #address-cells = <1>;
1312 #size-cells = <0>;
1317 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1319 #pwm-cells = <3>;
1320 pinctrl-names = "default";
1321 pinctrl-0 = <&pwm0_pin>;
1327 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1329 #pwm-cells = <3>;
1330 pinctrl-names = "default";
1331 pinctrl-0 = <&pwm1_pin>;
1337 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1339 #pwm-cells = <3>;
1340 pinctrl-names = "default";
1341 pinctrl-0 = <&pwm2_pin>;
1347 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1349 #pwm-cells = <3>;
1350 pinctrl-names = "default";
1351 pinctrl-0 = <&pwm3a_pin>;
1358 compatible = "rockchip,rk3399-dfi";
1362 clock-names = "pclk_ddr_mon";
1366 vpu: video-codec@ff650000 {
1367 compatible = "rockchip,rk3399-vpu";
1371 interrupt-names = "vepu", "vdpu";
1373 clock-names = "aclk", "hclk";
1375 power-domains = <&power RK3399_PD_VCODEC>;
1383 clock-names = "aclk", "iface";
1384 #iommu-cells = <0>;
1385 power-domains = <&power RK3399_PD_VCODEC>;
1388 vdec: video-codec@ff660000 {
1389 compatible = "rockchip,rk3399-vdec";
1394 clock-names = "axi", "ahb", "cabac", "core";
1396 power-domains = <&power RK3399_PD_VDU>;
1404 clock-names = "aclk", "iface";
1405 power-domains = <&power RK3399_PD_VDU>;
1406 #iommu-cells = <0>;
1414 clock-names = "aclk", "iface";
1415 #iommu-cells = <0>;
1420 compatible = "rockchip,rk3399-rga";
1424 clock-names = "aclk", "hclk", "sclk";
1426 reset-names = "core", "axi", "ahb";
1427 power-domains = <&power RK3399_PD_RGA>;
1431 compatible = "rockchip,rk3399-efuse";
1433 #address-cells = <1>;
1434 #size-cells = <1>;
1436 clock-names = "pclk_efuse";
1439 cpu_id: cpu-id@7 {
1442 cpub_leakage: cpu-leakage@17 {
1445 gpu_leakage: gpu-leakage@18 {
1448 center_leakage: center-leakage@19 {
1451 cpul_leakage: cpu-leakage@1a {
1454 logic_leakage: logic-leakage@1b {
1457 wafer_info: wafer-info@1c {
1462 dmac_bus: dma-controller@ff6d0000 {
1467 #dma-cells = <1>;
1468 arm,pl330-periph-burst;
1470 clock-names = "apb_pclk";
1473 dmac_peri: dma-controller@ff6e0000 {
1478 #dma-cells = <1>;
1479 arm,pl330-periph-burst;
1481 clock-names = "apb_pclk";
1484 pmucru: clock-controller@ff750000 {
1485 compatible = "rockchip,rk3399-pmucru";
1488 clock-names = "xin24m";
1490 #clock-cells = <1>;
1491 #reset-cells = <1>;
1492 assigned-clocks = <&pmucru PLL_PPLL>;
1493 assigned-clock-rates = <676000000>;
1496 cru: clock-controller@ff760000 {
1497 compatible = "rockchip,rk3399-cru";
1500 clock-names = "xin24m";
1502 #clock-cells = <1>;
1503 #reset-cells = <1>;
1504 assigned-clocks =
1516 assigned-clock-rates =
1531 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1533 #address-cells = <1>;
1534 #size-cells = <1>;
1536 io_domains: io-domains {
1537 compatible = "rockchip,rk3399-io-voltage-domain";
1541 mipi_dphy_rx0: mipi-dphy-rx0 {
1542 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1546 clock-names = "dphy-ref", "dphy-cfg", "grf";
1547 power-domains = <&power RK3399_PD_VIO>;
1548 #phy-cells = <0>;
1553 compatible = "rockchip,rk3399-usb2phy";
1556 clock-names = "phyclk";
1557 #clock-cells = <0>;
1558 clock-output-names = "clk_usbphy0_480m";
1561 u2phy0_host: host-port {
1562 #phy-cells = <0>;
1564 interrupt-names = "linestate";
1568 u2phy0_otg: otg-port {
1569 #phy-cells = <0>;
1573 interrupt-names = "otg-bvalid", "otg-id",
1580 compatible = "rockchip,rk3399-usb2phy";
1583 clock-names = "phyclk";
1584 #clock-cells = <0>;
1585 clock-output-names = "clk_usbphy1_480m";
1588 u2phy1_host: host-port {
1589 #phy-cells = <0>;
1591 interrupt-names = "linestate";
1595 u2phy1_otg: otg-port {
1596 #phy-cells = <0>;
1600 interrupt-names = "otg-bvalid", "otg-id",
1607 compatible = "rockchip,rk3399-emmc-phy";
1610 clock-names = "emmcclk";
1611 drive-impedance-ohm = <50>;
1612 #phy-cells = <0>;
1616 pcie_phy: pcie-phy {
1617 compatible = "rockchip,rk3399-pcie-phy";
1619 clock-names = "refclk";
1620 #phy-cells = <1>;
1622 reset-names = "phy";
1628 compatible = "rockchip,rk3399-typec-phy";
1632 clock-names = "tcpdcore", "tcpdphy-ref";
1633 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1634 assigned-clock-rates = <50000000>;
1635 power-domains = <&power RK3399_PD_TCPD0>;
1639 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1643 tcphy0_dp: dp-port {
1644 #phy-cells = <0>;
1647 tcphy0_usb3: usb3-port {
1648 #phy-cells = <0>;
1653 compatible = "rockchip,rk3399-typec-phy";
1657 clock-names = "tcpdcore", "tcpdphy-ref";
1658 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1659 assigned-clock-rates = <50000000>;
1660 power-domains = <&power RK3399_PD_TCPD1>;
1664 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1668 tcphy1_dp: dp-port {
1669 #phy-cells = <0>;
1672 tcphy1_usb3: usb3-port {
1673 #phy-cells = <0>;
1678 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
1685 compatible = "rockchip,rk3399-timer";
1689 clock-names = "pclk", "timer";
1693 compatible = "rockchip,rk3399-spdif";
1697 dma-names = "tx";
1698 clock-names = "mclk", "hclk";
1700 pinctrl-names = "default";
1701 pinctrl-0 = <&spdif_bus>;
1702 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1703 #sound-dai-cells = <0>;
1708 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1713 dma-names = "tx", "rx";
1714 clock-names = "i2s_clk", "i2s_hclk";
1716 pinctrl-names = "bclk_on", "bclk_off";
1717 pinctrl-0 = <&i2s0_8ch_bus>;
1718 pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
1719 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1720 #sound-dai-cells = <0>;
1725 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1729 dma-names = "tx", "rx";
1730 clock-names = "i2s_clk", "i2s_hclk";
1732 pinctrl-names = "default";
1733 pinctrl-0 = <&i2s1_2ch_bus>;
1734 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1735 #sound-dai-cells = <0>;
1740 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1744 dma-names = "tx", "rx";
1745 clock-names = "i2s_clk", "i2s_hclk";
1747 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1748 #sound-dai-cells = <0>;
1753 compatible = "rockchip,rk3399-vop-lit";
1756 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1757 assigned-clock-rates = <400000000>, <100000000>;
1759 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1761 power-domains = <&power RK3399_PD_VOPL>;
1763 reset-names = "axi", "ahb", "dclk";
1767 #address-cells = <1>;
1768 #size-cells = <0>;
1772 remote-endpoint = <&mipi_in_vopl>;
1777 remote-endpoint = <&edp_in_vopl>;
1782 remote-endpoint = <&hdmi_in_vopl>;
1787 remote-endpoint = <&mipi1_in_vopl>;
1792 remote-endpoint = <&dp_in_vopl>;
1802 clock-names = "aclk", "iface";
1803 power-domains = <&power RK3399_PD_VOPL>;
1804 #iommu-cells = <0>;
1809 compatible = "rockchip,rk3399-vop-big";
1812 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1813 assigned-clock-rates = <400000000>, <100000000>;
1815 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1817 power-domains = <&power RK3399_PD_VOPB>;
1819 reset-names = "axi", "ahb", "dclk";
1823 #address-cells = <1>;
1824 #size-cells = <0>;
1828 remote-endpoint = <&edp_in_vopb>;
1833 remote-endpoint = <&mipi_in_vopb>;
1838 remote-endpoint = <&hdmi_in_vopb>;
1843 remote-endpoint = <&mipi1_in_vopb>;
1848 remote-endpoint = <&dp_in_vopb>;
1858 clock-names = "aclk", "iface";
1859 power-domains = <&power RK3399_PD_VOPB>;
1860 #iommu-cells = <0>;
1865 compatible = "rockchip,rk3399-cif-isp";
1871 clock-names = "isp", "aclk", "hclk";
1874 phy-names = "dphy";
1875 power-domains = <&power RK3399_PD_ISP0>;
1879 #address-cells = <1>;
1880 #size-cells = <0>;
1884 #address-cells = <1>;
1885 #size-cells = <0>;
1895 clock-names = "aclk", "iface";
1896 #iommu-cells = <0>;
1897 power-domains = <&power RK3399_PD_ISP0>;
1898 rockchip,disable-mmu-reset;
1902 compatible = "rockchip,rk3399-cif-isp";
1908 clock-names = "isp", "aclk", "hclk";
1911 phy-names = "dphy";
1912 power-domains = <&power RK3399_PD_ISP1>;
1916 #address-cells = <1>;
1917 #size-cells = <0>;
1921 #address-cells = <1>;
1922 #size-cells = <0>;
1932 clock-names = "aclk", "iface";
1933 #iommu-cells = <0>;
1934 power-domains = <&power RK3399_PD_ISP1>;
1935 rockchip,disable-mmu-reset;
1938 hdmi_sound: hdmi-sound {
1939 compatible = "simple-audio-card";
1940 simple-audio-card,format = "i2s";
1941 simple-audio-card,mclk-fs = <256>;
1942 simple-audio-card,name = "hdmi-sound";
1945 simple-audio-card,cpu {
1946 sound-dai = <&i2s2>;
1948 simple-audio-card,codec {
1949 sound-dai = <&hdmi>;
1954 compatible = "rockchip,rk3399-dw-hdmi";
1956 reg-io-width = <4>;
1963 clock-names = "iahb", "isfr", "cec", "grf", "ref";
1964 power-domains = <&power RK3399_PD_HDCP>;
1966 #sound-dai-cells = <0>;
1970 #address-cells = <1>;
1971 #size-cells = <0>;
1975 #address-cells = <1>;
1976 #size-cells = <0>;
1980 remote-endpoint = <&vopb_out_hdmi>;
1984 remote-endpoint = <&vopl_out_hdmi>;
1995 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
2000 clock-names = "ref", "pclk", "phy_cfg", "grf";
2001 power-domains = <&power RK3399_PD_VIO>;
2003 reset-names = "apb";
2005 #address-cells = <1>;
2006 #size-cells = <0>;
2010 #address-cells = <1>;
2011 #size-cells = <0>;
2015 #address-cells = <1>;
2016 #size-cells = <0>;
2020 remote-endpoint = <&vopb_out_mipi>;
2025 remote-endpoint = <&vopl_out_mipi>;
2036 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
2041 clock-names = "ref", "pclk", "phy_cfg", "grf";
2042 power-domains = <&power RK3399_PD_VIO>;
2044 reset-names = "apb";
2046 #address-cells = <1>;
2047 #size-cells = <0>;
2048 #phy-cells = <0>;
2052 #address-cells = <1>;
2053 #size-cells = <0>;
2057 #address-cells = <1>;
2058 #size-cells = <0>;
2062 remote-endpoint = <&vopb_out_mipi1>;
2067 remote-endpoint = <&vopl_out_mipi1>;
2078 compatible = "rockchip,rk3399-edp";
2082 clock-names = "dp", "pclk", "grf";
2083 pinctrl-names = "default";
2084 pinctrl-0 = <&edp_hpd>;
2085 power-domains = <&power RK3399_PD_EDP>;
2087 reset-names = "dp";
2092 #address-cells = <1>;
2093 #size-cells = <0>;
2097 #address-cells = <1>;
2098 #size-cells = <0>;
2102 remote-endpoint = <&vopb_out_edp>;
2107 remote-endpoint = <&vopl_out_edp>;
2118 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
2123 interrupt-names = "job", "mmu", "gpu";
2125 #cooling-cells = <2>;
2126 power-domains = <&power RK3399_PD_GPU>;
2131 compatible = "rockchip,rk3399-pinctrl";
2134 #address-cells = <2>;
2135 #size-cells = <2>;
2139 compatible = "rockchip,gpio-bank";
2144 gpio-controller;
2145 #gpio-cells = <0x2>;
2147 interrupt-controller;
2148 #interrupt-cells = <0x2>;
2152 compatible = "rockchip,gpio-bank";
2157 gpio-controller;
2158 #gpio-cells = <0x2>;
2160 interrupt-controller;
2161 #interrupt-cells = <0x2>;
2165 compatible = "rockchip,gpio-bank";
2170 gpio-controller;
2171 #gpio-cells = <0x2>;
2173 interrupt-controller;
2174 #interrupt-cells = <0x2>;
2178 compatible = "rockchip,gpio-bank";
2183 gpio-controller;
2184 #gpio-cells = <0x2>;
2186 interrupt-controller;
2187 #interrupt-cells = <0x2>;
2191 compatible = "rockchip,gpio-bank";
2196 gpio-controller;
2197 #gpio-cells = <0x2>;
2199 interrupt-controller;
2200 #interrupt-cells = <0x2>;
2203 pcfg_pull_up: pcfg-pull-up {
2204 bias-pull-up;
2207 pcfg_pull_down: pcfg-pull-down {
2208 bias-pull-down;
2211 pcfg_pull_none: pcfg-pull-none {
2212 bias-disable;
2215 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2216 bias-disable;
2217 drive-strength = <12>;
2220 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2221 bias-disable;
2222 drive-strength = <13>;
2225 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2226 bias-disable;
2227 drive-strength = <18>;
2230 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2231 bias-disable;
2232 drive-strength = <20>;
2235 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2236 bias-pull-up;
2237 drive-strength = <2>;
2240 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2241 bias-pull-up;
2242 drive-strength = <8>;
2245 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2246 bias-pull-up;
2247 drive-strength = <18>;
2250 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2251 bias-pull-up;
2252 drive-strength = <20>;
2255 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2256 bias-pull-down;
2257 drive-strength = <4>;
2260 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2261 bias-pull-down;
2262 drive-strength = <8>;
2265 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2266 bias-pull-down;
2267 drive-strength = <12>;
2270 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2271 bias-pull-down;
2272 drive-strength = <18>;
2275 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2276 bias-pull-down;
2277 drive-strength = <20>;
2280 pcfg_output_high: pcfg-output-high {
2281 output-high;
2284 pcfg_output_low: pcfg-output-low {
2285 output-low;
2288 pcfg_input_enable: pcfg-input-enable {
2289 input-enable;
2292 pcfg_input_pull_up: pcfg-input-pull-up {
2293 input-enable;
2294 bias-pull-up;
2297 pcfg_input_pull_down: pcfg-input-pull-down {
2298 input-enable;
2299 bias-pull-down;
2303 clk_32k: clk-32k {
2309 cif_clkin: cif-clkin {
2314 cif_clkouta: cif-clkouta {
2321 edp_hpd: edp-hpd {
2328 rgmii_pins: rgmii-pins {
2362 rmii_pins: rmii-pins {
2388 i2c0_xfer: i2c0-xfer {
2396 i2c1_xfer: i2c1-xfer {
2404 i2c2_xfer: i2c2-xfer {
2412 i2c3_xfer: i2c3-xfer {
2420 i2c4_xfer: i2c4-xfer {
2428 i2c5_xfer: i2c5-xfer {
2436 i2c6_xfer: i2c6-xfer {
2444 i2c7_xfer: i2c7-xfer {
2452 i2c8_xfer: i2c8-xfer {
2460 i2s0_2ch_bus: i2s0-2ch-bus {
2470 i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off {
2480 i2s0_8ch_bus: i2s0-8ch-bus {
2493 i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {
2508 i2s1_2ch_bus: i2s1-2ch-bus {
2517 i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {
2528 sdio0_bus1: sdio0-bus1 {
2533 sdio0_bus4: sdio0-bus4 {
2541 sdio0_cmd: sdio0-cmd {
2546 sdio0_clk: sdio0-clk {
2551 sdio0_cd: sdio0-cd {
2556 sdio0_pwr: sdio0-pwr {
2561 sdio0_bkpwr: sdio0-bkpwr {
2566 sdio0_wp: sdio0-wp {
2571 sdio0_int: sdio0-int {
2578 sdmmc_bus1: sdmmc-bus1 {
2583 sdmmc_bus4: sdmmc-bus4 {
2591 sdmmc_clk: sdmmc-clk {
2596 sdmmc_cmd: sdmmc-cmd {
2601 sdmmc_cd: sdmmc-cd {
2606 sdmmc_wp: sdmmc-wp {
2613 ap_pwroff: ap-pwroff {
2617 ddrio_pwroff: ddrio-pwroff {
2623 spdif_bus: spdif-bus {
2628 spdif_bus_1: spdif-bus-1 {
2635 spi0_clk: spi0-clk {
2639 spi0_cs0: spi0-cs0 {
2643 spi0_cs1: spi0-cs1 {
2647 spi0_tx: spi0-tx {
2651 spi0_rx: spi0-rx {
2658 spi1_clk: spi1-clk {
2662 spi1_cs0: spi1-cs0 {
2666 spi1_rx: spi1-rx {
2670 spi1_tx: spi1-tx {
2677 spi2_clk: spi2-clk {
2681 spi2_cs0: spi2-cs0 {
2685 spi2_rx: spi2-rx {
2689 spi2_tx: spi2-tx {
2696 spi3_clk: spi3-clk {
2700 spi3_cs0: spi3-cs0 {
2704 spi3_rx: spi3-rx {
2708 spi3_tx: spi3-tx {
2715 spi4_clk: spi4-clk {
2719 spi4_cs0: spi4-cs0 {
2723 spi4_rx: spi4-rx {
2727 spi4_tx: spi4-tx {
2734 spi5_clk: spi5-clk {
2738 spi5_cs0: spi5-cs0 {
2742 spi5_rx: spi5-rx {
2746 spi5_tx: spi5-tx {
2753 test_clkout0: test-clkout0 {
2758 test_clkout1: test-clkout1 {
2763 test_clkout2: test-clkout2 {
2769 tsadc {
2770 otp_pin: otp-pin {
2774 otp_out: otp-out {
2780 uart0_xfer: uart0-xfer {
2786 uart0_cts: uart0-cts {
2791 uart0_rts: uart0-rts {
2798 uart1_xfer: uart1-xfer {
2806 uart2a_xfer: uart2a-xfer {
2814 uart2b_xfer: uart2b-xfer {
2822 uart2c_xfer: uart2c-xfer {
2830 uart3_xfer: uart3-xfer {
2836 uart3_cts: uart3-cts {
2841 uart3_rts: uart3-rts {
2848 uart4_xfer: uart4-xfer {
2856 uarthdcp_xfer: uarthdcp-xfer {
2864 pwm0_pin: pwm0-pin {
2869 pwm0_pin_pull_down: pwm0-pin-pull-down {
2874 vop0_pwm_pin: vop0-pwm-pin {
2879 vop1_pwm_pin: vop1-pwm-pin {
2886 pwm1_pin: pwm1-pin {
2891 pwm1_pin_pull_down: pwm1-pin-pull-down {
2898 pwm2_pin: pwm2-pin {
2903 pwm2_pin_pull_down: pwm2-pin-pull-down {
2910 pwm3a_pin: pwm3a-pin {
2917 pwm3b_pin: pwm3b-pin {
2924 hdmi_i2c_xfer: hdmi-i2c-xfer {
2930 hdmi_cec: hdmi-cec {
2937 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2942 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {