Lines Matching +full:rk3288 +full:- +full:dw +full:- +full:hdmi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
40 #address-cells = <0x2>;
41 #size-cells = <0x0>;
43 cpu-map {
77 compatible = "arm,cortex-a53";
79 enable-method = "psci";
80 #cooling-cells = <2>; /* min followed by max */
85 compatible = "arm,cortex-a53";
87 enable-method = "psci";
88 #cooling-cells = <2>; /* min followed by max */
93 compatible = "arm,cortex-a53";
95 enable-method = "psci";
96 #cooling-cells = <2>; /* min followed by max */
101 compatible = "arm,cortex-a53";
103 enable-method = "psci";
104 #cooling-cells = <2>; /* min followed by max */
109 compatible = "arm,cortex-a53";
111 enable-method = "psci";
112 #cooling-cells = <2>; /* min followed by max */
117 compatible = "arm,cortex-a53";
119 enable-method = "psci";
120 #cooling-cells = <2>; /* min followed by max */
125 compatible = "arm,cortex-a53";
127 enable-method = "psci";
128 #cooling-cells = <2>; /* min followed by max */
133 compatible = "arm,cortex-a53";
135 enable-method = "psci";
136 #cooling-cells = <2>; /* min followed by max */
140 arm-pmu {
141 compatible = "arm,armv8-pmuv3";
150 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
156 compatible = "arm,psci-0.2";
161 compatible = "arm,armv8-timer";
173 compatible = "fixed-clock";
174 clock-frequency = <24000000>;
175 clock-output-names = "xin24m";
176 #clock-cells = <0>;
180 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
182 max-frequency = <150000000>;
185 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
186 fifo-depth = <0x100>;
189 reset-names = "reset";
194 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
196 max-frequency = <150000000>;
199 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
200 fifo-depth = <0x100>;
203 reset-names = "reset";
208 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
210 max-frequency = <150000000>;
213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214 fifo-depth = <0x100>;
217 reset-names = "reset";
225 #io-channel-cells = <1>;
227 clock-names = "saradc", "apb_pclk";
229 reset-names = "saradc-apb";
234 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
237 clock-names = "spiclk", "apb_pclk";
239 pinctrl-names = "default";
240 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
241 #address-cells = <1>;
242 #size-cells = <0>;
247 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
250 clock-names = "spiclk", "apb_pclk";
252 pinctrl-names = "default";
253 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
254 #address-cells = <1>;
255 #size-cells = <0>;
260 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
263 clock-names = "spiclk", "apb_pclk";
265 pinctrl-names = "default";
266 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
267 #address-cells = <1>;
268 #size-cells = <0>;
273 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
276 #address-cells = <1>;
277 #size-cells = <0>;
278 clock-names = "i2c";
280 pinctrl-names = "default";
281 pinctrl-0 = <&i2c2_xfer>;
286 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
289 #address-cells = <1>;
290 #size-cells = <0>;
291 clock-names = "i2c";
293 pinctrl-names = "default";
294 pinctrl-0 = <&i2c3_xfer>;
299 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
302 #address-cells = <1>;
303 #size-cells = <0>;
304 clock-names = "i2c";
306 pinctrl-names = "default";
307 pinctrl-0 = <&i2c4_xfer>;
312 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
315 #address-cells = <1>;
316 #size-cells = <0>;
317 clock-names = "i2c";
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c5_xfer>;
325 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
327 clock-frequency = <24000000>;
329 clock-names = "baudclk", "apb_pclk";
331 reg-shift = <2>;
332 reg-io-width = <4>;
337 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
339 clock-frequency = <24000000>;
341 clock-names = "baudclk", "apb_pclk";
343 reg-shift = <2>;
344 reg-io-width = <4>;
349 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
351 clock-frequency = <24000000>;
353 clock-names = "baudclk", "apb_pclk";
355 reg-shift = <2>;
356 reg-io-width = <4>;
361 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
363 clock-frequency = <24000000>;
365 clock-names = "baudclk", "apb_pclk";
367 reg-shift = <2>;
368 reg-io-width = <4>;
372 dmac_peri: dma-controller@ff250000 {
377 #dma-cells = <1>;
378 arm,pl330-broken-no-flushp;
379 arm,pl330-periph-burst;
381 clock-names = "apb_pclk";
384 thermal-zones {
385 cpu_thermal: cpu-thermal {
386 polling-delay-passive = <100>; /* milliseconds */
387 polling-delay = <5000>; /* milliseconds */
389 thermal-sensors = <&tsadc 0>;
409 cooling-maps {
412 cooling-device =
420 cooling-device =
429 gpu_thermal: gpu-thermal {
430 polling-delay-passive = <100>; /* milliseconds */
431 polling-delay = <5000>; /* milliseconds */
433 thermal-sensors = <&tsadc 1>;
448 cooling-maps {
451 cooling-device =
462 compatible = "rockchip,rk3368-tsadc";
466 clock-names = "tsadc", "apb_pclk";
468 reset-names = "tsadc-apb";
469 pinctrl-names = "init", "default", "sleep";
470 pinctrl-0 = <&otp_pin>;
471 pinctrl-1 = <&otp_out>;
472 pinctrl-2 = <&otp_pin>;
473 #thermal-sensor-cells = <1>;
474 rockchip,hw-tshut-temp = <95000>;
479 compatible = "rockchip,rk3368-gmac";
482 interrupt-names = "macirq";
488 clock-names = "stmmaceth",
496 compatible = "generic-ehci";
504 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
509 clock-names = "otg";
511 g-np-tx-fifo-size = <16>;
512 g-rx-fifo-size = <275>;
513 g-tx-fifo-size = <256 128 128 64 64 32>;
517 dmac_bus: dma-controller@ff600000 {
522 #dma-cells = <1>;
523 arm,pl330-broken-no-flushp;
524 arm,pl330-periph-burst;
526 clock-names = "apb_pclk";
530 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
533 clock-names = "i2c";
535 pinctrl-names = "default";
536 pinctrl-0 = <&i2c0_xfer>;
537 #address-cells = <1>;
538 #size-cells = <0>;
543 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
546 #address-cells = <1>;
547 #size-cells = <0>;
548 clock-names = "i2c";
550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c1_xfer>;
556 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
558 #pwm-cells = <3>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pwm0_pin>;
566 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
568 #pwm-cells = <3>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&pwm1_pin>;
576 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
578 #pwm-cells = <3>;
584 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
586 #pwm-cells = <3>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&pwm3_pin>;
594 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
597 clock-names = "baudclk", "apb_pclk";
599 pinctrl-names = "default";
600 pinctrl-0 = <&uart2_xfer>;
601 reg-shift = <2>;
602 reg-io-width = <4>;
607 compatible = "rockchip,rk3368-mailbox";
614 clock-names = "pclk_mailbox";
615 #mbox-cells = <1>;
619 pmu: power-management@ff730000 {
620 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
623 power: power-controller {
624 compatible = "rockchip,rk3368-power-controller";
625 #power-domain-cells = <1>;
626 #address-cells = <1>;
627 #size-cells = <0>;
649 * *_HDMI HDMI
652 power-domain@RK3368_PD_VIO {
693 #power-domain-cells = <0>;
701 power-domain@RK3368_PD_VIDEO {
710 #power-domain-cells = <0>;
717 power-domain@RK3368_PD_GPU_1 {
723 #power-domain-cells = <0>;
729 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
732 pmu_io_domains: io-domains {
733 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
737 reboot-mode {
738 compatible = "syscon-reboot-mode";
740 mode-normal = <BOOT_NORMAL>;
741 mode-recovery = <BOOT_RECOVERY>;
742 mode-bootloader = <BOOT_FASTBOOT>;
743 mode-loader = <BOOT_BL_DOWNLOAD>;
747 cru: clock-controller@ff760000 {
748 compatible = "rockchip,rk3368-cru";
751 clock-names = "xin24m";
753 #clock-cells = <1>;
754 #reset-cells = <1>;
758 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
761 io_domains: io-domains {
762 compatible = "rockchip,rk3368-io-voltage-domain";
768 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
776 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
780 clock-names = "pclk", "timer";
784 compatible = "rockchip,rk3368-spdif";
788 clock-names = "mclk", "hclk";
790 dma-names = "tx";
791 pinctrl-names = "default";
792 pinctrl-0 = <&spdif_tx>;
793 #sound-dai-cells = <0>;
797 i2s_2ch: i2s-2ch@ff890000 {
798 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
801 clock-names = "i2s_clk", "i2s_hclk";
804 dma-names = "tx", "rx";
805 #sound-dai-cells = <0>;
809 i2s_8ch: i2s-8ch@ff898000 {
810 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
813 clock-names = "i2s_clk", "i2s_hclk";
816 dma-names = "tx", "rx";
817 pinctrl-names = "default";
818 pinctrl-0 = <&i2s_8ch_bus>;
819 #sound-dai-cells = <0>;
828 clock-names = "aclk", "iface";
829 power-domains = <&power RK3368_PD_VIO>;
830 #iommu-cells = <0>;
840 clock-names = "aclk", "iface";
841 #iommu-cells = <0>;
842 power-domains = <&power RK3368_PD_VIO>;
843 rockchip,disable-mmu-reset;
852 clock-names = "aclk", "iface";
853 power-domains = <&power RK3368_PD_VIO>;
854 #iommu-cells = <0>;
864 clock-names = "aclk", "iface";
865 #iommu-cells = <0>;
875 clock-names = "aclk", "iface";
876 #iommu-cells = <0>;
881 compatible = "rockchip,rk3368-qos", "syscon";
886 compatible = "rockchip,rk3368-qos", "syscon";
891 compatible = "rockchip,rk3368-qos", "syscon";
896 compatible = "rockchip,rk3368-qos", "syscon";
901 compatible = "rockchip,rk3368-qos", "syscon";
906 compatible = "rockchip,rk3368-qos", "syscon";
911 compatible = "rockchip,rk3368-qos", "syscon";
916 compatible = "rockchip,rk3368-qos", "syscon";
921 compatible = "rockchip,rk3368-qos", "syscon";
926 compatible = "rockchip,rk3368-qos", "syscon";
931 compatible = "rockchip,rk3368-qos", "syscon";
936 compatible = "rockchip,rk3368-qos", "syscon";
941 compatible = "rockchip,rk3368-qos", "syscon";
946 compatible = "rockchip,rk3368-efuse";
948 #address-cells = <1>;
949 #size-cells = <1>;
951 clock-names = "pclk_efuse";
953 cpu_leakage: cpu-leakage@17 {
956 temp_adjust: temp-adjust@1f {
961 gic: interrupt-controller@ffb71000 {
962 compatible = "arm,gic-400";
963 interrupt-controller;
964 #interrupt-cells = <3>;
965 #address-cells = <0>;
976 compatible = "rockchip,rk3368-pinctrl";
979 #address-cells = <0x2>;
980 #size-cells = <0x2>;
984 compatible = "rockchip,gpio-bank";
989 gpio-controller;
990 #gpio-cells = <0x2>;
992 interrupt-controller;
993 #interrupt-cells = <0x2>;
997 compatible = "rockchip,gpio-bank";
1002 gpio-controller;
1003 #gpio-cells = <0x2>;
1005 interrupt-controller;
1006 #interrupt-cells = <0x2>;
1010 compatible = "rockchip,gpio-bank";
1015 gpio-controller;
1016 #gpio-cells = <0x2>;
1018 interrupt-controller;
1019 #interrupt-cells = <0x2>;
1023 compatible = "rockchip,gpio-bank";
1028 gpio-controller;
1029 #gpio-cells = <0x2>;
1031 interrupt-controller;
1032 #interrupt-cells = <0x2>;
1035 pcfg_pull_up: pcfg-pull-up {
1036 bias-pull-up;
1039 pcfg_pull_down: pcfg-pull-down {
1040 bias-pull-down;
1043 pcfg_pull_none: pcfg-pull-none {
1044 bias-disable;
1047 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1048 bias-disable;
1049 drive-strength = <12>;
1053 emmc_clk: emmc-clk {
1057 emmc_cmd: emmc-cmd {
1061 emmc_pwr: emmc-pwr {
1065 emmc_bus1: emmc-bus1 {
1069 emmc_bus4: emmc-bus4 {
1076 emmc_bus8: emmc-bus8 {
1089 rgmii_pins: rgmii-pins {
1107 rmii_pins: rmii-pins {
1122 i2c0_xfer: i2c0-xfer {
1129 i2c1_xfer: i2c1-xfer {
1136 i2c2_xfer: i2c2-xfer {
1143 i2c3_xfer: i2c3-xfer {
1150 i2c4_xfer: i2c4-xfer {
1157 i2c5_xfer: i2c5-xfer {
1164 i2s_8ch_bus: i2s-8ch-bus {
1178 pwm0_pin: pwm0-pin {
1184 pwm1_pin: pwm1-pin {
1190 pwm3_pin: pwm3-pin {
1196 sdio0_bus1: sdio0-bus1 {
1200 sdio0_bus4: sdio0-bus4 {
1207 sdio0_cmd: sdio0-cmd {
1211 sdio0_clk: sdio0-clk {
1215 sdio0_cd: sdio0-cd {
1219 sdio0_wp: sdio0-wp {
1223 sdio0_pwr: sdio0-pwr {
1227 sdio0_bkpwr: sdio0-bkpwr {
1231 sdio0_int: sdio0-int {
1237 sdmmc_clk: sdmmc-clk {
1241 sdmmc_cmd: sdmmc-cmd {
1245 sdmmc_cd: sdmmc-cd {
1249 sdmmc_bus1: sdmmc-bus1 {
1253 sdmmc_bus4: sdmmc-bus4 {
1262 spdif_tx: spdif-tx {
1268 spi0_clk: spi0-clk {
1271 spi0_cs0: spi0-cs0 {
1274 spi0_cs1: spi0-cs1 {
1277 spi0_tx: spi0-tx {
1280 spi0_rx: spi0-rx {
1286 spi1_clk: spi1-clk {
1289 spi1_cs0: spi1-cs0 {
1292 spi1_cs1: spi1-cs1 {
1295 spi1_rx: spi1-rx {
1298 spi1_tx: spi1-tx {
1304 spi2_clk: spi2-clk {
1307 spi2_cs0: spi2-cs0 {
1310 spi2_rx: spi2-rx {
1313 spi2_tx: spi2-tx {
1319 otp_pin: otp-pin {
1323 otp_out: otp-out {
1329 uart0_xfer: uart0-xfer {
1334 uart0_cts: uart0-cts {
1338 uart0_rts: uart0-rts {
1344 uart1_xfer: uart1-xfer {
1349 uart1_cts: uart1-cts {
1353 uart1_rts: uart1-rts {
1359 uart2_xfer: uart2-xfer {
1367 uart3_xfer: uart3-xfer {
1372 uart3_cts: uart3-cts {
1376 uart3_rts: uart3-rts {
1382 uart4_xfer: uart4-xfer {
1387 uart4_cts: uart4-cts {
1391 uart4_rts: uart4-rts {