Lines Matching +full:rk3288 +full:- +full:dw +full:- +full:hdmi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
35 #address-cells = <2>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a53";
43 #cooling-cells = <2>;
44 cpu-idle-states = <&CPU_SLEEP>;
45 dynamic-power-coefficient = <120>;
46 enable-method = "psci";
47 next-level-cache = <&l2>;
48 operating-points-v2 = <&cpu0_opp_table>;
53 compatible = "arm,cortex-a53";
56 #cooling-cells = <2>;
57 cpu-idle-states = <&CPU_SLEEP>;
58 dynamic-power-coefficient = <120>;
59 enable-method = "psci";
60 next-level-cache = <&l2>;
61 operating-points-v2 = <&cpu0_opp_table>;
66 compatible = "arm,cortex-a53";
69 #cooling-cells = <2>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 dynamic-power-coefficient = <120>;
72 enable-method = "psci";
73 next-level-cache = <&l2>;
74 operating-points-v2 = <&cpu0_opp_table>;
79 compatible = "arm,cortex-a53";
82 #cooling-cells = <2>;
83 cpu-idle-states = <&CPU_SLEEP>;
84 dynamic-power-coefficient = <120>;
85 enable-method = "psci";
86 next-level-cache = <&l2>;
87 operating-points-v2 = <&cpu0_opp_table>;
90 idle-states {
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
95 local-timer-stop;
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
103 l2: l2-cache0 {
105 cache-level = <2>;
106 cache-unified;
110 cpu0_opp_table: opp-table-0 {
111 compatible = "operating-points-v2";
112 opp-shared;
114 opp-408000000 {
115 opp-hz = /bits/ 64 <408000000>;
116 opp-microvolt = <950000>;
117 clock-latency-ns = <40000>;
118 opp-suspend;
120 opp-600000000 {
121 opp-hz = /bits/ 64 <600000000>;
122 opp-microvolt = <950000>;
123 clock-latency-ns = <40000>;
125 opp-816000000 {
126 opp-hz = /bits/ 64 <816000000>;
127 opp-microvolt = <1000000>;
128 clock-latency-ns = <40000>;
130 opp-1008000000 {
131 opp-hz = /bits/ 64 <1008000000>;
132 opp-microvolt = <1100000>;
133 clock-latency-ns = <40000>;
135 opp-1200000000 {
136 opp-hz = /bits/ 64 <1200000000>;
137 opp-microvolt = <1225000>;
138 clock-latency-ns = <40000>;
140 opp-1296000000 {
141 opp-hz = /bits/ 64 <1296000000>;
142 opp-microvolt = <1300000>;
143 clock-latency-ns = <40000>;
147 analog_sound: analog-sound {
148 compatible = "simple-audio-card";
149 simple-audio-card,format = "i2s";
150 simple-audio-card,mclk-fs = <256>;
151 simple-audio-card,name = "Analog";
154 simple-audio-card,cpu {
155 sound-dai = <&i2s1>;
158 simple-audio-card,codec {
159 sound-dai = <&codec>;
163 arm-pmu {
164 compatible = "arm,cortex-a53-pmu";
169 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
172 display_subsystem: display-subsystem {
173 compatible = "rockchip,display-subsystem";
177 hdmi_sound: hdmi-sound {
178 compatible = "simple-audio-card";
179 simple-audio-card,format = "i2s";
180 simple-audio-card,mclk-fs = <128>;
181 simple-audio-card,name = "HDMI";
184 simple-audio-card,cpu {
185 sound-dai = <&i2s0>;
188 simple-audio-card,codec {
189 sound-dai = <&hdmi>;
194 compatible = "arm,psci-1.0", "arm,psci-0.2";
199 compatible = "arm,armv8-timer";
207 compatible = "fixed-clock";
208 #clock-cells = <0>;
209 clock-frequency = <24000000>;
210 clock-output-names = "xin24m";
214 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
218 clock-names = "i2s_clk", "i2s_hclk";
220 dma-names = "tx", "rx";
221 #sound-dai-cells = <0>;
226 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
230 clock-names = "i2s_clk", "i2s_hclk";
232 dma-names = "tx", "rx";
233 #sound-dai-cells = <0>;
238 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
242 clock-names = "i2s_clk", "i2s_hclk";
244 dma-names = "tx", "rx";
245 #sound-dai-cells = <0>;
250 compatible = "rockchip,rk3328-spdif";
254 clock-names = "mclk", "hclk";
256 dma-names = "tx";
257 pinctrl-names = "default";
258 pinctrl-0 = <&spdifm2_tx>;
259 #sound-dai-cells = <0>;
267 clock-names = "pdm_clk", "pdm_hclk";
269 dma-names = "rx";
270 pinctrl-names = "default", "sleep";
271 pinctrl-0 = <&pdmm0_clk
276 pinctrl-1 = <&pdmm0_clk_sleep
285 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
288 io_domains: io-domains {
289 compatible = "rockchip,rk3328-io-voltage-domain";
294 compatible = "rockchip,rk3328-grf-gpio";
295 gpio-controller;
296 #gpio-cells = <2>;
299 power: power-controller {
300 compatible = "rockchip,rk3328-power-controller";
301 #power-domain-cells = <1>;
302 #address-cells = <1>;
303 #size-cells = <0>;
305 power-domain@RK3328_PD_HEVC {
307 #power-domain-cells = <0>;
309 power-domain@RK3328_PD_VIDEO {
315 #power-domain-cells = <0>;
317 power-domain@RK3328_PD_VPU {
320 #power-domain-cells = <0>;
324 reboot-mode {
325 compatible = "syscon-reboot-mode";
327 mode-normal = <BOOT_NORMAL>;
328 mode-recovery = <BOOT_RECOVERY>;
329 mode-bootloader = <BOOT_FASTBOOT>;
330 mode-loader = <BOOT_BL_DOWNLOAD>;
335 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
339 clock-names = "baudclk", "apb_pclk";
341 dma-names = "tx", "rx";
342 pinctrl-names = "default";
343 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
344 reg-io-width = <4>;
345 reg-shift = <2>;
350 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
354 clock-names = "baudclk", "apb_pclk";
356 dma-names = "tx", "rx";
357 pinctrl-names = "default";
358 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
359 reg-io-width = <4>;
360 reg-shift = <2>;
365 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
369 clock-names = "baudclk", "apb_pclk";
371 dma-names = "tx", "rx";
372 pinctrl-names = "default";
373 pinctrl-0 = <&uart2m1_xfer>;
374 reg-io-width = <4>;
375 reg-shift = <2>;
380 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
383 #address-cells = <1>;
384 #size-cells = <0>;
386 clock-names = "i2c", "pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&i2c0_xfer>;
393 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
396 #address-cells = <1>;
397 #size-cells = <0>;
399 clock-names = "i2c", "pclk";
400 pinctrl-names = "default";
401 pinctrl-0 = <&i2c1_xfer>;
406 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
409 #address-cells = <1>;
410 #size-cells = <0>;
412 clock-names = "i2c", "pclk";
413 pinctrl-names = "default";
414 pinctrl-0 = <&i2c2_xfer>;
419 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
422 #address-cells = <1>;
423 #size-cells = <0>;
425 clock-names = "i2c", "pclk";
426 pinctrl-names = "default";
427 pinctrl-0 = <&i2c3_xfer>;
432 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
435 #address-cells = <1>;
436 #size-cells = <0>;
438 clock-names = "spiclk", "apb_pclk";
440 dma-names = "tx", "rx";
441 pinctrl-names = "default";
442 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
447 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
454 compatible = "rockchip,rk3328-pwm";
457 clock-names = "pwm", "pclk";
458 pinctrl-names = "default";
459 pinctrl-0 = <&pwm0_pin>;
460 #pwm-cells = <3>;
465 compatible = "rockchip,rk3328-pwm";
468 clock-names = "pwm", "pclk";
469 pinctrl-names = "default";
470 pinctrl-0 = <&pwm1_pin>;
471 #pwm-cells = <3>;
476 compatible = "rockchip,rk3328-pwm";
479 clock-names = "pwm", "pclk";
480 pinctrl-names = "default";
481 pinctrl-0 = <&pwm2_pin>;
482 #pwm-cells = <3>;
487 compatible = "rockchip,rk3328-pwm";
491 clock-names = "pwm", "pclk";
492 pinctrl-names = "default";
493 pinctrl-0 = <&pwmir_pin>;
494 #pwm-cells = <3>;
498 dmac: dma-controller@ff1f0000 {
503 arm,pl330-periph-burst;
505 clock-names = "apb_pclk";
506 #dma-cells = <1>;
509 thermal-zones {
510 soc_thermal: soc-thermal {
511 polling-delay-passive = <20>;
512 polling-delay = <1000>;
513 sustainable-power = <1000>;
515 thermal-sensors = <&tsadc 0>;
518 threshold: trip-point0 {
523 target: trip-point1 {
528 soc_crit: soc-crit {
535 cooling-maps {
538 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
550 compatible = "rockchip,rk3328-tsadc";
553 assigned-clocks = <&cru SCLK_TSADC>;
554 assigned-clock-rates = <50000>;
556 clock-names = "tsadc", "apb_pclk";
557 pinctrl-names = "init", "default", "sleep";
558 pinctrl-0 = <&otp_pin>;
559 pinctrl-1 = <&otp_out>;
560 pinctrl-2 = <&otp_pin>;
562 reset-names = "tsadc-apb";
564 rockchip,hw-tshut-temp = <100000>;
565 #thermal-sensor-cells = <1>;
570 compatible = "rockchip,rk3328-efuse";
572 #address-cells = <1>;
573 #size-cells = <1>;
575 clock-names = "pclk_efuse";
576 rockchip,efuse-size = <0x20>;
582 cpu_leakage: cpu-leakage@17 {
585 logic_leakage: logic-leakage@19 {
588 efuse_cpu_version: cpu-version@1a {
595 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
598 #io-channel-cells = <1>;
600 clock-names = "saradc", "apb_pclk";
602 reset-names = "saradc-apb";
607 compatible = "rockchip,rk3328-mali", "arm,mali-450";
616 interrupt-names = "gp",
624 clock-names = "bus", "core";
633 clock-names = "aclk", "iface";
634 #iommu-cells = <0>;
643 clock-names = "aclk", "iface";
644 #iommu-cells = <0>;
648 vpu: video-codec@ff350000 {
649 compatible = "rockchip,rk3328-vpu";
652 interrupt-names = "vdpu";
654 clock-names = "aclk", "hclk";
656 power-domains = <&power RK3328_PD_VPU>;
664 clock-names = "aclk", "iface";
665 #iommu-cells = <0>;
666 power-domains = <&power RK3328_PD_VPU>;
669 vdec: video-codec@ff360000 {
670 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
675 clock-names = "axi", "ahb", "cabac", "core";
676 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
678 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
680 power-domains = <&power RK3328_PD_VIDEO>;
688 clock-names = "aclk", "iface";
689 #iommu-cells = <0>;
690 power-domains = <&power RK3328_PD_VIDEO>;
694 compatible = "rockchip,rk3328-vop";
698 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
700 reset-names = "axi", "ahb", "dclk";
705 #address-cells = <1>;
706 #size-cells = <0>;
710 remote-endpoint = <&hdmi_in_vop>;
720 clock-names = "aclk", "iface";
721 #iommu-cells = <0>;
725 hdmi: hdmi@ff3c0000 { label
726 compatible = "rockchip,rk3328-dw-hdmi";
728 reg-io-width = <4>;
733 clock-names = "iahb",
737 phy-names = "hdmi";
738 pinctrl-names = "default";
739 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
741 #sound-dai-cells = <0>;
745 #address-cells = <1>;
746 #size-cells = <0>;
752 remote-endpoint = <&vop_out_hdmi>;
763 compatible = "rockchip,rk3328-codec";
766 clock-names = "pclk", "mclk";
768 #sound-dai-cells = <0>;
773 compatible = "rockchip,rk3328-hdmi-phy";
777 clock-names = "sysclk", "refoclk", "refpclk";
778 clock-output-names = "hdmi_phy";
779 #clock-cells = <0>;
780 nvmem-cells = <&efuse_cpu_version>;
781 nvmem-cell-names = "cpu-version";
782 #phy-cells = <0>;
786 cru: clock-controller@ff440000 {
787 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
790 #clock-cells = <1>;
791 #reset-cells = <1>;
792 assigned-clocks =
815 assigned-clock-parents =
819 assigned-clock-rates =
839 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
840 "simple-mfd";
842 #address-cells = <1>;
843 #size-cells = <1>;
846 compatible = "rockchip,rk3328-usb2phy";
849 clock-names = "phyclk";
850 clock-output-names = "usb480m_phy";
851 #clock-cells = <0>;
852 assigned-clocks = <&cru USB480M>;
853 assigned-clock-parents = <&u2phy>;
856 u2phy_otg: otg-port {
857 #phy-cells = <0>;
861 interrupt-names = "otg-bvalid", "otg-id",
866 u2phy_host: host-port {
867 #phy-cells = <0>;
869 interrupt-names = "linestate";
876 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
881 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
882 fifo-depth = <0x100>;
883 max-frequency = <150000000>;
888 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
893 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
894 fifo-depth = <0x100>;
895 max-frequency = <150000000>;
900 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
905 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
906 fifo-depth = <0x100>;
907 max-frequency = <150000000>;
912 compatible = "rockchip,rk3328-gmac";
915 interrupt-names = "macirq";
920 clock-names = "stmmaceth", "mac_clk_rx",
925 reset-names = "stmmaceth";
932 compatible = "rockchip,rk3328-gmac";
936 interrupt-names = "macirq";
941 clock-names = "stmmaceth", "mac_clk_rx",
946 reset-names = "stmmaceth";
947 phy-mode = "rmii";
948 phy-handle = <&phy>;
954 compatible = "snps,dwmac-mdio";
955 #address-cells = <1>;
956 #size-cells = <0>;
958 phy: ethernet-phy@0 {
959 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
963 pinctrl-names = "default";
964 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
965 phy-is-integrated;
971 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
976 clock-names = "otg";
978 g-np-tx-fifo-size = <16>;
979 g-rx-fifo-size = <280>;
980 g-tx-fifo-size = <256 128 128 64 32 16>;
982 phy-names = "usb2-phy";
987 compatible = "generic-ehci";
992 phy-names = "usb";
997 compatible = "generic-ohci";
1002 phy-names = "usb";
1007 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1012 clock-names = "ref_clk", "suspend_clk",
1016 snps,dis-del-phy-power-chg-quirk;
1018 snps,dis-tx-ipgap-linecheck-quirk;
1019 snps,dis-u2-freeclk-exists-quirk;
1025 gic: interrupt-controller@ff811000 {
1026 compatible = "arm,gic-400";
1027 #interrupt-cells = <3>;
1028 #address-cells = <0>;
1029 interrupt-controller;
1039 compatible = "rockchip,rk3328-crypto";
1044 clock-names = "hclk_master", "hclk_slave", "sclk";
1046 reset-names = "crypto-rst";
1050 compatible = "rockchip,rk3328-pinctrl";
1052 #address-cells = <2>;
1053 #size-cells = <2>;
1057 compatible = "rockchip,gpio-bank";
1062 gpio-controller;
1063 #gpio-cells = <2>;
1065 interrupt-controller;
1066 #interrupt-cells = <2>;
1070 compatible = "rockchip,gpio-bank";
1075 gpio-controller;
1076 #gpio-cells = <2>;
1078 interrupt-controller;
1079 #interrupt-cells = <2>;
1083 compatible = "rockchip,gpio-bank";
1088 gpio-controller;
1089 #gpio-cells = <2>;
1091 interrupt-controller;
1092 #interrupt-cells = <2>;
1096 compatible = "rockchip,gpio-bank";
1101 gpio-controller;
1102 #gpio-cells = <2>;
1104 interrupt-controller;
1105 #interrupt-cells = <2>;
1108 pcfg_pull_up: pcfg-pull-up {
1109 bias-pull-up;
1112 pcfg_pull_down: pcfg-pull-down {
1113 bias-pull-down;
1116 pcfg_pull_none: pcfg-pull-none {
1117 bias-disable;
1120 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1121 bias-disable;
1122 drive-strength = <2>;
1125 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1126 bias-pull-up;
1127 drive-strength = <2>;
1130 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1131 bias-pull-up;
1132 drive-strength = <4>;
1135 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1136 bias-disable;
1137 drive-strength = <4>;
1140 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1141 bias-pull-down;
1142 drive-strength = <4>;
1145 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1146 bias-disable;
1147 drive-strength = <8>;
1150 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1151 bias-pull-up;
1152 drive-strength = <8>;
1155 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1156 bias-disable;
1157 drive-strength = <12>;
1160 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1161 bias-pull-up;
1162 drive-strength = <12>;
1165 pcfg_output_high: pcfg-output-high {
1166 output-high;
1169 pcfg_output_low: pcfg-output-low {
1170 output-low;
1173 pcfg_input_high: pcfg-input-high {
1174 bias-pull-up;
1175 input-enable;
1178 pcfg_input: pcfg-input {
1179 input-enable;
1183 i2c0_xfer: i2c0-xfer {
1190 i2c1_xfer: i2c1-xfer {
1197 i2c2_xfer: i2c2-xfer {
1204 i2c3_xfer: i2c3-xfer {
1208 i2c3_pins: i2c3-pins {
1216 hdmii2c_xfer: hdmii2c-xfer {
1222 pdm-0 {
1223 pdmm0_clk: pdmm0-clk {
1227 pdmm0_fsync: pdmm0-fsync {
1231 pdmm0_sdi0: pdmm0-sdi0 {
1235 pdmm0_sdi1: pdmm0-sdi1 {
1239 pdmm0_sdi2: pdmm0-sdi2 {
1243 pdmm0_sdi3: pdmm0-sdi3 {
1247 pdmm0_clk_sleep: pdmm0-clk-sleep {
1252 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1257 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1262 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1267 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1272 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1279 otp_pin: otp-pin {
1283 otp_out: otp-out {
1289 uart0_xfer: uart0-xfer {
1294 uart0_cts: uart0-cts {
1298 uart0_rts: uart0-rts {
1302 uart0_rts_pin: uart0-rts-pin {
1308 uart1_xfer: uart1-xfer {
1313 uart1_cts: uart1-cts {
1317 uart1_rts: uart1-rts {
1321 uart1_rts_pin: uart1-rts-pin {
1326 uart2-0 {
1327 uart2m0_xfer: uart2m0-xfer {
1333 uart2-1 {
1334 uart2m1_xfer: uart2m1-xfer {
1340 spi0-0 {
1341 spi0m0_clk: spi0m0-clk {
1345 spi0m0_cs0: spi0m0-cs0 {
1349 spi0m0_tx: spi0m0-tx {
1353 spi0m0_rx: spi0m0-rx {
1357 spi0m0_cs1: spi0m0-cs1 {
1362 spi0-1 {
1363 spi0m1_clk: spi0m1-clk {
1367 spi0m1_cs0: spi0m1-cs0 {
1371 spi0m1_tx: spi0m1-tx {
1375 spi0m1_rx: spi0m1-rx {
1379 spi0m1_cs1: spi0m1-cs1 {
1384 spi0-2 {
1385 spi0m2_clk: spi0m2-clk {
1389 spi0m2_cs0: spi0m2-cs0 {
1393 spi0m2_tx: spi0m2-tx {
1397 spi0m2_rx: spi0m2-rx {
1403 i2s1_mclk: i2s1-mclk {
1407 i2s1_sclk: i2s1-sclk {
1411 i2s1_lrckrx: i2s1-lrckrx {
1415 i2s1_lrcktx: i2s1-lrcktx {
1419 i2s1_sdi: i2s1-sdi {
1423 i2s1_sdo: i2s1-sdo {
1427 i2s1_sdio1: i2s1-sdio1 {
1431 i2s1_sdio2: i2s1-sdio2 {
1435 i2s1_sdio3: i2s1-sdio3 {
1439 i2s1_sleep: i2s1-sleep {
1453 i2s2-0 {
1454 i2s2m0_mclk: i2s2m0-mclk {
1458 i2s2m0_sclk: i2s2m0-sclk {
1462 i2s2m0_lrckrx: i2s2m0-lrckrx {
1466 i2s2m0_lrcktx: i2s2m0-lrcktx {
1470 i2s2m0_sdi: i2s2m0-sdi {
1474 i2s2m0_sdo: i2s2m0-sdo {
1478 i2s2m0_sleep: i2s2m0-sleep {
1489 i2s2-1 {
1490 i2s2m1_mclk: i2s2m1-mclk {
1494 i2s2m1_sclk: i2s2m1-sclk {
1498 i2s2m1_lrckrx: i2sm1-lrckrx {
1502 i2s2m1_lrcktx: i2s2m1-lrcktx {
1506 i2s2m1_sdi: i2s2m1-sdi {
1510 i2s2m1_sdo: i2s2m1-sdo {
1514 i2s2m1_sleep: i2s2m1-sleep {
1524 spdif-0 {
1525 spdifm0_tx: spdifm0-tx {
1530 spdif-1 {
1531 spdifm1_tx: spdifm1-tx {
1536 spdif-2 {
1537 spdifm2_tx: spdifm2-tx {
1542 sdmmc0-0 {
1543 sdmmc0m0_pwren: sdmmc0m0-pwren {
1547 sdmmc0m0_pin: sdmmc0m0-pin {
1552 sdmmc0-1 {
1553 sdmmc0m1_pwren: sdmmc0m1-pwren {
1557 sdmmc0m1_pin: sdmmc0m1-pin {
1563 sdmmc0_clk: sdmmc0-clk {
1567 sdmmc0_cmd: sdmmc0-cmd {
1571 sdmmc0_dectn: sdmmc0-dectn {
1575 sdmmc0_wrprt: sdmmc0-wrprt {
1579 sdmmc0_bus1: sdmmc0-bus1 {
1583 sdmmc0_bus4: sdmmc0-bus4 {
1590 sdmmc0_pins: sdmmc0-pins {
1604 sdmmc0ext_clk: sdmmc0ext-clk {
1608 sdmmc0ext_cmd: sdmmc0ext-cmd {
1612 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1616 sdmmc0ext_dectn: sdmmc0ext-dectn {
1620 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1624 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1632 sdmmc0ext_pins: sdmmc0ext-pins {
1646 sdmmc1_clk: sdmmc1-clk {
1650 sdmmc1_cmd: sdmmc1-cmd {
1654 sdmmc1_pwren: sdmmc1-pwren {
1658 sdmmc1_wrprt: sdmmc1-wrprt {
1662 sdmmc1_dectn: sdmmc1-dectn {
1666 sdmmc1_bus1: sdmmc1-bus1 {
1670 sdmmc1_bus4: sdmmc1-bus4 {
1677 sdmmc1_pins: sdmmc1-pins {
1692 emmc_clk: emmc-clk {
1696 emmc_cmd: emmc-cmd {
1700 emmc_pwren: emmc-pwren {
1704 emmc_rstnout: emmc-rstnout {
1708 emmc_bus1: emmc-bus1 {
1712 emmc_bus4: emmc-bus4 {
1720 emmc_bus8: emmc-bus8 {
1734 pwm0_pin: pwm0-pin {
1740 pwm1_pin: pwm1-pin {
1746 pwm2_pin: pwm2-pin {
1752 pwmir_pin: pwmir-pin {
1757 gmac-1 {
1758 rgmiim1_pins: rgmiim1-pins {
1807 rmiim1_pins: rmiim1-pins {
1846 fephyled_speed10: fephyled-speed10 {
1850 fephyled_duplex: fephyled-duplex {
1854 fephyled_rxm1: fephyled-rxm1 {
1858 fephyled_txm1: fephyled-txm1 {
1862 fephyled_linkm1: fephyled-linkm1 {
1868 tsadc_int: tsadc-int {
1871 tsadc_pin: tsadc-pin {
1877 hdmi_cec: hdmi-cec {
1881 hdmi_hpd: hdmi-hpd {
1886 cif-0 {
1887 dvp_d2d9_m0:dvp-d2d9-m0 {
1916 cif-1 {
1917 dvp_d2d9_m1:dvp-d2d9-m1 {