Lines Matching +full:dclk +full:- +full:div
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
35 #address-cells = <2>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a53";
43 #cooling-cells = <2>;
44 cpu-idle-states = <&CPU_SLEEP>;
45 dynamic-power-coefficient = <120>;
46 enable-method = "psci";
47 next-level-cache = <&l2>;
48 operating-points-v2 = <&cpu0_opp_table>;
53 compatible = "arm,cortex-a53";
56 #cooling-cells = <2>;
57 cpu-idle-states = <&CPU_SLEEP>;
58 dynamic-power-coefficient = <120>;
59 enable-method = "psci";
60 next-level-cache = <&l2>;
61 operating-points-v2 = <&cpu0_opp_table>;
66 compatible = "arm,cortex-a53";
69 #cooling-cells = <2>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 dynamic-power-coefficient = <120>;
72 enable-method = "psci";
73 next-level-cache = <&l2>;
74 operating-points-v2 = <&cpu0_opp_table>;
79 compatible = "arm,cortex-a53";
82 #cooling-cells = <2>;
83 cpu-idle-states = <&CPU_SLEEP>;
84 dynamic-power-coefficient = <120>;
85 enable-method = "psci";
86 next-level-cache = <&l2>;
87 operating-points-v2 = <&cpu0_opp_table>;
90 idle-states {
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
95 local-timer-stop;
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
103 l2: l2-cache0 {
105 cache-level = <2>;
106 cache-unified;
110 cpu0_opp_table: opp-table-0 {
111 compatible = "operating-points-v2";
112 opp-shared;
114 opp-408000000 {
115 opp-hz = /bits/ 64 <408000000>;
116 opp-microvolt = <950000>;
117 clock-latency-ns = <40000>;
118 opp-suspend;
120 opp-600000000 {
121 opp-hz = /bits/ 64 <600000000>;
122 opp-microvolt = <950000>;
123 clock-latency-ns = <40000>;
125 opp-816000000 {
126 opp-hz = /bits/ 64 <816000000>;
127 opp-microvolt = <1000000>;
128 clock-latency-ns = <40000>;
130 opp-1008000000 {
131 opp-hz = /bits/ 64 <1008000000>;
132 opp-microvolt = <1100000>;
133 clock-latency-ns = <40000>;
135 opp-1200000000 {
136 opp-hz = /bits/ 64 <1200000000>;
137 opp-microvolt = <1225000>;
138 clock-latency-ns = <40000>;
140 opp-1296000000 {
141 opp-hz = /bits/ 64 <1296000000>;
142 opp-microvolt = <1300000>;
143 clock-latency-ns = <40000>;
147 analog_sound: analog-sound {
148 compatible = "simple-audio-card";
149 simple-audio-card,format = "i2s";
150 simple-audio-card,mclk-fs = <256>;
151 simple-audio-card,name = "Analog";
154 simple-audio-card,cpu {
155 sound-dai = <&i2s1>;
158 simple-audio-card,codec {
159 sound-dai = <&codec>;
163 arm-pmu {
164 compatible = "arm,cortex-a53-pmu";
169 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
172 display_subsystem: display-subsystem {
173 compatible = "rockchip,display-subsystem";
177 hdmi_sound: hdmi-sound {
178 compatible = "simple-audio-card";
179 simple-audio-card,format = "i2s";
180 simple-audio-card,mclk-fs = <128>;
181 simple-audio-card,name = "HDMI";
184 simple-audio-card,cpu {
185 sound-dai = <&i2s0>;
188 simple-audio-card,codec {
189 sound-dai = <&hdmi>;
194 compatible = "arm,psci-1.0", "arm,psci-0.2";
199 compatible = "arm,armv8-timer";
207 compatible = "fixed-clock";
208 #clock-cells = <0>;
209 clock-frequency = <24000000>;
210 clock-output-names = "xin24m";
214 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
218 clock-names = "i2s_clk", "i2s_hclk";
220 dma-names = "tx", "rx";
221 #sound-dai-cells = <0>;
226 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
230 clock-names = "i2s_clk", "i2s_hclk";
232 dma-names = "tx", "rx";
233 #sound-dai-cells = <0>;
238 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
242 clock-names = "i2s_clk", "i2s_hclk";
244 dma-names = "tx", "rx";
245 #sound-dai-cells = <0>;
250 compatible = "rockchip,rk3328-spdif";
254 clock-names = "mclk", "hclk";
256 dma-names = "tx";
257 pinctrl-names = "default";
258 pinctrl-0 = <&spdifm2_tx>;
259 #sound-dai-cells = <0>;
267 clock-names = "pdm_clk", "pdm_hclk";
269 dma-names = "rx";
270 pinctrl-names = "default", "sleep";
271 pinctrl-0 = <&pdmm0_clk
276 pinctrl-1 = <&pdmm0_clk_sleep
285 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
288 io_domains: io-domains {
289 compatible = "rockchip,rk3328-io-voltage-domain";
294 compatible = "rockchip,rk3328-grf-gpio";
295 gpio-controller;
296 #gpio-cells = <2>;
299 power: power-controller {
300 compatible = "rockchip,rk3328-power-controller";
301 #power-domain-cells = <1>;
302 #address-cells = <1>;
303 #size-cells = <0>;
305 power-domain@RK3328_PD_HEVC {
308 #power-domain-cells = <0>;
310 power-domain@RK3328_PD_VIDEO {
316 #power-domain-cells = <0>;
318 power-domain@RK3328_PD_VPU {
321 #power-domain-cells = <0>;
325 reboot-mode {
326 compatible = "syscon-reboot-mode";
328 mode-normal = <BOOT_NORMAL>;
329 mode-recovery = <BOOT_RECOVERY>;
330 mode-bootloader = <BOOT_FASTBOOT>;
331 mode-loader = <BOOT_BL_DOWNLOAD>;
336 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
340 clock-names = "baudclk", "apb_pclk";
342 dma-names = "tx", "rx";
343 pinctrl-names = "default";
344 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
345 reg-io-width = <4>;
346 reg-shift = <2>;
351 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
355 clock-names = "baudclk", "apb_pclk";
357 dma-names = "tx", "rx";
358 pinctrl-names = "default";
359 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
360 reg-io-width = <4>;
361 reg-shift = <2>;
366 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
370 clock-names = "baudclk", "apb_pclk";
372 dma-names = "tx", "rx";
373 pinctrl-names = "default";
374 pinctrl-0 = <&uart2m1_xfer>;
375 reg-io-width = <4>;
376 reg-shift = <2>;
381 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
384 #address-cells = <1>;
385 #size-cells = <0>;
387 clock-names = "i2c", "pclk";
388 pinctrl-names = "default";
389 pinctrl-0 = <&i2c0_xfer>;
394 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
397 #address-cells = <1>;
398 #size-cells = <0>;
400 clock-names = "i2c", "pclk";
401 pinctrl-names = "default";
402 pinctrl-0 = <&i2c1_xfer>;
407 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
410 #address-cells = <1>;
411 #size-cells = <0>;
413 clock-names = "i2c", "pclk";
414 pinctrl-names = "default";
415 pinctrl-0 = <&i2c2_xfer>;
420 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
423 #address-cells = <1>;
424 #size-cells = <0>;
426 clock-names = "i2c", "pclk";
427 pinctrl-names = "default";
428 pinctrl-0 = <&i2c3_xfer>;
433 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
436 #address-cells = <1>;
437 #size-cells = <0>;
439 clock-names = "spiclk", "apb_pclk";
441 dma-names = "tx", "rx";
442 pinctrl-names = "default";
443 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
448 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
455 compatible = "rockchip,rk3328-pwm";
458 clock-names = "pwm", "pclk";
459 pinctrl-names = "default";
460 pinctrl-0 = <&pwm0_pin>;
461 #pwm-cells = <3>;
466 compatible = "rockchip,rk3328-pwm";
469 clock-names = "pwm", "pclk";
470 pinctrl-names = "default";
471 pinctrl-0 = <&pwm1_pin>;
472 #pwm-cells = <3>;
477 compatible = "rockchip,rk3328-pwm";
480 clock-names = "pwm", "pclk";
481 pinctrl-names = "default";
482 pinctrl-0 = <&pwm2_pin>;
483 #pwm-cells = <3>;
488 compatible = "rockchip,rk3328-pwm";
492 clock-names = "pwm", "pclk";
493 pinctrl-names = "default";
494 pinctrl-0 = <&pwmir_pin>;
495 #pwm-cells = <3>;
499 dmac: dma-controller@ff1f0000 {
504 arm,pl330-periph-burst;
506 clock-names = "apb_pclk";
507 #dma-cells = <1>;
510 thermal-zones {
511 soc_thermal: soc-thermal {
512 polling-delay-passive = <20>;
513 polling-delay = <1000>;
514 sustainable-power = <1000>;
516 thermal-sensors = <&tsadc 0>;
519 threshold: trip-point0 {
524 target: trip-point1 {
529 soc_crit: soc-crit {
536 cooling-maps {
539 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
551 compatible = "rockchip,rk3328-tsadc";
554 assigned-clocks = <&cru SCLK_TSADC>;
555 assigned-clock-rates = <50000>;
557 clock-names = "tsadc", "apb_pclk";
558 pinctrl-names = "init", "default", "sleep";
559 pinctrl-0 = <&otp_pin>;
560 pinctrl-1 = <&otp_out>;
561 pinctrl-2 = <&otp_pin>;
563 reset-names = "tsadc-apb";
565 rockchip,hw-tshut-temp = <100000>;
566 #thermal-sensor-cells = <1>;
571 compatible = "rockchip,rk3328-efuse";
573 #address-cells = <1>;
574 #size-cells = <1>;
576 clock-names = "pclk_efuse";
577 rockchip,efuse-size = <0x20>;
583 cpu_leakage: cpu-leakage@17 {
586 logic_leakage: logic-leakage@19 {
589 efuse_cpu_version: cpu-version@1a {
596 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
599 #io-channel-cells = <1>;
601 clock-names = "saradc", "apb_pclk";
603 reset-names = "saradc-apb";
608 compatible = "rockchip,rk3328-mali", "arm,mali-450";
617 interrupt-names = "gp",
625 clock-names = "bus", "core";
634 clock-names = "aclk", "iface";
635 #iommu-cells = <0>;
644 clock-names = "aclk", "iface";
645 #iommu-cells = <0>;
649 vpu: video-codec@ff350000 {
650 compatible = "rockchip,rk3328-vpu";
653 interrupt-names = "vdpu";
655 clock-names = "aclk", "hclk";
657 power-domains = <&power RK3328_PD_VPU>;
665 clock-names = "aclk", "iface";
666 #iommu-cells = <0>;
667 power-domains = <&power RK3328_PD_VPU>;
670 vdec: video-codec@ff360000 {
671 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
676 clock-names = "axi", "ahb", "cabac", "core";
677 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
679 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
681 power-domains = <&power RK3328_PD_VIDEO>;
689 clock-names = "aclk", "iface";
690 #iommu-cells = <0>;
691 power-domains = <&power RK3328_PD_VIDEO>;
695 compatible = "rockchip,rk3328-vop";
699 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
701 reset-names = "axi", "ahb", "dclk";
706 #address-cells = <1>;
707 #size-cells = <0>;
711 remote-endpoint = <&hdmi_in_vop>;
721 clock-names = "aclk", "iface";
722 #iommu-cells = <0>;
727 compatible = "rockchip,rk3328-dw-hdmi";
729 reg-io-width = <4>;
734 clock-names = "iahb",
738 phy-names = "hdmi";
739 pinctrl-names = "default";
740 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
742 #sound-dai-cells = <0>;
746 #address-cells = <1>;
747 #size-cells = <0>;
753 remote-endpoint = <&vop_out_hdmi>;
764 compatible = "rockchip,rk3328-codec";
767 clock-names = "pclk", "mclk";
769 #sound-dai-cells = <0>;
774 compatible = "rockchip,rk3328-hdmi-phy";
778 clock-names = "sysclk", "refoclk", "refpclk";
779 clock-output-names = "hdmi_phy";
780 #clock-cells = <0>;
781 nvmem-cells = <&efuse_cpu_version>;
782 nvmem-cell-names = "cpu-version";
783 #phy-cells = <0>;
787 cru: clock-controller@ff440000 {
788 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
791 #clock-cells = <1>;
792 #reset-cells = <1>;
793 assigned-clocks =
797 * We need set cpll child clk div first,
816 assigned-clock-parents =
820 assigned-clock-rates =
840 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
841 "simple-mfd";
843 #address-cells = <1>;
844 #size-cells = <1>;
847 compatible = "rockchip,rk3328-usb2phy";
850 clock-names = "phyclk";
851 clock-output-names = "usb480m_phy";
852 #clock-cells = <0>;
853 assigned-clocks = <&cru USB480M>;
854 assigned-clock-parents = <&u2phy>;
857 u2phy_otg: otg-port {
858 #phy-cells = <0>;
862 interrupt-names = "otg-bvalid", "otg-id",
867 u2phy_host: host-port {
868 #phy-cells = <0>;
870 interrupt-names = "linestate";
877 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
882 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
883 fifo-depth = <0x100>;
884 max-frequency = <150000000>;
889 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
894 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
895 fifo-depth = <0x100>;
896 max-frequency = <150000000>;
901 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
906 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
907 fifo-depth = <0x100>;
908 max-frequency = <150000000>;
913 compatible = "rockchip,rk3328-gmac";
916 interrupt-names = "macirq";
921 clock-names = "stmmaceth", "mac_clk_rx",
926 reset-names = "stmmaceth";
933 compatible = "rockchip,rk3328-gmac";
937 interrupt-names = "macirq";
942 clock-names = "stmmaceth", "mac_clk_rx",
947 reset-names = "stmmaceth";
948 phy-mode = "rmii";
949 phy-handle = <&phy>;
955 compatible = "snps,dwmac-mdio";
956 #address-cells = <1>;
957 #size-cells = <0>;
959 phy: ethernet-phy@0 {
960 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
964 pinctrl-names = "default";
965 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
966 phy-is-integrated;
972 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
977 clock-names = "otg";
979 g-np-tx-fifo-size = <16>;
980 g-rx-fifo-size = <280>;
981 g-tx-fifo-size = <256 128 128 64 32 16>;
983 phy-names = "usb2-phy";
988 compatible = "generic-ehci";
993 phy-names = "usb";
998 compatible = "generic-ohci";
1003 phy-names = "usb";
1008 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1013 clock-names = "ref_clk", "suspend_clk",
1017 snps,dis-del-phy-power-chg-quirk;
1019 snps,dis-tx-ipgap-linecheck-quirk;
1020 snps,dis-u2-freeclk-exists-quirk;
1026 gic: interrupt-controller@ff811000 {
1027 compatible = "arm,gic-400";
1028 #interrupt-cells = <3>;
1029 #address-cells = <0>;
1030 interrupt-controller;
1040 compatible = "rockchip,rk3328-crypto";
1045 clock-names = "hclk_master", "hclk_slave", "sclk";
1047 reset-names = "crypto-rst";
1051 compatible = "rockchip,rk3328-pinctrl";
1053 #address-cells = <2>;
1054 #size-cells = <2>;
1058 compatible = "rockchip,gpio-bank";
1063 gpio-controller;
1064 #gpio-cells = <2>;
1066 interrupt-controller;
1067 #interrupt-cells = <2>;
1071 compatible = "rockchip,gpio-bank";
1076 gpio-controller;
1077 #gpio-cells = <2>;
1079 interrupt-controller;
1080 #interrupt-cells = <2>;
1084 compatible = "rockchip,gpio-bank";
1089 gpio-controller;
1090 #gpio-cells = <2>;
1092 interrupt-controller;
1093 #interrupt-cells = <2>;
1097 compatible = "rockchip,gpio-bank";
1102 gpio-controller;
1103 #gpio-cells = <2>;
1105 interrupt-controller;
1106 #interrupt-cells = <2>;
1109 pcfg_pull_up: pcfg-pull-up {
1110 bias-pull-up;
1113 pcfg_pull_down: pcfg-pull-down {
1114 bias-pull-down;
1117 pcfg_pull_none: pcfg-pull-none {
1118 bias-disable;
1121 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1122 bias-disable;
1123 drive-strength = <2>;
1126 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1127 bias-pull-up;
1128 drive-strength = <2>;
1131 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1132 bias-pull-up;
1133 drive-strength = <4>;
1136 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1137 bias-disable;
1138 drive-strength = <4>;
1141 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1142 bias-pull-down;
1143 drive-strength = <4>;
1146 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1147 bias-disable;
1148 drive-strength = <8>;
1151 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1152 bias-pull-up;
1153 drive-strength = <8>;
1156 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1157 bias-disable;
1158 drive-strength = <12>;
1161 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1162 bias-pull-up;
1163 drive-strength = <12>;
1166 pcfg_output_high: pcfg-output-high {
1167 output-high;
1170 pcfg_output_low: pcfg-output-low {
1171 output-low;
1174 pcfg_input_high: pcfg-input-high {
1175 bias-pull-up;
1176 input-enable;
1179 pcfg_input: pcfg-input {
1180 input-enable;
1184 i2c0_xfer: i2c0-xfer {
1191 i2c1_xfer: i2c1-xfer {
1198 i2c2_xfer: i2c2-xfer {
1205 i2c3_xfer: i2c3-xfer {
1209 i2c3_pins: i2c3-pins {
1217 hdmii2c_xfer: hdmii2c-xfer {
1223 pdm-0 {
1224 pdmm0_clk: pdmm0-clk {
1228 pdmm0_fsync: pdmm0-fsync {
1232 pdmm0_sdi0: pdmm0-sdi0 {
1236 pdmm0_sdi1: pdmm0-sdi1 {
1240 pdmm0_sdi2: pdmm0-sdi2 {
1244 pdmm0_sdi3: pdmm0-sdi3 {
1248 pdmm0_clk_sleep: pdmm0-clk-sleep {
1253 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1258 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1263 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1268 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1273 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1280 otp_pin: otp-pin {
1284 otp_out: otp-out {
1290 uart0_xfer: uart0-xfer {
1295 uart0_cts: uart0-cts {
1299 uart0_rts: uart0-rts {
1303 uart0_rts_pin: uart0-rts-pin {
1309 uart1_xfer: uart1-xfer {
1314 uart1_cts: uart1-cts {
1318 uart1_rts: uart1-rts {
1322 uart1_rts_pin: uart1-rts-pin {
1327 uart2-0 {
1328 uart2m0_xfer: uart2m0-xfer {
1334 uart2-1 {
1335 uart2m1_xfer: uart2m1-xfer {
1341 spi0-0 {
1342 spi0m0_clk: spi0m0-clk {
1346 spi0m0_cs0: spi0m0-cs0 {
1350 spi0m0_tx: spi0m0-tx {
1354 spi0m0_rx: spi0m0-rx {
1358 spi0m0_cs1: spi0m0-cs1 {
1363 spi0-1 {
1364 spi0m1_clk: spi0m1-clk {
1368 spi0m1_cs0: spi0m1-cs0 {
1372 spi0m1_tx: spi0m1-tx {
1376 spi0m1_rx: spi0m1-rx {
1380 spi0m1_cs1: spi0m1-cs1 {
1385 spi0-2 {
1386 spi0m2_clk: spi0m2-clk {
1390 spi0m2_cs0: spi0m2-cs0 {
1394 spi0m2_tx: spi0m2-tx {
1398 spi0m2_rx: spi0m2-rx {
1404 i2s1_mclk: i2s1-mclk {
1408 i2s1_sclk: i2s1-sclk {
1412 i2s1_lrckrx: i2s1-lrckrx {
1416 i2s1_lrcktx: i2s1-lrcktx {
1420 i2s1_sdi: i2s1-sdi {
1424 i2s1_sdo: i2s1-sdo {
1428 i2s1_sdio1: i2s1-sdio1 {
1432 i2s1_sdio2: i2s1-sdio2 {
1436 i2s1_sdio3: i2s1-sdio3 {
1440 i2s1_sleep: i2s1-sleep {
1454 i2s2-0 {
1455 i2s2m0_mclk: i2s2m0-mclk {
1459 i2s2m0_sclk: i2s2m0-sclk {
1463 i2s2m0_lrckrx: i2s2m0-lrckrx {
1467 i2s2m0_lrcktx: i2s2m0-lrcktx {
1471 i2s2m0_sdi: i2s2m0-sdi {
1475 i2s2m0_sdo: i2s2m0-sdo {
1479 i2s2m0_sleep: i2s2m0-sleep {
1490 i2s2-1 {
1491 i2s2m1_mclk: i2s2m1-mclk {
1495 i2s2m1_sclk: i2s2m1-sclk {
1499 i2s2m1_lrckrx: i2sm1-lrckrx {
1503 i2s2m1_lrcktx: i2s2m1-lrcktx {
1507 i2s2m1_sdi: i2s2m1-sdi {
1511 i2s2m1_sdo: i2s2m1-sdo {
1515 i2s2m1_sleep: i2s2m1-sleep {
1525 spdif-0 {
1526 spdifm0_tx: spdifm0-tx {
1531 spdif-1 {
1532 spdifm1_tx: spdifm1-tx {
1537 spdif-2 {
1538 spdifm2_tx: spdifm2-tx {
1543 sdmmc0-0 {
1544 sdmmc0m0_pwren: sdmmc0m0-pwren {
1548 sdmmc0m0_pin: sdmmc0m0-pin {
1553 sdmmc0-1 {
1554 sdmmc0m1_pwren: sdmmc0m1-pwren {
1558 sdmmc0m1_pin: sdmmc0m1-pin {
1564 sdmmc0_clk: sdmmc0-clk {
1568 sdmmc0_cmd: sdmmc0-cmd {
1572 sdmmc0_dectn: sdmmc0-dectn {
1576 sdmmc0_wrprt: sdmmc0-wrprt {
1580 sdmmc0_bus1: sdmmc0-bus1 {
1584 sdmmc0_bus4: sdmmc0-bus4 {
1591 sdmmc0_pins: sdmmc0-pins {
1605 sdmmc0ext_clk: sdmmc0ext-clk {
1609 sdmmc0ext_cmd: sdmmc0ext-cmd {
1613 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1617 sdmmc0ext_dectn: sdmmc0ext-dectn {
1621 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1625 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1633 sdmmc0ext_pins: sdmmc0ext-pins {
1647 sdmmc1_clk: sdmmc1-clk {
1651 sdmmc1_cmd: sdmmc1-cmd {
1655 sdmmc1_pwren: sdmmc1-pwren {
1659 sdmmc1_wrprt: sdmmc1-wrprt {
1663 sdmmc1_dectn: sdmmc1-dectn {
1667 sdmmc1_bus1: sdmmc1-bus1 {
1671 sdmmc1_bus4: sdmmc1-bus4 {
1678 sdmmc1_pins: sdmmc1-pins {
1693 emmc_clk: emmc-clk {
1697 emmc_cmd: emmc-cmd {
1701 emmc_pwren: emmc-pwren {
1705 emmc_rstnout: emmc-rstnout {
1709 emmc_bus1: emmc-bus1 {
1713 emmc_bus4: emmc-bus4 {
1721 emmc_bus8: emmc-bus8 {
1735 pwm0_pin: pwm0-pin {
1741 pwm1_pin: pwm1-pin {
1747 pwm2_pin: pwm2-pin {
1753 pwmir_pin: pwmir-pin {
1758 gmac-1 {
1759 rgmiim1_pins: rgmiim1-pins {
1808 rmiim1_pins: rmiim1-pins {
1847 fephyled_speed10: fephyled-speed10 {
1851 fephyled_duplex: fephyled-duplex {
1855 fephyled_rxm1: fephyled-rxm1 {
1859 fephyled_txm1: fephyled-txm1 {
1863 fephyled_linkm1: fephyled-linkm1 {
1869 tsadc_int: tsadc-int {
1872 tsadc_pin: tsadc-pin {
1878 hdmi_cec: hdmi-cec {
1882 hdmi_hpd: hdmi-hpd {
1887 cif-0 {
1888 dvp_d2d9_m0:dvp-d2d9-m0 {
1917 cif-1 {
1918 dvp_d2d9_m1:dvp-d2d9-m1 {