Lines Matching +full:0 +full:xff500000
39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
77 reg = <0x0 0x3>;
90 arm,psci-suspend-param = <0x0010000>;
104 cpu0_opp_table: opp-table-0 {
144 #clock-cells = <0>;
162 #clock-cells = <0>;
169 reg = <0x0 0xff000000 0x0 0x08000>;
173 offset = <0x500>;
184 reg = <0x0 0xff008000 0x0 0x4000>;
190 reg = <0x100 0x10>;
196 #clock-cells = <0>;
205 #phy-cells = <0>;
212 #phy-cells = <0>;
220 reg = <0x0 0xff00b000 0x0 0x1000>;
227 reg = <0x0 0xff00c000 0x0 0x1000>;
234 reg = <0x0 0xff040000 0x0 0x1000>;
239 pinctrl-0 = <&i2c0_xfer>;
241 #size-cells = <0>;
247 reg = <0x0 0xff050000 0x0 0x1000>;
252 pinctrl-0 = <&i2c1_xfer>;
254 #size-cells = <0>;
260 reg = <0x0 0xff060000 0x0 0x1000>;
265 pinctrl-0 = <&i2c2_xfer>;
267 #size-cells = <0>;
273 reg = <0x0 0xff070000 0x0 0x1000>;
278 pinctrl-0 = <&i2c3m0_xfer>;
280 #size-cells = <0>;
286 reg = <0x0 0xff080000 0x0 0x100>;
294 reg = <0x0 0xff0a0000 0x0 0x100>;
301 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
307 reg = <0x0 0xff0b0000 0x0 0x100>;
314 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
320 reg = <0x0 0xff0c0000 0x0 0x100>;
327 pinctrl-0 = <&uart2m0_xfer>;
333 reg = <0x0 0xff0d0000 0x0 0x100>;
340 pinctrl-0 = <&uart3_xfer>;
346 reg = <0x0 0xff0e0000 0x0 0x100>;
353 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
359 reg = <0x0 0xff120000 0x0 0x1000>;
362 #size-cells = <0>;
365 dmas = <&dmac0 0>, <&dmac0 1>;
368 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
374 reg = <0x0 0xff130000 0x0 0x1000>;
377 #size-cells = <0>;
383 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
389 reg = <0x0 0xff140000 0x0 0x1000>;
392 #size-cells = <0>;
398 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
404 reg = <0x0 0xff160000 0x0 0x10>;
408 pinctrl-0 = <&pwm8_pin>;
415 reg = <0x0 0xff160010 0x0 0x10>;
419 pinctrl-0 = <&pwm9_pin>;
426 reg = <0x0 0xff160020 0x0 0x10>;
430 pinctrl-0 = <&pwm10_pin>;
437 reg = <0x0 0xff160030 0x0 0x10>;
441 pinctrl-0 = <&pwm11_pin>;
448 reg = <0x0 0xff170000 0x0 0x10>;
452 pinctrl-0 = <&pwm4_pin>;
459 reg = <0x0 0xff170010 0x0 0x10>;
463 pinctrl-0 = <&pwm5_pin>;
470 reg = <0x0 0xff170020 0x0 0x10>;
474 pinctrl-0 = <&pwm6_pin>;
481 reg = <0x0 0xff170030 0x0 0x10>;
485 pinctrl-0 = <&pwm7_pin>;
492 reg = <0x0 0xff180000 0x0 0x10>;
496 pinctrl-0 = <&pwm0_pin>;
503 reg = <0x0 0xff180010 0x0 0x10>;
507 pinctrl-0 = <&pwm1_pin>;
514 reg = <0x0 0xff180020 0x0 0x10>;
518 pinctrl-0 = <&pwm2_pin>;
525 reg = <0x0 0xff180030 0x0 0x10>;
529 pinctrl-0 = <&pwm3_pin>;
536 reg = <0x0 0xff1a0000 0x0 0x20>;
544 reg = <0x0 0xff1e0000 0x0 0x100>;
556 reg = <0x0 0xff2c0000 0x0 0x4000>;
557 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
567 reg = <0x0 0xff2d0000 0x0 0x4000>;
578 reg = <0x0 0xff350000 0x0 0x1000>;
587 pinctrl-0 = <&i2s_2ch_0_sclk
596 reg = <0x0 0xff360000 0x0 0x1000>;
609 reg = <0x0 0xff3a0000 0x0 0x1000>;
616 pinctrl-0 = <&spdif_out>;
623 reg = <0x0 0xff400000 0x0 0x40000>;
638 reg = <0x0 0xff440000 0x0 0x10000>;
648 reg = <0x0 0xff450000 0x0 0x10000>;
658 reg = <0x0 0xff480000 0x0 0x4000>;
664 fifo-depth = <0x100>;
667 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
673 reg = <0x0 0xff490000 0x0 0x4000>;
679 fifo-depth = <0x100>;
686 reg = <0x0 0xff4a0000 0x0 0x4000>;
692 fifo-depth = <0x100>;
695 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
702 reg = <0x0 0xff4b0000 0x0 0x4000>;
708 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
716 reg = <0x0 0xff4e0000 0x0 0x10000>;
729 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
738 reg = <0x0 0xff4c0000 0x0 0x4000>;
742 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
749 reg = <0x0 0xff500000 0x0 0x1000>;
761 reg = <0x0 0xff581000 0x0 0x1000>,
762 <0x0 0xff582000 0x0 0x2000>,
763 <0x0 0xff584000 0x0 0x2000>,
764 <0x0 0xff586000 0x0 0x2000>;
768 #address-cells = <0>;
773 reg = <0x0 0xfff80000 0x0 0x40000>;
774 ranges = <0 0x0 0xfff80000 0x40000>;
779 ddr-sram@0 {
780 reg = <0x0 0x8000>;
785 reg = <0x8000 0x38000>;
798 reg = <0x0 0xff220000 0x0 0x100>;
809 reg = <0x0 0xff230000 0x0 0x100>;
820 reg = <0x0 0xff240000 0x0 0x100>;
831 reg = <0x0 0xff250000 0x0 0x100>;
842 reg = <0x0 0xff260000 0x0 0x100>;
1126 <0 RK_PB3 1 &pcfg_pull_none_smt>,
1127 <0 RK_PB4 1 &pcfg_pull_none_smt>;
1142 <0 RK_PB7 2 &pcfg_pull_none_smt>,
1143 <0 RK_PC0 2 &pcfg_pull_none_smt>;
1164 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1169 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1174 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1179 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1184 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1191 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1196 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1201 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1206 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1211 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1216 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1221 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1226 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1231 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1236 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1241 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1246 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1251 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1450 <0 RK_PB5 1 &pcfg_pull_none>;
1455 <0 RK_PB5 1 &pcfg_pull_down>;
1462 <0 RK_PB6 1 &pcfg_pull_none>;
1467 <0 RK_PB6 1 &pcfg_pull_down>;
1474 <0 RK_PB7 1 &pcfg_pull_none>;
1479 <0 RK_PB7 1 &pcfg_pull_down>;
1486 <0 RK_PC0 1 &pcfg_pull_none>;
1491 <0 RK_PC0 1 &pcfg_pull_down>;
1498 <0 RK_PA1 2 &pcfg_pull_none>;
1503 <0 RK_PA1 2 &pcfg_pull_down>;
1510 <0 RK_PC1 2 &pcfg_pull_none>;
1515 <0 RK_PC1 2 &pcfg_pull_down>;
1522 <0 RK_PC2 2 &pcfg_pull_none>;
1527 <0 RK_PC2 2 &pcfg_pull_down>;
1594 <0 RK_PC3 1 &pcfg_pull_none>;
1611 <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1646 <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1651 <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1656 <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1676 <0 RK_PC2 1 &pcfg_pull_none>;
1683 <0 RK_PC1 1 &pcfg_pull_none>;
1778 <0 RK_PB2 0 &pcfg_pull_none>;
1783 <0 RK_PB2 1 &pcfg_pull_none>;
1806 <2 RK_PA3 0 &pcfg_pull_none>;
1855 <0 RK_PC2 3 &pcfg_pull_up>,
1856 <0 RK_PC1 3 &pcfg_pull_up>;
1879 <4 RK_PA7 0 &pcfg_pull_none>;