Lines Matching +full:rk3288 +full:- +full:mipi +full:- +full:dsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
39 #address-cells = <2>;
40 #size-cells = <0>;
44 compatible = "arm,cortex-a35";
46 enable-method = "psci";
48 #cooling-cells = <2>;
49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
50 dynamic-power-coefficient = <90>;
51 operating-points-v2 = <&cpu0_opp_table>;
56 compatible = "arm,cortex-a35";
58 enable-method = "psci";
60 #cooling-cells = <2>;
61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
62 dynamic-power-coefficient = <90>;
63 operating-points-v2 = <&cpu0_opp_table>;
68 compatible = "arm,cortex-a35";
70 enable-method = "psci";
72 #cooling-cells = <2>;
73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
74 dynamic-power-coefficient = <90>;
75 operating-points-v2 = <&cpu0_opp_table>;
80 compatible = "arm,cortex-a35";
82 enable-method = "psci";
84 #cooling-cells = <2>;
85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86 dynamic-power-coefficient = <90>;
87 operating-points-v2 = <&cpu0_opp_table>;
90 idle-states {
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
95 local-timer-stop;
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
102 CLUSTER_SLEEP: cluster-sleep {
103 compatible = "arm,idle-state";
104 local-timer-stop;
105 arm,psci-suspend-param = <0x1010000>;
106 entry-latency-us = <400>;
107 exit-latency-us = <500>;
108 min-residency-us = <2000>;
113 cpu0_opp_table: opp-table-0 {
114 compatible = "operating-points-v2";
115 opp-shared;
117 opp-600000000 {
118 opp-hz = /bits/ 64 <600000000>;
119 opp-microvolt = <950000 950000 1350000>;
120 clock-latency-ns = <40000>;
121 opp-suspend;
123 opp-816000000 {
124 opp-hz = /bits/ 64 <816000000>;
125 opp-microvolt = <1050000 1050000 1350000>;
126 clock-latency-ns = <40000>;
128 opp-1008000000 {
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1175000 1175000 1350000>;
131 clock-latency-ns = <40000>;
133 opp-1200000000 {
134 opp-hz = /bits/ 64 <1200000000>;
135 opp-microvolt = <1300000 1300000 1350000>;
136 clock-latency-ns = <40000>;
138 opp-1296000000 {
139 opp-hz = /bits/ 64 <1296000000>;
140 opp-microvolt = <1350000 1350000 1350000>;
141 clock-latency-ns = <40000>;
145 arm-pmu {
146 compatible = "arm,cortex-a35-pmu";
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
154 display_subsystem: display-subsystem {
155 compatible = "rockchip,display-subsystem";
160 gmac_clkin: external-gmac-clock {
161 compatible = "fixed-clock";
162 clock-frequency = <50000000>;
163 clock-output-names = "gmac_clkin";
164 #clock-cells = <0>;
168 compatible = "arm,psci-1.0";
173 compatible = "arm,armv8-timer";
180 thermal_zones: thermal-zones {
181 soc_thermal: soc-thermal {
182 polling-delay-passive = <20>;
183 polling-delay = <1000>;
184 sustainable-power = <750>;
185 thermal-sensors = <&tsadc 0>;
188 threshold: trip-point-0 {
194 target: trip-point-1 {
200 soc_crit: soc-crit {
207 cooling-maps {
210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
216 gpu_thermal: gpu-thermal {
217 polling-delay-passive = <100>; /* milliseconds */
218 polling-delay = <1000>; /* milliseconds */
219 thermal-sensors = <&tsadc 1>;
222 gpu_threshold: gpu-threshold {
228 gpu_target: gpu-target {
234 gpu_crit: gpu-crit {
241 cooling-maps {
244 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
251 compatible = "fixed-clock";
252 #clock-cells = <0>;
253 clock-frequency = <24000000>;
254 clock-output-names = "xin24m";
257 pmu: power-management@ff000000 {
258 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
261 power: power-controller {
262 compatible = "rockchip,px30-power-controller";
263 #power-domain-cells = <1>;
264 #address-cells = <1>;
265 #size-cells = <0>;
268 power-domain@PX30_PD_USB {
274 #power-domain-cells = <0>;
276 power-domain@PX30_PD_SDCARD {
281 #power-domain-cells = <0>;
283 power-domain@PX30_PD_GMAC {
290 #power-domain-cells = <0>;
292 power-domain@PX30_PD_MMC_NAND {
304 #power-domain-cells = <0>;
306 power-domain@PX30_PD_VPU {
312 #power-domain-cells = <0>;
314 power-domain@PX30_PD_VO {
329 #power-domain-cells = <0>;
331 power-domain@PX30_PD_VI {
341 #power-domain-cells = <0>;
343 power-domain@PX30_PD_GPU {
347 #power-domain-cells = <0>;
353 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
355 #address-cells = <1>;
356 #size-cells = <1>;
358 pmu_io_domains: io-domains {
359 compatible = "rockchip,px30-pmu-io-voltage-domain";
363 reboot-mode {
364 compatible = "syscon-reboot-mode";
366 mode-bootloader = <BOOT_BL_DOWNLOAD>;
367 mode-fastboot = <BOOT_FASTBOOT>;
368 mode-loader = <BOOT_BL_DOWNLOAD>;
369 mode-normal = <BOOT_NORMAL>;
370 mode-recovery = <BOOT_RECOVERY>;
375 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
379 clock-names = "baudclk", "apb_pclk";
381 dma-names = "tx", "rx";
382 reg-shift = <2>;
383 reg-io-width = <4>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
390 compatible = "rockchip,px30-i2s-tdm";
394 clock-names = "mclk_tx", "mclk_rx", "hclk";
396 dma-names = "tx", "rx";
399 reset-names = "tx-m", "rx-m";
400 pinctrl-names = "default";
401 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
407 #sound-dai-cells = <0>;
412 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
416 clock-names = "i2s_clk", "i2s_hclk";
418 dma-names = "tx", "rx";
419 pinctrl-names = "default";
420 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
422 #sound-dai-cells = <0>;
427 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
431 clock-names = "i2s_clk", "i2s_hclk";
433 dma-names = "tx", "rx";
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
437 #sound-dai-cells = <0>;
441 gic: interrupt-controller@ff131000 {
442 compatible = "arm,gic-400";
443 #interrupt-cells = <3>;
444 #address-cells = <0>;
445 interrupt-controller;
455 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
457 #address-cells = <1>;
458 #size-cells = <1>;
460 io_domains: io-domains {
461 compatible = "rockchip,px30-io-voltage-domain";
466 compatible = "rockchip,px30-lvds";
468 phy-names = "dphy";
474 #address-cells = <1>;
475 #size-cells = <0>;
479 #address-cells = <1>;
480 #size-cells = <0>;
484 remote-endpoint = <&vopb_out_lvds>;
489 remote-endpoint = <&vopl_out_lvds>;
501 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
505 clock-names = "baudclk", "apb_pclk";
507 dma-names = "tx", "rx";
508 reg-shift = <2>;
509 reg-io-width = <4>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
516 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
520 clock-names = "baudclk", "apb_pclk";
522 dma-names = "tx", "rx";
523 reg-shift = <2>;
524 reg-io-width = <4>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&uart2m0_xfer>;
531 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
535 clock-names = "baudclk", "apb_pclk";
537 dma-names = "tx", "rx";
538 reg-shift = <2>;
539 reg-io-width = <4>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
546 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
550 clock-names = "baudclk", "apb_pclk";
552 dma-names = "tx", "rx";
553 reg-shift = <2>;
554 reg-io-width = <4>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
561 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
565 clock-names = "baudclk", "apb_pclk";
567 dma-names = "tx", "rx";
568 reg-shift = <2>;
569 reg-io-width = <4>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
576 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
579 clock-names = "i2c", "pclk";
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2c0_xfer>;
583 #address-cells = <1>;
584 #size-cells = <0>;
589 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
592 clock-names = "i2c", "pclk";
594 pinctrl-names = "default";
595 pinctrl-0 = <&i2c1_xfer>;
596 #address-cells = <1>;
597 #size-cells = <0>;
602 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
605 clock-names = "i2c", "pclk";
607 pinctrl-names = "default";
608 pinctrl-0 = <&i2c2_xfer>;
609 #address-cells = <1>;
610 #size-cells = <0>;
615 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
618 clock-names = "i2c", "pclk";
620 pinctrl-names = "default";
621 pinctrl-0 = <&i2c3_xfer>;
622 #address-cells = <1>;
623 #size-cells = <0>;
628 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
632 clock-names = "spiclk", "apb_pclk";
634 dma-names = "tx", "rx";
635 num-cs = <2>;
636 pinctrl-names = "default";
637 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
638 #address-cells = <1>;
639 #size-cells = <0>;
644 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
648 clock-names = "spiclk", "apb_pclk";
650 dma-names = "tx", "rx";
651 num-cs = <2>;
652 pinctrl-names = "default";
653 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
654 #address-cells = <1>;
655 #size-cells = <0>;
660 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
668 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
671 clock-names = "pwm", "pclk";
672 pinctrl-names = "default";
673 pinctrl-0 = <&pwm0_pin>;
674 #pwm-cells = <3>;
679 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
682 clock-names = "pwm", "pclk";
683 pinctrl-names = "default";
684 pinctrl-0 = <&pwm1_pin>;
685 #pwm-cells = <3>;
690 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
693 clock-names = "pwm", "pclk";
694 pinctrl-names = "default";
695 pinctrl-0 = <&pwm2_pin>;
696 #pwm-cells = <3>;
701 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
704 clock-names = "pwm", "pclk";
705 pinctrl-names = "default";
706 pinctrl-0 = <&pwm3_pin>;
707 #pwm-cells = <3>;
712 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
715 clock-names = "pwm", "pclk";
716 pinctrl-names = "default";
717 pinctrl-0 = <&pwm4_pin>;
718 #pwm-cells = <3>;
723 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
726 clock-names = "pwm", "pclk";
727 pinctrl-names = "default";
728 pinctrl-0 = <&pwm5_pin>;
729 #pwm-cells = <3>;
734 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
737 clock-names = "pwm", "pclk";
738 pinctrl-names = "default";
739 pinctrl-0 = <&pwm6_pin>;
740 #pwm-cells = <3>;
745 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
748 clock-names = "pwm", "pclk";
749 pinctrl-names = "default";
750 pinctrl-0 = <&pwm7_pin>;
751 #pwm-cells = <3>;
756 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
760 clock-names = "pclk", "timer";
763 dmac: dma-controller@ff240000 {
768 arm,pl330-periph-burst;
770 clock-names = "apb_pclk";
771 #dma-cells = <1>;
775 compatible = "rockchip,px30-tsadc";
778 assigned-clocks = <&cru SCLK_TSADC>;
779 assigned-clock-rates = <50000>;
781 clock-names = "tsadc", "apb_pclk";
783 reset-names = "tsadc-apb";
785 rockchip,hw-tshut-temp = <120000>;
786 pinctrl-names = "init", "default", "sleep";
787 pinctrl-0 = <&tsadc_otp_pin>;
788 pinctrl-1 = <&tsadc_otp_out>;
789 pinctrl-2 = <&tsadc_otp_pin>;
790 #thermal-sensor-cells = <1>;
795 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
798 #io-channel-cells = <1>;
800 clock-names = "saradc", "apb_pclk";
802 reset-names = "saradc-apb";
807 compatible = "rockchip,px30-otp";
811 clock-names = "otp", "apb_pclk", "phy";
813 reset-names = "phy";
814 #address-cells = <1>;
815 #size-cells = <1>;
821 cpu_leakage: cpu-leakage@17 {
830 cru: clock-controller@ff2b0000 {
831 compatible = "rockchip,px30-cru";
834 clock-names = "xin24m", "gpll";
836 #clock-cells = <1>;
837 #reset-cells = <1>;
839 assigned-clocks = <&cru PLL_NPLL>,
844 assigned-clock-rates = <1188000000>,
850 pmucru: clock-controller@ff2bc000 {
851 compatible = "rockchip,px30-pmucru";
854 clock-names = "xin24m";
856 #clock-cells = <1>;
857 #reset-cells = <1>;
859 assigned-clocks =
862 assigned-clock-rates =
868 compatible = "rockchip,px30-usb2phy-grf", "syscon",
869 "simple-mfd";
871 #address-cells = <1>;
872 #size-cells = <1>;
875 compatible = "rockchip,px30-usb2phy";
878 clock-names = "phyclk";
879 #clock-cells = <0>;
880 assigned-clocks = <&cru USB480M>;
881 assigned-clock-parents = <&u2phy>;
882 clock-output-names = "usb480m_phy";
885 u2phy_host: host-port {
886 #phy-cells = <0>;
888 interrupt-names = "linestate";
892 u2phy_otg: otg-port {
893 #phy-cells = <0>;
897 interrupt-names = "otg-bvalid", "otg-id",
905 compatible = "rockchip,px30-dsi-dphy";
908 clock-names = "ref", "pclk";
910 reset-names = "apb";
911 #phy-cells = <0>;
912 power-domains = <&power PX30_PD_VO>;
917 compatible = "rockchip,px30-csi-dphy";
920 clock-names = "pclk";
921 #phy-cells = <0>;
922 power-domains = <&power PX30_PD_VI>;
924 reset-names = "apb";
930 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
935 clock-names = "otg";
937 g-np-tx-fifo-size = <16>;
938 g-rx-fifo-size = <280>;
939 g-tx-fifo-size = <256 128 128 64 32 16>;
941 phy-names = "usb2-phy";
942 power-domains = <&power PX30_PD_USB>;
947 compatible = "generic-ehci";
952 phy-names = "usb";
953 power-domains = <&power PX30_PD_USB>;
958 compatible = "generic-ohci";
963 phy-names = "usb";
964 power-domains = <&power PX30_PD_USB>;
969 compatible = "rockchip,px30-gmac";
972 interrupt-names = "macirq";
977 clock-names = "stmmaceth", "mac_clk_rx",
982 phy-mode = "rmii";
983 pinctrl-names = "default";
984 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
985 power-domains = <&power PX30_PD_GMAC>;
987 reset-names = "stmmaceth";
992 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
997 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
998 bus-width = <4>;
999 fifo-depth = <0x100>;
1000 max-frequency = <150000000>;
1001 pinctrl-names = "default";
1002 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1003 power-domains = <&power PX30_PD_SDCARD>;
1008 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1013 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1014 bus-width = <4>;
1015 fifo-depth = <0x100>;
1016 max-frequency = <150000000>;
1017 pinctrl-names = "default";
1018 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1019 power-domains = <&power PX30_PD_MMC_NAND>;
1024 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1029 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1030 bus-width = <8>;
1031 fifo-depth = <0x100>;
1032 max-frequency = <150000000>;
1033 pinctrl-names = "default";
1034 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1035 power-domains = <&power PX30_PD_MMC_NAND>;
1044 clock-names = "clk_sfc", "hclk_sfc";
1045 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1046 pinctrl-names = "default";
1047 power-domains = <&power PX30_PD_MMC_NAND>;
1051 nfc: nand-controller@ff3b0000 {
1052 compatible = "rockchip,px30-nfc";
1056 clock-names = "ahb", "nfc";
1057 assigned-clocks = <&cru SCLK_NANDC>;
1058 assigned-clock-rates = <150000000>;
1059 pinctrl-names = "default";
1060 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1062 power-domains = <&power PX30_PD_MMC_NAND>;
1066 gpu_opp_table: opp-table-1 {
1067 compatible = "operating-points-v2";
1069 opp-200000000 {
1070 opp-hz = /bits/ 64 <200000000>;
1071 opp-microvolt = <950000>;
1073 opp-300000000 {
1074 opp-hz = /bits/ 64 <300000000>;
1075 opp-microvolt = <975000>;
1077 opp-400000000 {
1078 opp-hz = /bits/ 64 <400000000>;
1079 opp-microvolt = <1050000>;
1081 opp-480000000 {
1082 opp-hz = /bits/ 64 <480000000>;
1083 opp-microvolt = <1125000>;
1088 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1093 interrupt-names = "job", "mmu", "gpu";
1095 #cooling-cells = <2>;
1096 power-domains = <&power PX30_PD_GPU>;
1097 operating-points-v2 = <&gpu_opp_table>;
1101 vpu: video-codec@ff442000 {
1102 compatible = "rockchip,px30-vpu";
1106 interrupt-names = "vepu", "vdpu";
1108 clock-names = "aclk", "hclk";
1110 power-domains = <&power PX30_PD_VPU>;
1118 clock-names = "aclk", "iface";
1119 #iommu-cells = <0>;
1120 power-domains = <&power PX30_PD_VPU>;
1123 dsi: dsi@ff450000 { label
1124 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
1128 clock-names = "pclk";
1130 phy-names = "dphy";
1131 power-domains = <&power PX30_PD_VO>;
1133 reset-names = "apb";
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1140 #address-cells = <1>;
1141 #size-cells = <0>;
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1150 remote-endpoint = <&vopb_out_dsi>;
1155 remote-endpoint = <&vopl_out_dsi>;
1166 compatible = "rockchip,px30-vop-big";
1171 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1173 reset-names = "axi", "ahb", "dclk";
1175 power-domains = <&power PX30_PD_VO>;
1179 #address-cells = <1>;
1180 #size-cells = <0>;
1184 remote-endpoint = <&dsi_in_vopb>;
1189 remote-endpoint = <&lvds_vopb_in>;
1199 clock-names = "aclk", "iface";
1200 power-domains = <&power PX30_PD_VO>;
1201 #iommu-cells = <0>;
1206 compatible = "rockchip,px30-vop-lit";
1211 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1213 reset-names = "axi", "ahb", "dclk";
1215 power-domains = <&power PX30_PD_VO>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1224 remote-endpoint = <&dsi_in_vopl>;
1229 remote-endpoint = <&lvds_vopl_in>;
1239 clock-names = "aclk", "iface";
1240 power-domains = <&power PX30_PD_VO>;
1241 #iommu-cells = <0>;
1246 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1251 interrupt-names = "isp", "mi", "mipi";
1256 clock-names = "isp", "aclk", "hclk", "pclk";
1259 phy-names = "dphy";
1260 power-domains = <&power PX30_PD_VI>;
1264 #address-cells = <1>;
1265 #size-cells = <0>;
1269 #address-cells = <1>;
1270 #size-cells = <0>;
1280 clock-names = "aclk", "iface";
1281 power-domains = <&power PX30_PD_VI>;
1282 rockchip,disable-mmu-reset;
1283 #iommu-cells = <0>;
1287 compatible = "rockchip,px30-qos", "syscon";
1292 compatible = "rockchip,px30-qos", "syscon";
1297 compatible = "rockchip,px30-qos", "syscon";
1302 compatible = "rockchip,px30-qos", "syscon";
1307 compatible = "rockchip,px30-qos", "syscon";
1312 compatible = "rockchip,px30-qos", "syscon";
1317 compatible = "rockchip,px30-qos", "syscon";
1322 compatible = "rockchip,px30-qos", "syscon";
1327 compatible = "rockchip,px30-qos", "syscon";
1332 compatible = "rockchip,px30-qos", "syscon";
1337 compatible = "rockchip,px30-qos", "syscon";
1342 compatible = "rockchip,px30-qos", "syscon";
1347 compatible = "rockchip,px30-qos", "syscon";
1352 compatible = "rockchip,px30-qos", "syscon";
1357 compatible = "rockchip,px30-qos", "syscon";
1362 compatible = "rockchip,px30-qos", "syscon";
1367 compatible = "rockchip,px30-qos", "syscon";
1372 compatible = "rockchip,px30-qos", "syscon";
1377 compatible = "rockchip,px30-qos", "syscon";
1382 compatible = "rockchip,px30-qos", "syscon";
1387 compatible = "rockchip,px30-pinctrl";
1390 #address-cells = <2>;
1391 #size-cells = <2>;
1395 compatible = "rockchip,gpio-bank";
1399 gpio-controller;
1400 #gpio-cells = <2>;
1402 interrupt-controller;
1403 #interrupt-cells = <2>;
1407 compatible = "rockchip,gpio-bank";
1411 gpio-controller;
1412 #gpio-cells = <2>;
1414 interrupt-controller;
1415 #interrupt-cells = <2>;
1419 compatible = "rockchip,gpio-bank";
1423 gpio-controller;
1424 #gpio-cells = <2>;
1426 interrupt-controller;
1427 #interrupt-cells = <2>;
1431 compatible = "rockchip,gpio-bank";
1435 gpio-controller;
1436 #gpio-cells = <2>;
1438 interrupt-controller;
1439 #interrupt-cells = <2>;
1442 pcfg_pull_up: pcfg-pull-up {
1443 bias-pull-up;
1446 pcfg_pull_down: pcfg-pull-down {
1447 bias-pull-down;
1450 pcfg_pull_none: pcfg-pull-none {
1451 bias-disable;
1454 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1455 bias-disable;
1456 drive-strength = <2>;
1459 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1460 bias-pull-up;
1461 drive-strength = <2>;
1464 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1465 bias-pull-up;
1466 drive-strength = <4>;
1469 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1470 bias-disable;
1471 drive-strength = <4>;
1474 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1475 bias-pull-down;
1476 drive-strength = <4>;
1479 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1480 bias-disable;
1481 drive-strength = <8>;
1484 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1485 bias-pull-up;
1486 drive-strength = <8>;
1489 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1490 bias-disable;
1491 drive-strength = <12>;
1494 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1495 bias-pull-up;
1496 drive-strength = <12>;
1499 pcfg_pull_none_smt: pcfg-pull-none-smt {
1500 bias-disable;
1501 input-schmitt-enable;
1504 pcfg_output_high: pcfg-output-high {
1505 output-high;
1508 pcfg_output_low: pcfg-output-low {
1509 output-low;
1512 pcfg_input_high: pcfg-input-high {
1513 bias-pull-up;
1514 input-enable;
1517 pcfg_input: pcfg-input {
1518 input-enable;
1522 i2c0_xfer: i2c0-xfer {
1530 i2c1_xfer: i2c1-xfer {
1538 i2c2_xfer: i2c2-xfer {
1546 i2c3_xfer: i2c3-xfer {
1554 tsadc_otp_pin: tsadc-otp-pin {
1559 tsadc_otp_out: tsadc-otp-out {
1566 uart0_xfer: uart0-xfer {
1572 uart0_cts: uart0-cts {
1577 uart0_rts: uart0-rts {
1584 uart1_xfer: uart1-xfer {
1590 uart1_cts: uart1-cts {
1595 uart1_rts: uart1-rts {
1601 uart2-m0 {
1602 uart2m0_xfer: uart2m0-xfer {
1609 uart2-m1 {
1610 uart2m1_xfer: uart2m1-xfer {
1617 uart3-m0 {
1618 uart3m0_xfer: uart3m0-xfer {
1624 uart3m0_cts: uart3m0-cts {
1629 uart3m0_rts: uart3m0-rts {
1635 uart3-m1 {
1636 uart3m1_xfer: uart3m1-xfer {
1642 uart3m1_cts: uart3m1-cts {
1647 uart3m1_rts: uart3m1-rts {
1654 uart4_xfer: uart4-xfer {
1660 uart4_cts: uart4-cts {
1665 uart4_rts: uart4-rts {
1672 uart5_xfer: uart5-xfer {
1678 uart5_cts: uart5-cts {
1683 uart5_rts: uart5-rts {
1690 spi0_clk: spi0-clk {
1695 spi0_csn: spi0-csn {
1700 spi0_miso: spi0-miso {
1705 spi0_mosi: spi0-mosi {
1710 spi0_clk_hs: spi0-clk-hs {
1715 spi0_miso_hs: spi0-miso-hs {
1720 spi0_mosi_hs: spi0-mosi-hs {
1727 spi1_clk: spi1-clk {
1732 spi1_csn0: spi1-csn0 {
1737 spi1_csn1: spi1-csn1 {
1742 spi1_miso: spi1-miso {
1747 spi1_mosi: spi1-mosi {
1752 spi1_clk_hs: spi1-clk-hs {
1757 spi1_miso_hs: spi1-miso-hs {
1762 spi1_mosi_hs: spi1-mosi-hs {
1769 pdm_clk0m0: pdm-clk0m0 {
1774 pdm_clk0m1: pdm-clk0m1 {
1779 pdm_clk1: pdm-clk1 {
1784 pdm_sdi0m0: pdm-sdi0m0 {
1789 pdm_sdi0m1: pdm-sdi0m1 {
1794 pdm_sdi1: pdm-sdi1 {
1799 pdm_sdi2: pdm-sdi2 {
1804 pdm_sdi3: pdm-sdi3 {
1809 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1814 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1819 pdm_clk1_sleep: pdm-clk1-sleep {
1824 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1829 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1834 pdm_sdi1_sleep: pdm-sdi1-sleep {
1839 pdm_sdi2_sleep: pdm-sdi2-sleep {
1844 pdm_sdi3_sleep: pdm-sdi3-sleep {
1851 i2s0_8ch_mclk: i2s0-8ch-mclk {
1856 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1861 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1866 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1871 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1876 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1881 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1886 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1891 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1896 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1901 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1906 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1911 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1918 i2s1_2ch_mclk: i2s1-2ch-mclk {
1923 i2s1_2ch_sclk: i2s1-2ch-sclk {
1928 i2s1_2ch_lrck: i2s1-2ch-lrck {
1933 i2s1_2ch_sdi: i2s1-2ch-sdi {
1938 i2s1_2ch_sdo: i2s1-2ch-sdo {
1945 i2s2_2ch_mclk: i2s2-2ch-mclk {
1950 i2s2_2ch_sclk: i2s2-2ch-sclk {
1955 i2s2_2ch_lrck: i2s2-2ch-lrck {
1960 i2s2_2ch_sdi: i2s2-2ch-sdi {
1965 i2s2_2ch_sdo: i2s2-2ch-sdo {
1972 sdmmc_clk: sdmmc-clk {
1977 sdmmc_cmd: sdmmc-cmd {
1982 sdmmc_det: sdmmc-det {
1987 sdmmc_bus1: sdmmc-bus1 {
1992 sdmmc_bus4: sdmmc-bus4 {
2002 sdio_clk: sdio-clk {
2007 sdio_cmd: sdio-cmd {
2012 sdio_bus4: sdio-bus4 {
2022 emmc_clk: emmc-clk {
2027 emmc_cmd: emmc-cmd {
2032 emmc_rstnout: emmc-rstnout {
2037 emmc_bus1: emmc-bus1 {
2042 emmc_bus4: emmc-bus4 {
2050 emmc_bus8: emmc-bus8 {
2064 flash_cs0: flash-cs0 {
2069 flash_rdy: flash-rdy {
2074 flash_dqs: flash-dqs {
2079 flash_ale: flash-ale {
2084 flash_cle: flash-cle {
2089 flash_wrn: flash-wrn {
2094 flash_csl: flash-csl {
2099 flash_rdn: flash-rdn {
2104 flash_bus8: flash-bus8 {
2118 sfc_bus4: sfc-bus4 {
2126 sfc_bus2: sfc-bus2 {
2132 sfc_cs0: sfc-cs0 {
2137 sfc_clk: sfc-clk {
2144 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2149 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2154 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2159 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2164 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2192 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2214 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2234 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2255 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2270 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2285 pwm0_pin: pwm0-pin {
2292 pwm1_pin: pwm1-pin {
2299 pwm2_pin: pwm2-pin {
2306 pwm3_pin: pwm3-pin {
2313 pwm4_pin: pwm4-pin {
2320 pwm5_pin: pwm5-pin {
2327 pwm6_pin: pwm6-pin {
2334 pwm7_pin: pwm7-pin {
2341 rmii_pins: rmii-pins {
2354 mac_refclk_12ma: mac-refclk-12ma {
2359 mac_refclk: mac-refclk {
2365 cif-m0 {
2366 cif_clkout_m0: cif-clkout-m0 {
2371 dvp_d2d9_m0: dvp-d2d9-m0 {
2387 dvp_d0d1_m0: dvp-d0d1-m0 {
2393 dvp_d10d11_m0:d10-d11-m0 {
2400 cif-m1 {
2401 cif_clkout_m1: cif-clkout-m1 {
2406 dvp_d2d9_m1: dvp-d2d9-m1 {
2422 dvp_d0d1_m1: dvp-d0d1-m1 {
2428 dvp_d10d11_m1:d10-d11-m1 {
2436 isp_prelight: isp-prelight {