dts/renesas/r9a07g043u.dtsi

1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 		#address-cells = <1>;
17 		#size-cells = <0>;
20 			compatible = "arm,cortex-a55";
23 			#cooling-cells = <2>;
24 			next-level-cache = <&L3_CA55>;
25 			enable-method = "psci";
27 			operating-points-v2 = <&cluster0_opp>;
30 		L3_CA55: cache-controller-0 {
32 			cache-unified;
33 			cache-size = <0x40000>;
34 			cache-level = <3>;
39 		compatible = "arm,cortex-a55-pmu";
40 		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
44 		compatible = "arm,psci-1.0", "arm,psci-0.2";
49 		compatible = "arm,armv8-timer";
50 		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
55 		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
56 				  "hyp-virt";
61 	interrupt-parent = <&irqc>;
65 	interrupt-parent = <&gic>;
67 	irqc: interrupt-controller@110a0000 {  label
68 		compatible = "renesas,r9a07g043u-irqc",
69 			     "renesas,rzg2l-irqc";
71 		#interrupt-cells = <2>;
72 		#address-cells = <0>;
73 		interrupt-controller;
122 		interrupt-names = "nmi",
133 				  "bus-err", "ec7tie1-0", "ec7tie2-0",
134 				  "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
135 				  "ec7tiovf-1";
138 		clock-names = "clk", "pclk";
139 		power-domains = <&cpg>;
143 	gic: interrupt-controller@11900000 {
144 		compatible = "arm,gic-v3";
145 		#interrupt-cells = <3>;
146 		#address-cells = <0>;
147 		interrupt-controller;
159 	interrupt-names = "lpm_int", "ca55stbydone_int",