Lines Matching +full:0 +full:xe6500000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
27 #clock-cells = <0>;
28 clock-frequency = <0>;
31 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
88 a76_0: cpu@0 {
90 reg = <0>;
102 reg = <0x100>;
114 reg = <0x10000>;
126 reg = <0x10100>;
139 CPU_SLEEP_0: cpu-sleep-0 {
141 arm,psci-suspend-param = <0x0010000>;
149 L3_CA76_0: cache-controller-0 {
166 #clock-cells = <0>;
168 clock-frequency = <0>;
173 #clock-cells = <0>;
175 clock-frequency = <0>;
191 #clock-cells = <0>;
192 clock-frequency = <0>;
197 #clock-cells = <0>;
198 clock-frequency = <0>;
211 reg = <0 0xe6020000 0 0x0c>;
221 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
222 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
223 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
224 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>,
225 <0 0xe6068000 0 0x16c>;
231 reg = <0 0xe6050180 0 0x54>;
238 gpio-ranges = <&pfc 0 0 19>;
246 reg = <0 0xe6050980 0 0x54>;
253 gpio-ranges = <&pfc 0 32 29>;
261 reg = <0 0xe6058180 0 0x54>;
268 gpio-ranges = <&pfc 0 64 20>;
276 reg = <0 0xe6058980 0 0x54>;
283 gpio-ranges = <&pfc 0 96 30>;
291 reg = <0 0xe6060180 0 0x54>;
298 gpio-ranges = <&pfc 0 128 25>;
306 reg = <0 0xe6060980 0 0x54>;
313 gpio-ranges = <&pfc 0 160 21>;
321 reg = <0 0xe6061180 0 0x54>;
328 gpio-ranges = <&pfc 0 192 21>;
336 reg = <0 0xe6061980 0 0x54>;
343 gpio-ranges = <&pfc 0 224 21>;
351 reg = <0 0xe6068180 0 0x54>;
358 gpio-ranges = <&pfc 0 256 14>;
366 reg = <0 0xe60f0000 0 0x1004>;
379 reg = <0 0xe6130000 0 0x1004>;
398 reg = <0 0xe6140000 0 0x1004>;
417 reg = <0 0xe6148000 0 0x1004>;
435 reg = <0 0xe6150000 0 0x4000>;
439 #power-domain-cells = <0>;
445 reg = <0 0xe6160000 0 0x4000>;
450 reg = <0 0xe6180000 0 0x4000>;
456 reg = <0 0xe6198000 0 0x200>,
457 <0 0xe61a0000 0 0x200>,
458 <0 0xe61a8000 0 0x200>,
459 <0 0xe61b0000 0 0x200>;
470 reg = <0 0xe61c0000 0 0x200>;
471 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
484 reg = <0 0xe61e0000 0 0x30>;
497 reg = <0 0xe6fc0000 0 0x30>;
510 reg = <0 0xe6fd0000 0 0x30>;
523 reg = <0 0xe6fe0000 0 0x30>;
536 reg = <0 0xffc00000 0 0x30>;
550 reg = <0 0xe6500000 0 0x40>;
553 dmas = <&dmac0 0x91>, <&dmac0 0x90>,
554 <&dmac1 0x91>, <&dmac1 0x90>;
560 #size-cells = <0>;
567 reg = <0 0xe6508000 0 0x40>;
570 dmas = <&dmac0 0x93>, <&dmac0 0x92>,
571 <&dmac1 0x93>, <&dmac1 0x92>;
577 #size-cells = <0>;
584 reg = <0 0xe6510000 0 0x40>;
587 dmas = <&dmac0 0x95>, <&dmac0 0x94>,
588 <&dmac1 0x95>, <&dmac1 0x94>;
594 #size-cells = <0>;
601 reg = <0 0xe66d0000 0 0x40>;
604 dmas = <&dmac0 0x97>, <&dmac0 0x96>,
605 <&dmac1 0x97>, <&dmac1 0x96>;
611 #size-cells = <0>;
618 reg = <0 0xe66d8000 0 0x40>;
622 dmas = <&dmac0 0x99>, <&dmac0 0x98>,
623 <&dmac1 0x99>, <&dmac1 0x98>;
628 #size-cells = <0>;
635 reg = <0 0xe66e0000 0 0x40>;
638 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
639 <&dmac1 0x9b>, <&dmac1 0x9a>;
645 #size-cells = <0>;
652 reg = <0 0xe6540000 0 0x60>;
658 dmas = <&dmac0 0x31>, <&dmac0 0x30>,
659 <&dmac1 0x31>, <&dmac1 0x30>;
669 reg = <0 0xe6550000 0 0x60>;
675 dmas = <&dmac0 0x33>, <&dmac0 0x32>,
676 <&dmac1 0x33>, <&dmac1 0x32>;
686 reg = <0 0xe6560000 0 0x60>;
692 dmas = <&dmac0 0x35>, <&dmac0 0x34>,
693 <&dmac1 0x35>, <&dmac1 0x34>;
703 reg = <0 0xe66a0000 0 0x60>;
709 dmas = <&dmac0 0x37>, <&dmac0 0x36>,
710 <&dmac1 0x37>, <&dmac1 0x36>;
720 reg = <0 0xe6660000 0 0x8500>;
770 reg = <0 0xe6800000 0 0x1000>;
807 rx-internal-delay-ps = <0>;
808 tx-internal-delay-ps = <0>;
810 #size-cells = <0>;
817 reg = <0 0xe6810000 0 0x1000>;
854 rx-internal-delay-ps = <0>;
855 tx-internal-delay-ps = <0>;
857 #size-cells = <0>;
864 reg = <0 0xe6820000 0 0x1000>;
901 rx-internal-delay-ps = <0>;
902 tx-internal-delay-ps = <0>;
904 #size-cells = <0>;
910 reg = <0 0xe6e30000 0 0x10>;
920 reg = <0 0xe6e31000 0 0x10>;
930 reg = <0 0xe6e32000 0 0x10>;
940 reg = <0 0xe6e33000 0 0x10>;
950 reg = <0 0xe6e34000 0 0x10>;
960 reg = <0 0xe6e35000 0 0x10>;
970 reg = <0 0xe6e36000 0 0x10>;
980 reg = <0 0xe6e37000 0 0x10>;
990 reg = <0 0xe6e38000 0 0x10>;
1000 reg = <0 0xe6e39000 0 0x10>;
1011 reg = <0 0xe6e60000 0 64>;
1017 dmas = <&dmac0 0x51>, <&dmac0 0x50>,
1018 <&dmac1 0x51>, <&dmac1 0x50>;
1028 reg = <0 0xe6e68000 0 64>;
1034 dmas = <&dmac0 0x53>, <&dmac0 0x52>,
1035 <&dmac1 0x53>, <&dmac1 0x52>;
1045 reg = <0 0xe6c50000 0 64>;
1051 dmas = <&dmac0 0x57>, <&dmac0 0x56>,
1052 <&dmac1 0x57>, <&dmac1 0x56>;
1062 reg = <0 0xe6c40000 0 64>;
1068 dmas = <&dmac0 0x59>, <&dmac0 0x58>,
1069 <&dmac1 0x59>, <&dmac1 0x58>;
1078 reg = <0 0xe6e80000 0 0x148>;
1090 reg = <0 0xe6e90000 0 0x0064>;
1093 dmas = <&dmac0 0x41>, <&dmac0 0x40>,
1094 <&dmac1 0x41>, <&dmac1 0x40>;
1099 #size-cells = <0>;
1106 reg = <0 0xe6ea0000 0 0x0064>;
1109 dmas = <&dmac0 0x43>, <&dmac0 0x42>,
1110 <&dmac1 0x43>, <&dmac1 0x42>;
1115 #size-cells = <0>;
1122 reg = <0 0xe6c00000 0 0x0064>;
1125 dmas = <&dmac0 0x45>, <&dmac0 0x44>,
1126 <&dmac1 0x45>, <&dmac1 0x44>;
1131 #size-cells = <0>;
1138 reg = <0 0xe6c10000 0 0x0064>;
1141 dmas = <&dmac0 0x47>, <&dmac0 0x46>,
1142 <&dmac1 0x47>, <&dmac1 0x46>;
1147 #size-cells = <0>;
1154 reg = <0 0xe6c20000 0 0x0064>;
1157 dmas = <&dmac0 0x49>, <&dmac0 0x48>,
1158 <&dmac1 0x49>, <&dmac1 0x48>;
1163 #size-cells = <0>;
1170 reg = <0 0xe6c28000 0 0x0064>;
1173 dmas = <&dmac0 0x4b>, <&dmac0 0x4a>,
1174 <&dmac1 0x4b>, <&dmac1 0x4a>;
1179 #size-cells = <0>;
1185 reg = <0 0xe6ef0000 0 0x1000>;
1190 renesas,id = <0>;
1195 #size-cells = <0>;
1199 #size-cells = <0>;
1203 vin00isp0: endpoint@0 {
1204 reg = <0>;
1213 reg = <0 0xe6ef1000 0 0x1000>;
1223 #size-cells = <0>;
1227 #size-cells = <0>;
1231 vin01isp0: endpoint@0 {
1232 reg = <0>;
1241 reg = <0 0xe6ef2000 0 0x1000>;
1251 #size-cells = <0>;
1255 #size-cells = <0>;
1259 vin02isp0: endpoint@0 {
1260 reg = <0>;
1269 reg = <0 0xe6ef3000 0 0x1000>;
1279 #size-cells = <0>;
1283 #size-cells = <0>;
1287 vin03isp0: endpoint@0 {
1288 reg = <0>;
1297 reg = <0 0xe6ef4000 0 0x1000>;
1307 #size-cells = <0>;
1311 #size-cells = <0>;
1315 vin04isp0: endpoint@0 {
1316 reg = <0>;
1325 reg = <0 0xe6ef5000 0 0x1000>;
1335 #size-cells = <0>;
1339 #size-cells = <0>;
1343 vin05isp0: endpoint@0 {
1344 reg = <0>;
1353 reg = <0 0xe6ef6000 0 0x1000>;
1363 #size-cells = <0>;
1367 #size-cells = <0>;
1371 vin06isp0: endpoint@0 {
1372 reg = <0>;
1381 reg = <0 0xe6ef7000 0 0x1000>;
1391 #size-cells = <0>;
1395 #size-cells = <0>;
1399 vin07isp0: endpoint@0 {
1400 reg = <0>;
1409 reg = <0 0xe6ef8000 0 0x1000>;
1419 #size-cells = <0>;
1423 #size-cells = <0>;
1437 reg = <0 0xe6ef9000 0 0x1000>;
1447 #size-cells = <0>;
1451 #size-cells = <0>;
1465 reg = <0 0xe6efa000 0 0x1000>;
1475 #size-cells = <0>;
1479 #size-cells = <0>;
1493 reg = <0 0xe6efb000 0 0x1000>;
1503 #size-cells = <0>;
1507 #size-cells = <0>;
1521 reg = <0 0xe6efc000 0 0x1000>;
1531 #size-cells = <0>;
1535 #size-cells = <0>;
1549 reg = <0 0xe6efd000 0 0x1000>;
1559 #size-cells = <0>;
1563 #size-cells = <0>;
1577 reg = <0 0xe6efe000 0 0x1000>;
1587 #size-cells = <0>;
1591 #size-cells = <0>;
1605 reg = <0 0xe6eff000 0 0x1000>;
1615 #size-cells = <0>;
1619 #size-cells = <0>;
1634 reg = <0 0xe7350000 0 0x1000>,
1635 <0 0xe7300000 0 0x10000>;
1664 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1677 reg = <0 0xe7351000 0 0x1000>,
1678 <0 0xe7310000 0 0x10000>;
1721 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1727 * clkout : #clock-cells = <0>; <&rcar_sound>;
1731 reg = <0 0xec5a0000 0 0x020>,
1732 <0 0xec540000 0 0x1000>,
1733 <0 0xec541000 0 0x050>,
1734 <0 0xec400000 0 0x40000>;
1738 clock-names = "ssiu.0", "ssi.0", "clkin";
1741 reset-names = "ssiu.0", "ssi.0";
1745 ssiu00: ssiu-0 {
1746 dmas = <&dmac0 0x6e>, <&dmac0 0x6f>;
1750 dmas = <&dmac0 0x6c>, <&dmac0 0x6d>;
1754 dmas = <&dmac0 0x6a>, <&dmac0 0x6b>;
1758 dmas = <&dmac0 0x68>, <&dmac0 0x69>;
1762 dmas = <&dmac0 0x66>, <&dmac0 0x67>;
1766 dmas = <&dmac0 0x64>, <&dmac0 0x65>;
1770 dmas = <&dmac0 0x62>, <&dmac0 0x63>;
1774 dmas = <&dmac0 0x60>, <&dmac0 0x61>;
1780 ssi0: ssi-0 {
1789 reg = <0 0xee140000 0 0x2000>;
1804 reg = <0 0xee200000 0 0x200>,
1805 <0 0x08000000 0 0x04000000>,
1806 <0 0xee208000 0 0x100>;
1813 #size-cells = <0>;
1820 reg = <0 0xee480000 0 0x20000>;
1829 reg = <0 0xee4c0000 0 0x20000>;
1838 reg = <0 0xeed00000 0 0x20000>;
1847 reg = <0 0xeed40000 0 0x20000>;
1856 reg = <0 0xeed80000 0 0x20000>;
1865 reg = <0 0xeedc0000 0 0x20000>;
1874 reg = <0 0xeee00000 0 0x20000>;
1883 reg = <0 0xeee80000 0 0x20000>;
1892 reg = <0 0xeeec0000 0 0x20000>;
1901 reg = <0 0xeef00000 0 0x20000>;
1910 reg = <0 0xeef40000 0 0x20000>;
1919 reg = <0 0xeefc0000 0 0x20000>;
1929 #address-cells = <0>;
1931 reg = <0x0 0xf1000000 0 0x20000>,
1932 <0x0 0xf1060000 0 0x110000>;
1938 reg = <0 0xfe500000 0 0x40000>;
1947 #size-cells = <0>;
1949 port@0 {
1950 reg = <0>;
1964 reg = <0 0xfe540000 0 0x40000>;
1973 #size-cells = <0>;
1975 port@0 {
1976 reg = <0>;
1990 reg = <0 0xfea10000 0 0x200>;
1998 reg = <0 0xfea11000 0 0x200>;
2006 reg = <0 0xfea20000 0 0x7000>;
2017 reg = <0 0xfea28000 0 0x7000>;
2028 reg = <0 0xfeb00000 0 0x40000>;
2032 clock-names = "du.0";
2035 reset-names = "du.0";
2036 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2042 #size-cells = <0>;
2044 port@0 {
2045 reg = <0>;
2062 reg = <0 0xfed00000 0 0x10000>;
2071 #size-cells = <0>;
2073 port@0 {
2075 #size-cells = <0>;
2077 reg = <0>;
2079 isp0csi40: endpoint@0 {
2080 reg = <0>;
2145 reg = <0 0xfed20000 0 0x10000>;
2154 #size-cells = <0>;
2156 port@0 {
2158 #size-cells = <0>;
2160 reg = <0>;
2228 reg = <0 0xfed80000 0 0x10000>;
2240 #size-cells = <0>;
2242 port@0 {
2243 reg = <0>;
2257 reg = <0 0xfed90000 0 0x10000>;
2269 #size-cells = <0>;
2271 port@0 {
2272 reg = <0>;
2286 reg = <0 0xfff00044 0 4>;
2294 thermal-sensors = <&tsc 0>;