Lines Matching +full:0 +full:x040000
59 #size-cells = <0>;
61 port@0 {
62 reg = <0>;
80 reg = <0x0 0x48000000 0x0 0x38000000>;
85 #clock-cells = <0>;
91 pinctrl-0 = <&avb_pins>;
100 phy0: ethernet-phy@0 {
104 reg = <0>;
112 pinctrl-0 = <&canfd0_pins>;
125 port@0 {
127 clock-lanes = <0>;
137 clock-names = "du.0", "dclkin.0";
150 pinctrl-0 = <&i2c0_pins>;
158 reg = <0x20>;
165 reg = <0x39>;
175 #size-cells = <0>;
177 port@0 {
178 reg = <0>;
195 pinctrl-0 = <&i2c3_pins>;
203 reg = <0x48>;
205 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
206 enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
210 #size-cells = <0>;
212 port@0 {
213 reg = <0>;
231 clock-lanes = <0>;
240 #size-cells = <0>;
242 i2c@0 {
244 #size-cells = <0>;
245 reg = <0>;
252 #size-cells = <0>;
260 #size-cells = <0>;
268 #size-cells = <0>;
290 pinctrl-0 = <&scif_clk_pins>;
330 pinctrl-0 = <&qspi0_pins>;
335 flash@0 {
337 reg = <0>;
346 bootparam@0 {
347 reg = <0x00000000 0x040000>;
351 reg = <0x00040000 0x080000>;
355 reg = <0x000c0000 0x080000>;
359 reg = <0x00140000 0x040000>;
363 reg = <0x00180000 0x040000>;
367 reg = <0x001c0000 0x460000>;
371 reg = <0x00640000 0x0c0000>;
375 reg = <0x00700000 0x040000>;
379 reg = <0x00740000 0x080000>;
382 reg = <0x007c0000 0x1400000>;
385 reg = <0x01bc0000 0x2440000>;
397 pinctrl-0 = <&scif0_pins>;