Lines Matching +full:0 +full:xe6550000
21 * The external audio clocks are configured as 0 Hz fixed frequency
27 #clock-cells = <0>;
28 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
39 #clock-cells = <0>;
40 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
50 cluster0_opp: opp-table-0 {
95 #size-cells = <0>;
129 a57_0: cpu@0 {
131 reg = <0x0>;
146 reg = <0x1>;
160 reg = <0x2>;
174 reg = <0x3>;
188 reg = <0x100>;
203 reg = <0x101>;
216 reg = <0x102>;
229 reg = <0x103>;
240 L2_CA57: cache-controller-0 {
257 CPU_SLEEP_0: cpu-sleep-0 {
259 arm,psci-suspend-param = <0x0010000>;
268 arm,psci-suspend-param = <0x0010000>;
279 #clock-cells = <0>;
281 clock-frequency = <0>;
286 #clock-cells = <0>;
288 clock-frequency = <0>;
294 #clock-cells = <0>;
295 clock-frequency = <0>;
324 #clock-cells = <0>;
325 clock-frequency = <0>;
338 reg = <0 0xe6020000 0 0x0c>;
349 reg = <0 0xe6050000 0 0x50>;
353 gpio-ranges = <&pfc 0 0 16>;
364 reg = <0 0xe6051000 0 0x50>;
368 gpio-ranges = <&pfc 0 32 29>;
379 reg = <0 0xe6052000 0 0x50>;
383 gpio-ranges = <&pfc 0 64 15>;
394 reg = <0 0xe6053000 0 0x50>;
398 gpio-ranges = <&pfc 0 96 16>;
409 reg = <0 0xe6054000 0 0x50>;
413 gpio-ranges = <&pfc 0 128 18>;
424 reg = <0 0xe6055000 0 0x50>;
428 gpio-ranges = <&pfc 0 160 26>;
439 reg = <0 0xe6055400 0 0x50>;
443 gpio-ranges = <&pfc 0 192 32>;
454 reg = <0 0xe6055800 0 0x50>;
458 gpio-ranges = <&pfc 0 224 4>;
468 reg = <0 0xe6060000 0 0x50c>;
474 reg = <0 0xe60f0000 0 0x1004>;
487 reg = <0 0xe6130000 0 0x1004>;
506 reg = <0 0xe6140000 0 0x1004>;
525 reg = <0 0xe6148000 0 0x1004>;
543 reg = <0 0xe6150000 0 0x1000>;
547 #power-domain-cells = <0>;
553 reg = <0 0xe6160000 0 0x0200>;
558 reg = <0 0xe6180000 0 0x0400>;
564 reg = <0 0xe6198000 0 0x100>,
565 <0 0xe61a0000 0 0x100>,
566 <0 0xe61a8000 0 0x100>;
580 reg = <0 0xe61c0000 0 0x200>;
581 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
594 reg = <0 0xe61e0000 0 0x30>;
607 reg = <0 0xe6fc0000 0 0x30>;
620 reg = <0 0xe6fd0000 0 0x30>;
633 reg = <0 0xe6fe0000 0 0x30>;
646 reg = <0 0xffc00000 0 0x30>;
659 #size-cells = <0>;
662 reg = <0 0xe6500000 0 0x40>;
667 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
668 <&dmac2 0x91>, <&dmac2 0x90>;
676 #size-cells = <0>;
679 reg = <0 0xe6508000 0 0x40>;
684 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
685 <&dmac2 0x93>, <&dmac2 0x92>;
693 #size-cells = <0>;
696 reg = <0 0xe6510000 0 0x40>;
701 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
702 <&dmac2 0x95>, <&dmac2 0x94>;
710 #size-cells = <0>;
713 reg = <0 0xe66d0000 0 0x40>;
718 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
726 #size-cells = <0>;
729 reg = <0 0xe66d8000 0 0x40>;
734 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
742 #size-cells = <0>;
745 reg = <0 0xe66e0000 0 0x40>;
750 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
758 #size-cells = <0>;
761 reg = <0 0xe66e8000 0 0x40>;
766 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
774 #size-cells = <0>;
778 reg = <0 0xe60b0000 0 0x425>;
783 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
792 reg = <0 0xe6540000 0 0x60>;
798 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
799 <&dmac2 0x31>, <&dmac2 0x30>;
810 reg = <0 0xe6550000 0 0x60>;
816 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
817 <&dmac2 0x33>, <&dmac2 0x32>;
828 reg = <0 0xe6560000 0 0x60>;
834 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
835 <&dmac2 0x35>, <&dmac2 0x34>;
846 reg = <0 0xe66a0000 0 0x60>;
852 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
863 reg = <0 0xe66b0000 0 0x60>;
869 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
879 reg = <0 0xe6590000 0 0x200>;
882 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
883 <&usb_dmac1 0>, <&usb_dmac1 1>;
896 reg = <0 0xe6590630 0 0x02>;
901 #clock-cells = <0>;
911 reg = <0 0xe65a0000 0 0x100>;
925 reg = <0 0xe65b0000 0 0x100>;
939 reg = <0 0xe65ee000 0 0x90>;
945 #phy-cells = <0>;
952 reg = <0 0xe6700000 0 0x10000>;
981 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
994 reg = <0 0xe7300000 0 0x10000>;
1023 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1036 reg = <0 0xe7310000 0 0x10000>;
1077 reg = <0 0xe6740000 0 0x1000>;
1078 renesas,ipmmu-main = <&ipmmu_mm 0>;
1085 reg = <0 0xe7740000 0 0x1000>;
1093 reg = <0 0xe6570000 0 0x1000>;
1101 reg = <0 0xe67b0000 0 0x1000>;
1110 reg = <0 0xec670000 0 0x1000>;
1118 reg = <0 0xfd800000 0 0x1000>;
1126 reg = <0 0xfd950000 0 0x1000>;
1134 reg = <0 0xfd960000 0 0x1000>;
1142 reg = <0 0xfd970000 0 0x1000>;
1150 reg = <0 0xfe6b0000 0 0x1000>;
1158 reg = <0 0xfe6f0000 0 0x1000>;
1166 reg = <0 0xfebd0000 0 0x1000>;
1174 reg = <0 0xfebe0000 0 0x1000>;
1182 reg = <0 0xfe990000 0 0x1000>;
1190 reg = <0 0xfe980000 0 0x1000>;
1199 reg = <0 0xe6800000 0 0x800>;
1237 rx-internal-delay-ps = <0>;
1238 tx-internal-delay-ps = <0>;
1241 #size-cells = <0>;
1248 reg = <0 0xe6c30000 0 0x1000>;
1264 reg = <0 0xe6c38000 0 0x1000>;
1280 reg = <0 0xe66c0000 0 0x8000>;
1305 reg = <0 0xe6e30000 0 0x8>;
1315 reg = <0 0xe6e31000 0 0x8>;
1325 reg = <0 0xe6e32000 0 0x8>;
1335 reg = <0 0xe6e33000 0 0x8>;
1345 reg = <0 0xe6e34000 0 0x8>;
1355 reg = <0 0xe6e35000 0 0x8>;
1365 reg = <0 0xe6e36000 0 0x8>;
1376 reg = <0 0xe6e60000 0 0x40>;
1382 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1383 <&dmac2 0x51>, <&dmac2 0x50>;
1393 reg = <0 0xe6e68000 0 0x40>;
1399 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1400 <&dmac2 0x53>, <&dmac2 0x52>;
1410 reg = <0 0xe6e88000 0 0x40>;
1416 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1417 <&dmac2 0x13>, <&dmac2 0x12>;
1427 reg = <0 0xe6c50000 0 0x40>;
1433 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1443 reg = <0 0xe6c40000 0 0x40>;
1449 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1459 reg = <0 0xe6f30000 0 0x40>;
1465 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1466 <&dmac2 0x5b>, <&dmac2 0x5a>;
1476 reg = <0 0xe6e90000 0 0x0064>;
1479 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1480 <&dmac2 0x41>, <&dmac2 0x40>;
1485 #size-cells = <0>;
1492 reg = <0 0xe6ea0000 0 0x0064>;
1495 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1496 <&dmac2 0x43>, <&dmac2 0x42>;
1501 #size-cells = <0>;
1508 reg = <0 0xe6c00000 0 0x0064>;
1511 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1516 #size-cells = <0>;
1523 reg = <0 0xe6c10000 0 0x0064>;
1526 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1531 #size-cells = <0>;
1537 reg = <0 0xe6ef0000 0 0x1000>;
1542 renesas,id = <0>;
1547 #size-cells = <0>;
1551 #size-cells = <0>;
1555 vin0csi20: endpoint@0 {
1556 reg = <0>;
1569 reg = <0 0xe6ef1000 0 0x1000>;
1579 #size-cells = <0>;
1583 #size-cells = <0>;
1587 vin1csi20: endpoint@0 {
1588 reg = <0>;
1601 reg = <0 0xe6ef2000 0 0x1000>;
1611 #size-cells = <0>;
1615 #size-cells = <0>;
1619 vin2csi20: endpoint@0 {
1620 reg = <0>;
1633 reg = <0 0xe6ef3000 0 0x1000>;
1643 #size-cells = <0>;
1647 #size-cells = <0>;
1651 vin3csi20: endpoint@0 {
1652 reg = <0>;
1665 reg = <0 0xe6ef4000 0 0x1000>;
1675 #size-cells = <0>;
1679 #size-cells = <0>;
1683 vin4csi20: endpoint@0 {
1684 reg = <0>;
1693 reg = <0 0xe6ef5000 0 0x1000>;
1703 #size-cells = <0>;
1707 #size-cells = <0>;
1711 vin5csi20: endpoint@0 {
1712 reg = <0>;
1721 reg = <0 0xe6ef6000 0 0x1000>;
1731 #size-cells = <0>;
1735 #size-cells = <0>;
1739 vin6csi20: endpoint@0 {
1740 reg = <0>;
1749 reg = <0 0xe6ef7000 0 0x1000>;
1759 #size-cells = <0>;
1763 #size-cells = <0>;
1767 vin7csi20: endpoint@0 {
1768 reg = <0>;
1779 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1785 * clkout : #clock-cells = <0>; <&rcar_sound>;
1789 reg = <0 0xec500000 0 0x1000>, /* SCU */
1790 <0 0xec5a0000 0 0x100>, /* ADG */
1791 <0 0xec540000 0 0x1000>, /* SSIU */
1792 <0 0xec541000 0 0x280>, /* SSI */
1793 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1816 "ssi.1", "ssi.0",
1819 "src.1", "src.0",
1820 "mix.1", "mix.0",
1821 "ctu.1", "ctu.0",
1822 "dvc.0", "dvc.1",
1834 "ssi.1", "ssi.0";
1838 dvc0: dvc-0 {
1839 dmas = <&audma1 0xbc>;
1843 dmas = <&audma1 0xbe>;
1849 mix0: mix-0 { };
1854 ctu00: ctu-0 { };
1865 src0: src-0 {
1867 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1872 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1877 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1882 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1887 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1892 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1897 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1902 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1907 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1912 dmas = <&audma0 0x97>, <&audma1 0xba>;
1918 ssiu00: ssiu-0 {
1919 dmas = <&audma0 0x15>, <&audma1 0x16>;
1923 dmas = <&audma0 0x35>, <&audma1 0x36>;
1927 dmas = <&audma0 0x37>, <&audma1 0x38>;
1931 dmas = <&audma0 0x47>, <&audma1 0x48>;
1935 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1939 dmas = <&audma0 0x43>, <&audma1 0x44>;
1943 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1947 dmas = <&audma0 0x53>, <&audma1 0x54>;
1951 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1955 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1959 dmas = <&audma0 0x57>, <&audma1 0x58>;
1963 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1967 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1971 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1975 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1979 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1983 dmas = <&audma0 0x63>, <&audma1 0x64>;
1987 dmas = <&audma0 0x67>, <&audma1 0x68>;
1991 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1995 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1999 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2003 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2007 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2011 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2015 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2019 dmas = <&audma0 0x21>, <&audma1 0x22>;
2023 dmas = <&audma0 0x23>, <&audma1 0x24>;
2027 dmas = <&audma0 0x25>, <&audma1 0x26>;
2031 dmas = <&audma0 0x27>, <&audma1 0x28>;
2035 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2039 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2043 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2047 dmas = <&audma0 0x71>, <&audma1 0x72>;
2051 dmas = <&audma0 0x17>, <&audma1 0x18>;
2055 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2059 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2063 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2067 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2071 dmas = <&audma0 0x31>, <&audma1 0x32>;
2075 dmas = <&audma0 0x33>, <&audma1 0x34>;
2079 dmas = <&audma0 0x73>, <&audma1 0x74>;
2083 dmas = <&audma0 0x75>, <&audma1 0x76>;
2087 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2091 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2095 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2099 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2103 dmas = <&audma0 0x81>, <&audma1 0x82>;
2107 dmas = <&audma0 0x83>, <&audma1 0x84>;
2111 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2115 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2119 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2123 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2129 ssi0: ssi-0 {
2131 dmas = <&audma0 0x01>, <&audma1 0x02>;
2136 dmas = <&audma0 0x03>, <&audma1 0x04>;
2141 dmas = <&audma0 0x05>, <&audma1 0x06>;
2146 dmas = <&audma0 0x07>, <&audma1 0x08>;
2151 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2156 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2161 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2166 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2171 dmas = <&audma0 0x11>, <&audma1 0x12>;
2176 dmas = <&audma0 0x13>, <&audma1 0x14>;
2185 reg = <0 0xec700000 0 0x10000>;
2214 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2227 reg = <0 0xec720000 0 0x10000>;
2269 reg = <0 0xee000000 0 0xc00>;
2280 reg = <0 0xee020000 0 0x400>;
2290 reg = <0 0xee080000 0 0x100>;
2302 reg = <0 0xee0a0000 0 0x100>;
2314 reg = <0 0xee080100 0 0x100>;
2327 reg = <0 0xee0a0100 0 0x100>;
2341 reg = <0 0xee080200 0 0x700>;
2353 reg = <0 0xee0a0200 0 0x700>;
2364 reg = <0 0xee100000 0 0x2000>;
2378 reg = <0 0xee120000 0 0x2000>;
2392 reg = <0 0xee140000 0 0x2000>;
2406 reg = <0 0xee160000 0 0x2000>;
2420 reg = <0 0xee200000 0 0x200>,
2421 <0 0x08000000 0 0x4000000>,
2422 <0 0xee208000 0 0x100>;
2429 #size-cells = <0>;
2436 reg = <0 0xee300000 0 0x200000>;
2448 #address-cells = <0>;
2450 reg = <0x0 0xf1010000 0 0x1000>,
2451 <0x0 0xf1020000 0 0x20000>,
2452 <0x0 0xf1040000 0 0x20000>,
2453 <0x0 0xf1060000 0 0x20000>;
2465 reg = <0 0xfe000000 0 0x80000>;
2468 bus-range = <0x00 0xff>;
2470 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2471 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2472 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2473 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2475 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2480 interrupt-map-mask = <0 0 0 0>;
2481 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2486 iommu-map = <0 &ipmmu_hc 0 1>;
2487 iommu-map-mask = <0>;
2494 reg = <0 0xee800000 0 0x80000>;
2497 bus-range = <0x00 0xff>;
2499 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2500 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2501 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2502 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2504 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2509 interrupt-map-mask = <0 0 0 0>;
2510 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2515 iommu-map = <0 &ipmmu_hc 1 1>;
2516 iommu-map-mask = <0>;
2523 reg = <0x0 0xfe000000 0 0x80000>,
2524 <0x0 0xfe100000 0 0x100000>,
2525 <0x0 0xfe200000 0 0x200000>,
2526 <0x0 0x30000000 0 0x8000000>,
2527 <0x0 0x38000000 0 0x8000000>;
2542 reg = <0x0 0xee800000 0 0x80000>,
2543 <0x0 0xee900000 0 0x100000>,
2544 <0x0 0xeea00000 0 0x200000>,
2545 <0x0 0xc0000000 0 0x8000000>,
2546 <0x0 0xc8000000 0 0x8000000>;
2560 reg = <0 0xfe920000 0 0x8000>;
2571 reg = <0 0xfe960000 0 0x8000>;
2582 reg = <0 0xfea20000 0 0x5000>;
2593 reg = <0 0xfea28000 0 0x5000>;
2604 reg = <0 0xfe9a0000 0 0x8000>;
2615 reg = <0 0xfe9b0000 0 0x8000>;
2626 reg = <0 0xfe940000 0 0x2400>;
2636 reg = <0 0xfe944000 0 0x2400>;
2646 reg = <0 0xfe950000 0 0x200>;
2654 reg = <0 0xfe951000 0 0x200>;
2662 reg = <0 0xfe96f000 0 0x200>;
2670 reg = <0 0xfe92f000 0 0x200>;
2678 reg = <0 0xfe9af000 0 0x200>;
2686 reg = <0 0xfe9bf000 0 0x200>;
2694 reg = <0 0xfea27000 0 0x200>;
2702 reg = <0 0xfea2f000 0 0x200>;
2710 reg = <0 0xfea80000 0 0x10000>;
2719 #size-cells = <0>;
2721 port@0 {
2722 reg = <0>;
2727 #size-cells = <0>;
2731 csi20vin0: endpoint@0 {
2732 reg = <0>;
2769 reg = <0 0xfeaa0000 0 0x10000>;
2778 #size-cells = <0>;
2780 port@0 {
2781 reg = <0>;
2786 #size-cells = <0>;
2790 csi40vin0: endpoint@0 {
2791 reg = <0>;
2813 reg = <0 0xfead0000 0 0x10000>;
2824 #size-cells = <0>;
2826 port@0 {
2827 reg = <0>;
2844 reg = <0 0xfeb00000 0 0x80000>;
2851 clock-names = "du.0", "du.1", "du.3";
2853 reset-names = "du.0", "du.3";
2856 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2860 #size-cells = <0>;
2862 port@0 {
2863 reg = <0>;
2882 reg = <0 0xfeb90000 0 0x14>;
2890 #size-cells = <0>;
2892 port@0 {
2893 reg = <0>;
2906 reg = <0 0xfff00044 0 4>;
2914 thermal-sensors = <&tsc 0>;
2964 cooling-device = <&a57_0 0 2>;
2970 cooling-device = <&a53_0 0 2>;
2988 #clock-cells = <0>;
2989 clock-frequency = <0>;
2994 #clock-cells = <0>;
2995 clock-frequency = <0>;