Lines Matching +full:0 +full:x040000
36 d3_3v: regulator-0 {
62 #size-cells = <0>;
64 port@0 {
65 reg = <0>;
83 reg = <0 0x48000000 0 0x78000000>;
97 #clock-cells = <0>;
103 pinctrl-0 = <&canfd0_pins>;
116 port@0 {
118 clock-lanes = <0>;
130 port@0 {
132 clock-lanes = <0>;
143 clock-names = "du.0", "dclkin.0";
156 pinctrl-0 = <&gether_pins>;
164 phy0: ethernet-phy@0 {
168 reg = <0>;
176 pinctrl-0 = <&i2c0_pins>;
184 reg = <0x20>;
191 reg = <0x21>;
198 reg = <0x39>;
213 #size-cells = <0>;
215 port@0 {
216 reg = <0>;
233 pinctrl-0 = <&i2c1_pins>;
241 reg = <0x48>;
243 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
244 enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
248 #size-cells = <0>;
250 port@0 {
251 reg = <0>;
269 clock-lanes = <0>;
278 #size-cells = <0>;
280 i2c@0 {
282 #size-cells = <0>;
283 reg = <0>;
290 #size-cells = <0>;
298 #size-cells = <0>;
306 #size-cells = <0>;
316 reg = <0x4a>;
318 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
319 enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
323 #size-cells = <0>;
325 port@0 {
326 reg = <0>;
344 clock-lanes = <0>;
353 #size-cells = <0>;
355 i2c@0 {
357 #size-cells = <0>;
358 reg = <0>;
365 #size-cells = <0>;
373 #size-cells = <0>;
381 #size-cells = <0>;
403 pinctrl-0 = <&mmc_pins>;
474 pinctrl-0 = <&qspi0_pins>;
479 flash@0 {
481 reg = <0>;
490 bootparam@0 {
491 reg = <0x00000000 0x040000>;
495 reg = <0x00040000 0x080000>;
499 reg = <0x000c0000 0x080000>;
503 reg = <0x00140000 0x040000>;
507 reg = <0x00180000 0x040000>;
511 reg = <0x001c0000 0x460000>;
515 reg = <0x00640000 0x0c0000>;
519 reg = <0x00700000 0x040000>;
523 reg = <0x00740000 0x080000>;
526 reg = <0x007c0000 0x1400000>;
529 reg = <0x01bc0000 0x2440000>;
541 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;