Lines Matching +full:sm8450 +full:- +full:mdss
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
10 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
11 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
44 bi_tcxo_div2: bi-tcxo-div2-clk {
45 #clock-cells = <0>;
46 compatible = "fixed-factor-clock";
48 clock-mult = <1>;
49 clock-div = <2>;
52 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
53 #clock-cells = <0>;
54 compatible = "fixed-factor-clock";
56 clock-mult = <1>;
57 clock-div = <2>;
60 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
67 #address-cells = <2>;
68 #size-cells = <0>;
72 compatible = "arm,cortex-a510";
75 enable-method = "psci";
76 next-level-cache = <&L2_0>;
77 power-domains = <&CPU_PD0>;
78 power-domain-names = "psci";
79 qcom,freq-domain = <&cpufreq_hw 0>;
80 capacity-dmips-mhz = <1024>;
81 dynamic-power-coefficient = <100>;
82 #cooling-cells = <2>;
83 L2_0: l2-cache {
85 cache-level = <2>;
86 cache-unified;
87 next-level-cache = <&L3_0>;
88 L3_0: l3-cache {
90 cache-level = <3>;
91 cache-unified;
98 compatible = "arm,cortex-a510";
101 enable-method = "psci";
102 next-level-cache = <&L2_100>;
103 power-domains = <&CPU_PD1>;
104 power-domain-names = "psci";
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 capacity-dmips-mhz = <1024>;
107 dynamic-power-coefficient = <100>;
108 #cooling-cells = <2>;
109 L2_100: l2-cache {
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&L3_0>;
119 compatible = "arm,cortex-a510";
122 enable-method = "psci";
123 next-level-cache = <&L2_200>;
124 power-domains = <&CPU_PD2>;
125 power-domain-names = "psci";
126 qcom,freq-domain = <&cpufreq_hw 0>;
127 capacity-dmips-mhz = <1024>;
128 dynamic-power-coefficient = <100>;
129 #cooling-cells = <2>;
130 L2_200: l2-cache {
132 cache-level = <2>;
133 cache-unified;
134 next-level-cache = <&L3_0>;
140 compatible = "arm,cortex-a715";
143 enable-method = "psci";
144 next-level-cache = <&L2_300>;
145 power-domains = <&CPU_PD3>;
146 power-domain-names = "psci";
147 qcom,freq-domain = <&cpufreq_hw 1>;
148 capacity-dmips-mhz = <1792>;
149 dynamic-power-coefficient = <270>;
150 #cooling-cells = <2>;
151 L2_300: l2-cache {
153 cache-level = <2>;
154 cache-unified;
155 next-level-cache = <&L3_0>;
161 compatible = "arm,cortex-a715";
164 enable-method = "psci";
165 next-level-cache = <&L2_400>;
166 power-domains = <&CPU_PD4>;
167 power-domain-names = "psci";
168 qcom,freq-domain = <&cpufreq_hw 1>;
169 capacity-dmips-mhz = <1792>;
170 dynamic-power-coefficient = <270>;
171 #cooling-cells = <2>;
172 L2_400: l2-cache {
174 cache-level = <2>;
175 cache-unified;
176 next-level-cache = <&L3_0>;
182 compatible = "arm,cortex-a710";
185 enable-method = "psci";
186 next-level-cache = <&L2_500>;
187 power-domains = <&CPU_PD5>;
188 power-domain-names = "psci";
189 qcom,freq-domain = <&cpufreq_hw 1>;
190 capacity-dmips-mhz = <1792>;
191 dynamic-power-coefficient = <270>;
192 #cooling-cells = <2>;
193 L2_500: l2-cache {
195 cache-level = <2>;
196 cache-unified;
197 next-level-cache = <&L3_0>;
203 compatible = "arm,cortex-a710";
206 enable-method = "psci";
207 next-level-cache = <&L2_600>;
208 power-domains = <&CPU_PD6>;
209 power-domain-names = "psci";
210 qcom,freq-domain = <&cpufreq_hw 1>;
211 capacity-dmips-mhz = <1792>;
212 dynamic-power-coefficient = <270>;
213 #cooling-cells = <2>;
214 L2_600: l2-cache {
216 cache-level = <2>;
217 cache-unified;
218 next-level-cache = <&L3_0>;
224 compatible = "arm,cortex-x3";
227 enable-method = "psci";
228 next-level-cache = <&L2_700>;
229 power-domains = <&CPU_PD7>;
230 power-domain-names = "psci";
231 qcom,freq-domain = <&cpufreq_hw 2>;
232 capacity-dmips-mhz = <1894>;
233 dynamic-power-coefficient = <588>;
234 #cooling-cells = <2>;
235 L2_700: l2-cache {
237 cache-level = <2>;
238 cache-unified;
239 next-level-cache = <&L3_0>;
243 cpu-map {
279 idle-states {
280 entry-method = "psci";
282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
283 compatible = "arm,idle-state";
284 idle-state-name = "silver-rail-power-collapse";
285 arm,psci-suspend-param = <0x40000004>;
286 entry-latency-us = <550>;
287 exit-latency-us = <750>;
288 min-residency-us = <6700>;
289 local-timer-stop;
292 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
293 compatible = "arm,idle-state";
294 idle-state-name = "gold-rail-power-collapse";
295 arm,psci-suspend-param = <0x40000004>;
296 entry-latency-us = <600>;
297 exit-latency-us = <1300>;
298 min-residency-us = <8136>;
299 local-timer-stop;
302 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
303 compatible = "arm,idle-state";
304 idle-state-name = "goldplus-rail-power-collapse";
305 arm,psci-suspend-param = <0x40000004>;
306 entry-latency-us = <500>;
307 exit-latency-us = <1350>;
308 min-residency-us = <7480>;
309 local-timer-stop;
313 domain-idle-states {
314 CLUSTER_SLEEP_0: cluster-sleep-0 {
315 compatible = "domain-idle-state";
316 arm,psci-suspend-param = <0x41000044>;
317 entry-latency-us = <750>;
318 exit-latency-us = <2350>;
319 min-residency-us = <9144>;
322 CLUSTER_SLEEP_1: cluster-sleep-1 {
323 compatible = "domain-idle-state";
324 arm,psci-suspend-param = <0x4100c344>;
325 entry-latency-us = <2800>;
326 exit-latency-us = <4400>;
327 min-residency-us = <10150>;
334 compatible = "qcom,scm-sm8550", "qcom,scm";
339 clk_virt: interconnect-0 {
340 compatible = "qcom,sm8550-clk-virt";
341 #interconnect-cells = <2>;
342 qcom,bcm-voters = <&apps_bcm_voter>;
345 mc_virt: interconnect-1 {
346 compatible = "qcom,sm8550-mc-virt";
347 #interconnect-cells = <2>;
348 qcom,bcm-voters = <&apps_bcm_voter>;
358 compatible = "arm,armv8-pmuv3";
363 compatible = "arm,psci-1.0";
366 CPU_PD0: power-domain-cpu0 {
367 #power-domain-cells = <0>;
368 power-domains = <&CLUSTER_PD>;
369 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
372 CPU_PD1: power-domain-cpu1 {
373 #power-domain-cells = <0>;
374 power-domains = <&CLUSTER_PD>;
375 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
378 CPU_PD2: power-domain-cpu2 {
379 #power-domain-cells = <0>;
380 power-domains = <&CLUSTER_PD>;
381 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
384 CPU_PD3: power-domain-cpu3 {
385 #power-domain-cells = <0>;
386 power-domains = <&CLUSTER_PD>;
387 domain-idle-states = <&BIG_CPU_SLEEP_0>;
390 CPU_PD4: power-domain-cpu4 {
391 #power-domain-cells = <0>;
392 power-domains = <&CLUSTER_PD>;
393 domain-idle-states = <&BIG_CPU_SLEEP_0>;
396 CPU_PD5: power-domain-cpu5 {
397 #power-domain-cells = <0>;
398 power-domains = <&CLUSTER_PD>;
399 domain-idle-states = <&BIG_CPU_SLEEP_0>;
402 CPU_PD6: power-domain-cpu6 {
403 #power-domain-cells = <0>;
404 power-domains = <&CLUSTER_PD>;
405 domain-idle-states = <&BIG_CPU_SLEEP_0>;
408 CPU_PD7: power-domain-cpu7 {
409 #power-domain-cells = <0>;
410 power-domains = <&CLUSTER_PD>;
411 domain-idle-states = <&PRIME_CPU_SLEEP_0>;
414 CLUSTER_PD: power-domain-cluster {
415 #power-domain-cells = <0>;
416 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
420 reserved_memory: reserved-memory {
421 #address-cells = <2>;
422 #size-cells = <2>;
425 hyp_mem: hyp-region@80000000 {
427 no-map;
430 cpusys_vm_mem: cpusys-vm-region@80a00000 {
432 no-map;
435 hyp_tags_mem: hyp-tags-region@80e00000 {
437 no-map;
440 xbl_sc_mem: xbl-sc-region@d8100000 {
442 no-map;
445 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
447 no-map;
451 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
453 no-map;
456 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
457 compatible = "qcom,cmd-db";
459 no-map;
463 aop_config_merged_mem: aop-config-merged-region@81c80000 {
465 no-map;
473 no-map;
476 adsp_mhi_mem: adsp-mhi-region@81f00000 {
478 no-map;
481 global_sync_mem: global-sync-region@82600000 {
483 no-map;
486 tz_stat_mem: tz-stat-region@82700000 {
488 no-map;
491 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
493 no-map;
496 mpss_mem: mpss-region@8a800000 {
498 no-map;
501 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
503 no-map;
506 ipa_fw_mem: ipa-fw-region@9b080000 {
508 no-map;
511 ipa_gsi_mem: ipa-gsi-region@9b090000 {
513 no-map;
516 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
518 no-map;
521 spss_region_mem: spss-region@9b100000 {
523 no-map;
527 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
529 no-map;
533 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
535 no-map;
538 camera_mem: camera-region@9b300000 {
540 no-map;
543 video_mem: video-region@9bb00000 {
545 no-map;
548 cvp_mem: cvp-region@9c200000 {
550 no-map;
553 cdsp_mem: cdsp-region@9c900000 {
555 no-map;
558 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
560 no-map;
563 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
565 no-map;
568 adspslpi_mem: adspslpi-region@9ea00000 {
570 no-map;
577 rmtfs_mem: rmtfs-region@d4a80000 {
578 compatible = "qcom,rmtfs-mem";
580 no-map;
582 qcom,client-id = <1>;
586 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
588 no-map;
591 tz_reserved_mem: tz-reserved-region@d8000000 {
593 no-map;
596 cpucp_fw_mem: cpucp-fw-region@d8140000 {
598 no-map;
601 qtee_mem: qtee-region@d8300000 {
603 no-map;
606 ta_mem: ta-region@d8800000 {
608 no-map;
611 tz_tags_mem: tz-tags-region@e1200000 {
613 no-map;
616 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
618 no-map;
621 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
623 no-map;
626 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
628 no-map;
631 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
633 no-map;
636 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
638 no-map;
641 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
643 no-map;
646 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
648 no-map;
651 oem_vm_mem: oem-vm-region@f8400000 {
653 no-map;
656 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
658 no-map;
661 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
663 no-map;
666 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
668 no-map;
671 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
673 no-map;
677 smp2p-adsp {
680 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
686 qcom,local-pid = <0>;
687 qcom,remote-pid = <2>;
689 smp2p_adsp_out: master-kernel {
690 qcom,entry-name = "master-kernel";
691 #qcom,smem-state-cells = <1>;
694 smp2p_adsp_in: slave-kernel {
695 qcom,entry-name = "slave-kernel";
696 interrupt-controller;
697 #interrupt-cells = <2>;
701 smp2p-cdsp {
704 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
710 qcom,local-pid = <0>;
711 qcom,remote-pid = <5>;
713 smp2p_cdsp_out: master-kernel {
714 qcom,entry-name = "master-kernel";
715 #qcom,smem-state-cells = <1>;
718 smp2p_cdsp_in: slave-kernel {
719 qcom,entry-name = "slave-kernel";
720 interrupt-controller;
721 #interrupt-cells = <2>;
725 smp2p-modem {
728 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
734 qcom,local-pid = <0>;
735 qcom,remote-pid = <1>;
737 smp2p_modem_out: master-kernel {
738 qcom,entry-name = "master-kernel";
739 #qcom,smem-state-cells = <1>;
742 smp2p_modem_in: slave-kernel {
743 qcom,entry-name = "slave-kernel";
744 interrupt-controller;
745 #interrupt-cells = <2>;
748 ipa_smp2p_out: ipa-ap-to-modem {
749 qcom,entry-name = "ipa";
750 #qcom,smem-state-cells = <1>;
753 ipa_smp2p_in: ipa-modem-to-ap {
754 qcom,entry-name = "ipa";
755 interrupt-controller;
756 #interrupt-cells = <2>;
761 compatible = "simple-bus";
763 dma-ranges = <0 0 0 0 0x10 0>;
765 #address-cells = <2>;
766 #size-cells = <2>;
768 gcc: clock-controller@100000 {
769 compatible = "qcom,sm8550-gcc";
771 #clock-cells = <1>;
772 #reset-cells = <1>;
773 #power-domain-cells = <1>;
785 compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
788 interrupt-controller;
789 #interrupt-cells = <3>;
790 #mbox-cells = <2>;
793 gpi_dma2: dma-controller@800000 {
794 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
795 #dma-cells = <3>;
809 dma-channels = <12>;
810 dma-channel-mask = <0x3e>;
816 compatible = "qcom,geni-se-qup";
819 clock-names = "m-ahb", "s-ahb";
823 #address-cells = <2>;
824 #size-cells = <2>;
828 compatible = "qcom,geni-i2c";
830 clock-names = "se";
832 pinctrl-names = "default";
833 pinctrl-0 = <&qup_i2c8_data_clk>;
835 #address-cells = <1>;
836 #size-cells = <0>;
840 interconnect-names = "qup-core", "qup-config", "qup-memory";
843 dma-names = "tx", "rx";
848 compatible = "qcom,geni-spi";
850 clock-names = "se";
853 pinctrl-names = "default";
854 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
858 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dma-names = "tx", "rx";
862 #address-cells = <1>;
863 #size-cells = <0>;
868 compatible = "qcom,geni-i2c";
870 clock-names = "se";
872 pinctrl-names = "default";
873 pinctrl-0 = <&qup_i2c9_data_clk>;
875 #address-cells = <1>;
876 #size-cells = <0>;
880 interconnect-names = "qup-core", "qup-config", "qup-memory";
883 dma-names = "tx", "rx";
888 compatible = "qcom,geni-spi";
890 clock-names = "se";
893 pinctrl-names = "default";
894 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
898 interconnect-names = "qup-core", "qup-config", "qup-memory";
901 dma-names = "tx", "rx";
902 #address-cells = <1>;
903 #size-cells = <0>;
908 compatible = "qcom,geni-i2c";
910 clock-names = "se";
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_i2c10_data_clk>;
915 #address-cells = <1>;
916 #size-cells = <0>;
920 interconnect-names = "qup-core", "qup-config", "qup-memory";
923 dma-names = "tx", "rx";
928 compatible = "qcom,geni-spi";
930 clock-names = "se";
933 pinctrl-names = "default";
934 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
938 interconnect-names = "qup-core", "qup-config", "qup-memory";
941 dma-names = "tx", "rx";
942 #address-cells = <1>;
943 #size-cells = <0>;
948 compatible = "qcom,geni-i2c";
950 clock-names = "se";
952 pinctrl-names = "default";
953 pinctrl-0 = <&qup_i2c11_data_clk>;
955 #address-cells = <1>;
956 #size-cells = <0>;
960 interconnect-names = "qup-core", "qup-config", "qup-memory";
963 dma-names = "tx", "rx";
968 compatible = "qcom,geni-spi";
970 clock-names = "se";
973 pinctrl-names = "default";
974 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
978 interconnect-names = "qup-core", "qup-config", "qup-memory";
981 dma-names = "tx", "rx";
982 #address-cells = <1>;
983 #size-cells = <0>;
988 compatible = "qcom,geni-i2c";
990 clock-names = "se";
992 pinctrl-names = "default";
993 pinctrl-0 = <&qup_i2c12_data_clk>;
995 #address-cells = <1>;
996 #size-cells = <0>;
1000 interconnect-names = "qup-core", "qup-config", "qup-memory";
1003 dma-names = "tx", "rx";
1008 compatible = "qcom,geni-spi";
1010 clock-names = "se";
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1018 interconnect-names = "qup-core", "qup-config", "qup-memory";
1021 dma-names = "tx", "rx";
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1028 compatible = "qcom,geni-i2c";
1030 clock-names = "se";
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&qup_i2c13_data_clk>;
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1040 interconnect-names = "qup-core", "qup-config", "qup-memory";
1043 dma-names = "tx", "rx";
1048 compatible = "qcom,geni-spi";
1050 clock-names = "se";
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1058 interconnect-names = "qup-core", "qup-config", "qup-memory";
1061 dma-names = "tx", "rx";
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1068 compatible = "qcom,geni-i2c";
1070 clock-names = "se";
1072 pinctrl-names = "default";
1073 pinctrl-0 = <&qup_i2c15_data_clk>;
1075 #address-cells = <1>;
1076 #size-cells = <0>;
1080 interconnect-names = "qup-core", "qup-config", "qup-memory";
1083 dma-names = "tx", "rx";
1088 compatible = "qcom,geni-spi";
1090 clock-names = "se";
1093 pinctrl-names = "default";
1094 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1098 interconnect-names = "qup-core", "qup-config", "qup-memory";
1101 dma-names = "tx", "rx";
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1109 compatible = "qcom,geni-se-i2c-master-hub";
1111 clock-names = "s-ahb";
1113 #address-cells = <2>;
1114 #size-cells = <2>;
1119 compatible = "qcom,geni-i2c-master-hub";
1121 clock-names = "se", "core";
1124 pinctrl-names = "default";
1125 pinctrl-0 = <&hub_i2c0_data_clk>;
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1131 interconnect-names = "qup-core", "qup-config";
1136 compatible = "qcom,geni-i2c-master-hub";
1138 clock-names = "se", "core";
1141 pinctrl-names = "default";
1142 pinctrl-0 = <&hub_i2c1_data_clk>;
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1148 interconnect-names = "qup-core", "qup-config";
1153 compatible = "qcom,geni-i2c-master-hub";
1155 clock-names = "se", "core";
1158 pinctrl-names = "default";
1159 pinctrl-0 = <&hub_i2c2_data_clk>;
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1165 interconnect-names = "qup-core", "qup-config";
1170 compatible = "qcom,geni-i2c-master-hub";
1172 clock-names = "se", "core";
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&hub_i2c3_data_clk>;
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1182 interconnect-names = "qup-core", "qup-config";
1187 compatible = "qcom,geni-i2c-master-hub";
1189 clock-names = "se", "core";
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&hub_i2c4_data_clk>;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1199 interconnect-names = "qup-core", "qup-config";
1204 compatible = "qcom,geni-i2c-master-hub";
1206 clock-names = "se", "core";
1209 pinctrl-names = "default";
1210 pinctrl-0 = <&hub_i2c5_data_clk>;
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1216 interconnect-names = "qup-core", "qup-config";
1221 compatible = "qcom,geni-i2c-master-hub";
1223 clock-names = "se", "core";
1226 pinctrl-names = "default";
1227 pinctrl-0 = <&hub_i2c6_data_clk>;
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1233 interconnect-names = "qup-core", "qup-config";
1238 compatible = "qcom,geni-i2c-master-hub";
1240 clock-names = "se", "core";
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&hub_i2c7_data_clk>;
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1250 interconnect-names = "qup-core", "qup-config";
1255 compatible = "qcom,geni-i2c-master-hub";
1257 clock-names = "se", "core";
1260 pinctrl-names = "default";
1261 pinctrl-0 = <&hub_i2c8_data_clk>;
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1267 interconnect-names = "qup-core", "qup-config";
1272 compatible = "qcom,geni-i2c-master-hub";
1274 clock-names = "se", "core";
1277 pinctrl-names = "default";
1278 pinctrl-0 = <&hub_i2c9_data_clk>;
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1284 interconnect-names = "qup-core", "qup-config";
1289 gpi_dma1: dma-controller@a00000 {
1290 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1291 #dma-cells = <3>;
1305 dma-channels = <12>;
1306 dma-channel-mask = <0x1e>;
1312 compatible = "qcom,geni-se-qup";
1315 clock-names = "m-ahb", "s-ahb";
1320 interconnect-names = "qup-core";
1321 #address-cells = <2>;
1322 #size-cells = <2>;
1326 compatible = "qcom,geni-i2c";
1328 clock-names = "se";
1330 pinctrl-names = "default";
1331 pinctrl-0 = <&qup_i2c0_data_clk>;
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1338 interconnect-names = "qup-core", "qup-config", "qup-memory";
1341 dma-names = "tx", "rx";
1346 compatible = "qcom,geni-spi";
1348 clock-names = "se";
1351 pinctrl-names = "default";
1352 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1356 interconnect-names = "qup-core", "qup-config", "qup-memory";
1359 dma-names = "tx", "rx";
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1366 compatible = "qcom,geni-i2c";
1368 clock-names = "se";
1370 pinctrl-names = "default";
1371 pinctrl-0 = <&qup_i2c1_data_clk>;
1373 #address-cells = <1>;
1374 #size-cells = <0>;
1378 interconnect-names = "qup-core", "qup-config", "qup-memory";
1381 dma-names = "tx", "rx";
1386 compatible = "qcom,geni-spi";
1388 clock-names = "se";
1391 pinctrl-names = "default";
1392 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1396 interconnect-names = "qup-core", "qup-config", "qup-memory";
1399 dma-names = "tx", "rx";
1400 #address-cells = <1>;
1401 #size-cells = <0>;
1406 compatible = "qcom,geni-i2c";
1408 clock-names = "se";
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&qup_i2c2_data_clk>;
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1418 interconnect-names = "qup-core", "qup-config", "qup-memory";
1421 dma-names = "tx", "rx";
1426 compatible = "qcom,geni-spi";
1428 clock-names = "se";
1431 pinctrl-names = "default";
1432 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1436 interconnect-names = "qup-core", "qup-config", "qup-memory";
1439 dma-names = "tx", "rx";
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1446 compatible = "qcom,geni-i2c";
1448 clock-names = "se";
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&qup_i2c3_data_clk>;
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1458 interconnect-names = "qup-core", "qup-config", "qup-memory";
1461 dma-names = "tx", "rx";
1466 compatible = "qcom,geni-spi";
1468 clock-names = "se";
1471 pinctrl-names = "default";
1472 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1476 interconnect-names = "qup-core", "qup-config", "qup-memory";
1479 dma-names = "tx", "rx";
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1486 compatible = "qcom,geni-i2c";
1488 clock-names = "se";
1490 pinctrl-names = "default";
1491 pinctrl-0 = <&qup_i2c4_data_clk>;
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1498 interconnect-names = "qup-core", "qup-config", "qup-memory";
1501 dma-names = "tx", "rx";
1506 compatible = "qcom,geni-spi";
1508 clock-names = "se";
1511 pinctrl-names = "default";
1512 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1516 interconnect-names = "qup-core", "qup-config", "qup-memory";
1519 dma-names = "tx", "rx";
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1526 compatible = "qcom,geni-i2c";
1528 clock-names = "se";
1530 pinctrl-names = "default";
1531 pinctrl-0 = <&qup_i2c5_data_clk>;
1536 interconnect-names = "qup-core", "qup-config", "qup-memory";
1539 dma-names = "tx", "rx";
1540 #address-cells = <1>;
1541 #size-cells = <0>;
1546 compatible = "qcom,geni-spi";
1548 clock-names = "se";
1551 pinctrl-names = "default";
1552 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1556 interconnect-names = "qup-core", "qup-config", "qup-memory";
1559 dma-names = "tx", "rx";
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1566 compatible = "qcom,geni-i2c";
1568 clock-names = "se";
1570 pinctrl-names = "default";
1571 pinctrl-0 = <&qup_i2c6_data_clk>;
1576 interconnect-names = "qup-core", "qup-config", "qup-memory";
1579 dma-names = "tx", "rx";
1580 #address-cells = <1>;
1581 #size-cells = <0>;
1586 compatible = "qcom,geni-spi";
1588 clock-names = "se";
1591 pinctrl-names = "default";
1592 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1596 interconnect-names = "qup-core", "qup-config", "qup-memory";
1599 dma-names = "tx", "rx";
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1606 compatible = "qcom,geni-debug-uart";
1608 clock-names = "se";
1610 pinctrl-names = "default";
1611 pinctrl-0 = <&qup_uart7_default>;
1613 interconnect-names = "qup-core", "qup-config";
1621 compatible = "qcom,sm8550-cnoc-main";
1623 #interconnect-cells = <2>;
1624 qcom,bcm-voters = <&apps_bcm_voter>;
1628 compatible = "qcom,sm8550-config-noc";
1630 #interconnect-cells = <2>;
1631 qcom,bcm-voters = <&apps_bcm_voter>;
1635 compatible = "qcom,sm8550-system-noc";
1637 #interconnect-cells = <2>;
1638 qcom,bcm-voters = <&apps_bcm_voter>;
1642 compatible = "qcom,sm8550-pcie-anoc";
1644 #interconnect-cells = <2>;
1647 qcom,bcm-voters = <&apps_bcm_voter>;
1651 compatible = "qcom,sm8550-aggre1-noc";
1653 #interconnect-cells = <2>;
1656 qcom,bcm-voters = <&apps_bcm_voter>;
1660 compatible = "qcom,sm8550-aggre2-noc";
1662 #interconnect-cells = <2>;
1664 qcom,bcm-voters = <&apps_bcm_voter>;
1668 compatible = "qcom,sm8550-mmss-noc";
1670 #interconnect-cells = <2>;
1671 qcom,bcm-voters = <&apps_bcm_voter>;
1676 compatible = "qcom,pcie-sm8550";
1682 reg-names = "parf", "dbi", "elbi", "atu", "config";
1683 #address-cells = <3>;
1684 #size-cells = <2>;
1687 bus-range = <0x00 0xff>;
1689 dma-coherent;
1691 linux,pci-domain = <0>;
1692 num-lanes = <2>;
1695 interrupt-names = "msi";
1697 #interrupt-cells = <1>;
1698 interrupt-map-mask = <0 0 0 0x7>;
1699 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1711 clock-names = "aux",
1721 interconnect-names = "pcie-mem", "cpu-pcie";
1723 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1727 reset-names = "pci";
1729 power-domains = <&gcc PCIE_0_GDSC>;
1732 phy-names = "pciephy";
1738 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1746 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1750 reset-names = "phy";
1752 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1753 assigned-clock-rates = <100000000>;
1755 power-domains = <&gcc PCIE_0_PHY_GDSC>;
1757 #clock-cells = <0>;
1758 clock-output-names = "pcie0_pipe_clk";
1760 #phy-cells = <0>;
1767 compatible = "qcom,pcie-sm8550";
1773 reg-names = "parf", "dbi", "elbi", "atu", "config";
1774 #address-cells = <3>;
1775 #size-cells = <2>;
1778 bus-range = <0x00 0xff>;
1780 dma-coherent;
1782 linux,pci-domain = <1>;
1783 num-lanes = <2>;
1786 interrupt-names = "msi";
1788 #interrupt-cells = <1>;
1789 interrupt-map-mask = <0 0 0 0x7>;
1790 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1803 clock-names = "aux",
1812 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1813 assigned-clock-rates = <19200000>;
1817 interconnect-names = "pcie-mem", "cpu-pcie";
1819 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1824 reset-names = "pci", "link_down";
1826 power-domains = <&gcc PCIE_1_GDSC>;
1829 phy-names = "pciephy";
1835 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1843 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1848 reset-names = "phy", "phy_nocsr";
1850 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1851 assigned-clock-rates = <100000000>;
1853 power-domains = <&gcc PCIE_1_PHY_GDSC>;
1855 #clock-cells = <0>;
1856 clock-output-names = "pcie1_pipe_clk";
1858 #phy-cells = <0>;
1863 cryptobam: dma-controller@1dc4000 {
1864 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1867 #dma-cells = <1>;
1869 qcom,controlled-remotely;
1875 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1878 dma-names = "rx", "tx";
1882 interconnect-names = "memory";
1886 compatible = "qcom,sm8550-qmp-ufs-phy";
1890 clock-names = "ref", "ref_aux";
1892 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1895 reset-names = "ufsphy";
1897 #clock-cells = <1>;
1898 #phy-cells = <0>;
1904 compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1905 "jedec,ufs-2.0";
1909 phy-names = "ufsphy";
1910 lanes-per-direction = <2>;
1911 #reset-cells = <1>;
1913 reset-names = "rst";
1915 power-domains = <&gcc UFS_PHY_GDSC>;
1916 required-opps = <&rpmhpd_opp_nom>;
1919 dma-coherent;
1924 interconnect-names = "ufs-ddr", "cpu-ufs";
1925 clock-names = "core_clk",
1941 freq-table-hz =
1956 compatible = "qcom,sm8550-inline-crypto-engine",
1957 "qcom,inline-crypto-engine";
1963 compatible = "qcom,tcsr-mutex";
1965 #hwlock-cells = <1>;
1968 tcsr: clock-controller@1fc0000 {
1969 compatible = "qcom,sm8550-tcsr", "syscon";
1972 #clock-cells = <1>;
1973 #reset-cells = <1>;
1976 gpucc: clock-controller@3d90000 {
1977 compatible = "qcom,sm8550-gpucc";
1982 #clock-cells = <1>;
1983 #reset-cells = <1>;
1984 #power-domain-cells = <1>;
1988 compatible = "qcom,sm8550-mpss-pas";
1991 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
1997 interrupt-names = "wdog", "fatal", "ready", "handover",
1998 "stop-ack", "shutdown-ack";
2001 clock-names = "xo";
2003 power-domains = <&rpmhpd RPMHPD_CX>,
2005 power-domain-names = "cx", "mss";
2009 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2013 qcom,smem-states = <&smp2p_modem_out 0>;
2014 qcom,smem-state-names = "stop";
2018 glink-edge {
2019 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2025 qcom,remote-pid = <1>;
2030 compatible = "qcom,sm8550-lpass-wsa-macro";
2036 clock-names = "mclk", "macro", "dcodec", "fsgen";
2037 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2038 assigned-clock-rates = <19200000>;
2040 #clock-cells = <0>;
2041 clock-output-names = "wsa2-mclk";
2042 pinctrl-names = "default";
2043 pinctrl-0 = <&wsa2_swr_active>;
2044 #sound-dai-cells = <1>;
2048 compatible = "qcom,soundwire-v2.0.0";
2052 clock-names = "iface";
2055 qcom,din-ports = <4>;
2056 qcom,dout-ports = <9>;
2058 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2059 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2060 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2061 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2062 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2063 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2064 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2065 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2066 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2068 #address-cells = <2>;
2069 #size-cells = <0>;
2070 #sound-dai-cells = <1>;
2075 compatible = "qcom,sm8550-lpass-rx-macro";
2081 clock-names = "mclk", "macro", "dcodec", "fsgen";
2083 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2084 assigned-clock-rates = <19200000>;
2086 #clock-cells = <0>;
2087 clock-output-names = "mclk";
2088 pinctrl-names = "default";
2089 pinctrl-0 = <&rx_swr_active>;
2090 #sound-dai-cells = <1>;
2094 compatible = "qcom,soundwire-v2.0.0";
2098 clock-names = "iface";
2101 qcom,din-ports = <0>;
2102 qcom,dout-ports = <10>;
2104 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
2105 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
2106 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2107 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2108 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2109 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>;
2110 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>;
2111 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2112 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2114 #address-cells = <2>;
2115 #size-cells = <0>;
2116 #sound-dai-cells = <1>;
2121 compatible = "qcom,sm8550-lpass-tx-macro";
2127 clock-names = "mclk", "macro", "dcodec", "fsgen";
2128 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2130 assigned-clock-rates = <19200000>;
2132 #clock-cells = <0>;
2133 clock-output-names = "mclk";
2134 pinctrl-names = "default";
2135 pinctrl-0 = <&tx_swr_active>;
2136 #sound-dai-cells = <1>;
2140 compatible = "qcom,sm8550-lpass-wsa-macro";
2146 clock-names = "mclk", "macro", "dcodec", "fsgen";
2148 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2149 assigned-clock-rates = <19200000>;
2151 #clock-cells = <0>;
2152 clock-output-names = "mclk";
2153 pinctrl-names = "default";
2154 pinctrl-0 = <&wsa_swr_active>;
2155 #sound-dai-cells = <1>;
2159 compatible = "qcom,soundwire-v2.0.0";
2163 clock-names = "iface";
2166 qcom,din-ports = <4>;
2167 qcom,dout-ports = <9>;
2169 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2170 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2171 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2172 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2173 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2174 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2175 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2176 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2177 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2179 #address-cells = <2>;
2180 #size-cells = <0>;
2181 #sound-dai-cells = <1>;
2186 compatible = "qcom,soundwire-v2.0.0";
2190 interrupt-names = "core", "wakeup";
2192 clock-names = "iface";
2195 qcom,din-ports = <4>;
2196 qcom,dout-ports = <0>;
2197 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2198 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2199 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2200 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2201 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2202 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2203 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2204 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2205 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2207 #address-cells = <2>;
2208 #size-cells = <0>;
2209 #sound-dai-cells = <1>;
2214 compatible = "qcom,sm8550-lpass-va-macro";
2219 clock-names = "mclk", "macro", "dcodec";
2221 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2222 assigned-clock-rates = <19200000>;
2224 #clock-cells = <0>;
2225 clock-output-names = "fsgen";
2226 #sound-dai-cells = <1>;
2230 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2233 gpio-controller;
2234 #gpio-cells = <2>;
2235 gpio-ranges = <&lpass_tlmm 0 0 23>;
2239 clock-names = "core", "audio";
2241 tx_swr_active: tx-swr-active-state {
2242 clk-pins {
2245 drive-strength = <2>;
2246 slew-rate = <1>;
2247 bias-disable;
2250 data-pins {
2253 drive-strength = <2>;
2254 slew-rate = <1>;
2255 bias-bus-hold;
2259 rx_swr_active: rx-swr-active-state {
2260 clk-pins {
2263 drive-strength = <2>;
2264 slew-rate = <1>;
2265 bias-disable;
2268 data-pins {
2271 drive-strength = <2>;
2272 slew-rate = <1>;
2273 bias-bus-hold;
2277 dmic01_default: dmic01-default-state {
2278 clk-pins {
2281 drive-strength = <8>;
2282 output-high;
2285 data-pins {
2288 drive-strength = <8>;
2289 input-enable;
2293 dmic02_default: dmic02-default-state {
2294 clk-pins {
2297 drive-strength = <8>;
2298 output-high;
2301 data-pins {
2304 drive-strength = <8>;
2305 input-enable;
2309 wsa_swr_active: wsa-swr-active-state {
2310 clk-pins {
2313 drive-strength = <2>;
2314 slew-rate = <1>;
2315 bias-disable;
2318 data-pins {
2321 drive-strength = <2>;
2322 slew-rate = <1>;
2323 bias-bus-hold;
2327 wsa2_swr_active: wsa2-swr-active-state {
2328 clk-pins {
2331 drive-strength = <2>;
2332 slew-rate = <1>;
2333 bias-disable;
2336 data-pins {
2339 drive-strength = <2>;
2340 slew-rate = <1>;
2341 bias-bus-hold;
2347 compatible = "qcom,sm8550-lpass-lpiaon-noc";
2349 #interconnect-cells = <2>;
2350 qcom,bcm-voters = <&apps_bcm_voter>;
2354 compatible = "qcom,sm8550-lpass-lpicx-noc";
2356 #interconnect-cells = <2>;
2357 qcom,bcm-voters = <&apps_bcm_voter>;
2361 compatible = "qcom,sm8550-lpass-ag-noc";
2363 #interconnect-cells = <2>;
2364 qcom,bcm-voters = <&apps_bcm_voter>;
2368 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2373 interrupt-names = "hc_irq", "pwr_irq";
2378 clock-names = "iface", "core", "xo";
2380 qcom,dll-config = <0x0007642c>;
2381 qcom,ddr-config = <0x80040868>;
2382 power-domains = <&rpmhpd RPMHPD_CX>;
2383 operating-points-v2 = <&sdhc2_opp_table>;
2387 interconnect-names = "sdhc-ddr", "cpu-sdhc";
2388 bus-width = <4>;
2389 dma-coherent;
2391 /* Forbid SDR104/SDR50 - broken hw! */
2392 sdhci-caps-mask = <0x3 0>;
2396 sdhc2_opp_table: opp-table {
2397 compatible = "operating-points-v2";
2399 opp-19200000 {
2400 opp-hz = /bits/ 64 <19200000>;
2401 required-opps = <&rpmhpd_opp_min_svs>;
2404 opp-50000000 {
2405 opp-hz = /bits/ 64 <50000000>;
2406 required-opps = <&rpmhpd_opp_low_svs>;
2409 opp-100000000 {
2410 opp-hz = /bits/ 64 <100000000>;
2411 required-opps = <&rpmhpd_opp_svs>;
2414 opp-202000000 {
2415 opp-hz = /bits/ 64 <202000000>;
2416 required-opps = <&rpmhpd_opp_svs_l1>;
2421 videocc: clock-controller@aaf0000 {
2422 compatible = "qcom,sm8550-videocc";
2426 power-domains = <&rpmhpd RPMHPD_MMCX>;
2427 required-opps = <&rpmhpd_opp_low_svs>;
2428 #clock-cells = <1>;
2429 #reset-cells = <1>;
2430 #power-domain-cells = <1>;
2433 mdss: display-subsystem@ae00000 { label
2434 compatible = "qcom,sm8550-mdss";
2436 reg-names = "mdss";
2439 interrupt-controller;
2440 #interrupt-cells = <1>;
2449 power-domains = <&dispcc MDSS_GDSC>;
2453 interconnect-names = "mdp0-mem", "mdp1-mem";
2457 #address-cells = <2>;
2458 #size-cells = <2>;
2463 mdss_mdp: display-controller@ae01000 {
2464 compatible = "qcom,sm8550-dpu";
2467 reg-names = "mdp", "vbif";
2469 interrupt-parent = <&mdss>;
2478 clock-names = "bus",
2485 power-domains = <&rpmhpd RPMHPD_MMCX>;
2487 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2488 assigned-clock-rates = <19200000>;
2490 operating-points-v2 = <&mdp_opp_table>;
2493 #address-cells = <1>;
2494 #size-cells = <0>;
2499 remote-endpoint = <&mdss_dsi0_in>;
2506 remote-endpoint = <&mdss_dsi1_in>;
2513 remote-endpoint = <&mdss_dp0_in>;
2518 mdp_opp_table: opp-table {
2519 compatible = "operating-points-v2";
2521 opp-200000000 {
2522 opp-hz = /bits/ 64 <200000000>;
2523 required-opps = <&rpmhpd_opp_low_svs>;
2526 opp-325000000 {
2527 opp-hz = /bits/ 64 <325000000>;
2528 required-opps = <&rpmhpd_opp_svs>;
2531 opp-375000000 {
2532 opp-hz = /bits/ 64 <375000000>;
2533 required-opps = <&rpmhpd_opp_svs_l1>;
2536 opp-514000000 {
2537 opp-hz = /bits/ 64 <514000000>;
2538 required-opps = <&rpmhpd_opp_nom>;
2543 mdss_dp0: displayport-controller@ae90000 {
2544 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
2550 interrupt-parent = <&mdss>;
2557 clock-names = "core_iface",
2563 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2565 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2569 phy-names = "dp";
2571 #sound-dai-cells = <0>;
2573 operating-points-v2 = <&dp_opp_table>;
2574 power-domains = <&rpmhpd RPMHPD_MMCX>;
2579 #address-cells = <1>;
2580 #size-cells = <0>;
2585 remote-endpoint = <&dpu_intf0_out>;
2596 dp_opp_table: opp-table {
2597 compatible = "operating-points-v2";
2599 opp-162000000 {
2600 opp-hz = /bits/ 64 <162000000>;
2601 required-opps = <&rpmhpd_opp_low_svs_d1>;
2604 opp-270000000 {
2605 opp-hz = /bits/ 64 <270000000>;
2606 required-opps = <&rpmhpd_opp_low_svs>;
2609 opp-540000000 {
2610 opp-hz = /bits/ 64 <540000000>;
2611 required-opps = <&rpmhpd_opp_svs_l1>;
2614 opp-810000000 {
2615 opp-hz = /bits/ 64 <810000000>;
2616 required-opps = <&rpmhpd_opp_nom>;
2622 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2624 reg-names = "dsi_ctrl";
2626 interrupt-parent = <&mdss>;
2635 clock-names = "byte",
2642 power-domains = <&rpmhpd RPMHPD_MMCX>;
2644 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2646 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2649 operating-points-v2 = <&mdss_dsi_opp_table>;
2652 phy-names = "dsi";
2654 #address-cells = <1>;
2655 #size-cells = <0>;
2660 #address-cells = <1>;
2661 #size-cells = <0>;
2666 remote-endpoint = <&dpu_intf1_out>;
2677 mdss_dsi_opp_table: opp-table {
2678 compatible = "operating-points-v2";
2680 opp-187500000 {
2681 opp-hz = /bits/ 64 <187500000>;
2682 required-opps = <&rpmhpd_opp_low_svs>;
2685 opp-300000000 {
2686 opp-hz = /bits/ 64 <300000000>;
2687 required-opps = <&rpmhpd_opp_svs>;
2690 opp-358000000 {
2691 opp-hz = /bits/ 64 <358000000>;
2692 required-opps = <&rpmhpd_opp_svs_l1>;
2698 compatible = "qcom,sm8550-dsi-phy-4nm";
2702 reg-names = "dsi_phy",
2708 clock-names = "iface", "ref";
2710 #clock-cells = <1>;
2711 #phy-cells = <0>;
2717 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2719 reg-names = "dsi_ctrl";
2721 interrupt-parent = <&mdss>;
2730 clock-names = "byte",
2737 power-domains = <&rpmhpd RPMHPD_MMCX>;
2739 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2741 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2744 operating-points-v2 = <&mdss_dsi_opp_table>;
2747 phy-names = "dsi";
2749 #address-cells = <1>;
2750 #size-cells = <0>;
2755 #address-cells = <1>;
2756 #size-cells = <0>;
2761 remote-endpoint = <&dpu_intf2_out>;
2774 compatible = "qcom,sm8550-dsi-phy-4nm";
2778 reg-names = "dsi_phy",
2784 clock-names = "iface", "ref";
2786 #clock-cells = <1>;
2787 #phy-cells = <0>;
2793 dispcc: clock-controller@af00000 {
2794 compatible = "qcom,sm8550-dispcc";
2812 power-domains = <&rpmhpd RPMHPD_MMCX>;
2813 required-opps = <&rpmhpd_opp_low_svs>;
2814 #clock-cells = <1>;
2815 #reset-cells = <1>;
2816 #power-domain-cells = <1>;
2820 compatible = "qcom,sm8550-snps-eusb2-phy";
2822 #phy-cells = <0>;
2825 clock-names = "ref";
2833 compatible = "qcom,sm8550-qmp-usb3-dp-phy";
2840 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2842 power-domains = <&gcc USB3_PHY_GDSC>;
2846 reset-names = "phy", "common";
2848 #clock-cells = <1>;
2849 #phy-cells = <1>;
2854 #address-cells = <1>;
2855 #size-cells = <0>;
2881 compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
2883 #address-cells = <2>;
2884 #size-cells = <2>;
2893 clock-names = "cfg_noc",
2900 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2902 assigned-clock-rates = <19200000>, <200000000>;
2904 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2908 interrupt-names = "hs_phy_irq",
2913 power-domains = <&gcc USB30_PRIM_GDSC>;
2914 required-opps = <&rpmhpd_opp_nom>;
2920 interconnect-names = "usb-ddr", "apps-usb";
2934 phy-names = "usb2-phy", "usb3-phy";
2937 #address-cells = <1>;
2938 #size-cells = <0>;
2957 pdc: interrupt-controller@b220000 {
2958 compatible = "qcom,sm8550-pdc", "qcom,pdc";
2960 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2963 #interrupt-cells = <2>;
2964 interrupt-parent = <&intc>;
2965 interrupt-controller;
2968 tsens0: thermal-sensor@c271000 {
2969 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2975 interrupt-names = "uplow", "critical";
2976 #thermal-sensor-cells = <1>;
2979 tsens1: thermal-sensor@c272000 {
2980 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2986 interrupt-names = "uplow", "critical";
2987 #thermal-sensor-cells = <1>;
2990 tsens2: thermal-sensor@c273000 {
2991 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2997 interrupt-names = "uplow", "critical";
2998 #thermal-sensor-cells = <1>;
3001 aoss_qmp: power-management@c300000 {
3002 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
3004 interrupt-parent = <&ipcc>;
3005 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3009 #clock-cells = <0>;
3013 compatible = "qcom,rpmh-stats";
3018 compatible = "qcom,spmi-pmic-arb";
3024 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3025 interrupt-names = "periph_irq";
3026 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3029 qcom,bus-id = <0>;
3030 #address-cells = <2>;
3031 #size-cells = <0>;
3032 interrupt-controller;
3033 #interrupt-cells = <4>;
3037 compatible = "qcom,sm8550-tlmm";
3040 gpio-controller;
3041 #gpio-cells = <2>;
3042 interrupt-controller;
3043 #interrupt-cells = <2>;
3044 gpio-ranges = <&tlmm 0 0 211>;
3045 wakeup-parent = <&pdc>;
3047 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3051 drive-strength = <2>;
3052 bias-pull-up;
3055 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3059 drive-strength = <2>;
3060 bias-pull-up;
3063 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3067 drive-strength = <2>;
3068 bias-pull-up;
3071 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3075 drive-strength = <2>;
3076 bias-pull-up;
3079 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3083 drive-strength = <2>;
3084 bias-pull-up;
3087 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3091 drive-strength = <2>;
3092 bias-pull-up;
3095 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3099 drive-strength = <2>;
3100 bias-pull-up;
3103 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3107 drive-strength = <2>;
3108 bias-pull-up;
3111 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3115 drive-strength = <2>;
3116 bias-pull-up;
3119 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3123 drive-strength = <2>;
3124 bias-pull-up;
3127 pcie0_default_state: pcie0-default-state {
3128 perst-pins {
3131 drive-strength = <2>;
3132 bias-pull-down;
3135 clkreq-pins {
3138 drive-strength = <2>;
3139 bias-pull-up;
3142 wake-pins {
3145 drive-strength = <2>;
3146 bias-pull-up;
3150 pcie1_default_state: pcie1-default-state {
3151 perst-pins {
3154 drive-strength = <2>;
3155 bias-pull-down;
3158 clkreq-pins {
3161 drive-strength = <2>;
3162 bias-pull-up;
3165 wake-pins {
3168 drive-strength = <2>;
3169 bias-pull-up;
3173 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3177 drive-strength = <2>;
3178 bias-pull-up = <2200>;
3181 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3185 drive-strength = <2>;
3186 bias-pull-up = <2200>;
3189 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3193 drive-strength = <2>;
3194 bias-pull-up = <2200>;
3197 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3201 drive-strength = <2>;
3202 bias-pull-up = <2200>;
3205 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3209 drive-strength = <2>;
3210 bias-pull-up = <2200>;
3213 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3217 drive-strength = <2>;
3218 bias-pull-up = <2200>;
3221 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3225 drive-strength = <2>;
3226 bias-pull-up = <2200>;
3229 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3230 scl-pins {
3233 drive-strength = <2>;
3234 bias-pull-up = <2200>;
3237 sda-pins {
3240 drive-strength = <2>;
3241 bias-pull-up = <2200>;
3245 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3249 drive-strength = <2>;
3250 bias-pull-up = <2200>;
3253 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3257 drive-strength = <2>;
3258 bias-pull-up = <2200>;
3261 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3265 drive-strength = <2>;
3266 bias-pull-up = <2200>;
3269 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3273 drive-strength = <2>;
3274 bias-pull-up = <2200>;
3277 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3281 drive-strength = <2>;
3282 bias-pull-up = <2200>;
3285 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3289 drive-strength = <2>;
3290 bias-pull-up = <2200>;
3293 qup_spi0_cs: qup-spi0-cs-state {
3296 drive-strength = <6>;
3297 bias-disable;
3300 qup_spi0_data_clk: qup-spi0-data-clk-state {
3304 drive-strength = <6>;
3305 bias-disable;
3308 qup_spi1_cs: qup-spi1-cs-state {
3311 drive-strength = <6>;
3312 bias-disable;
3315 qup_spi1_data_clk: qup-spi1-data-clk-state {
3319 drive-strength = <6>;
3320 bias-disable;
3323 qup_spi2_cs: qup-spi2-cs-state {
3326 drive-strength = <6>;
3327 bias-disable;
3330 qup_spi2_data_clk: qup-spi2-data-clk-state {
3334 drive-strength = <6>;
3335 bias-disable;
3338 qup_spi3_cs: qup-spi3-cs-state {
3341 drive-strength = <6>;
3342 bias-disable;
3345 qup_spi3_data_clk: qup-spi3-data-clk-state {
3349 drive-strength = <6>;
3350 bias-disable;
3353 qup_spi4_cs: qup-spi4-cs-state {
3356 drive-strength = <6>;
3357 bias-disable;
3360 qup_spi4_data_clk: qup-spi4-data-clk-state {
3364 drive-strength = <6>;
3365 bias-disable;
3368 qup_spi5_cs: qup-spi5-cs-state {
3371 drive-strength = <6>;
3372 bias-disable;
3375 qup_spi5_data_clk: qup-spi5-data-clk-state {
3379 drive-strength = <6>;
3380 bias-disable;
3383 qup_spi6_cs: qup-spi6-cs-state {
3386 drive-strength = <6>;
3387 bias-disable;
3390 qup_spi6_data_clk: qup-spi6-data-clk-state {
3394 drive-strength = <6>;
3395 bias-disable;
3398 qup_spi8_cs: qup-spi8-cs-state {
3401 drive-strength = <6>;
3402 bias-disable;
3405 qup_spi8_data_clk: qup-spi8-data-clk-state {
3409 drive-strength = <6>;
3410 bias-disable;
3413 qup_spi9_cs: qup-spi9-cs-state {
3416 drive-strength = <6>;
3417 bias-disable;
3420 qup_spi9_data_clk: qup-spi9-data-clk-state {
3424 drive-strength = <6>;
3425 bias-disable;
3428 qup_spi10_cs: qup-spi10-cs-state {
3431 drive-strength = <6>;
3432 bias-disable;
3435 qup_spi10_data_clk: qup-spi10-data-clk-state {
3439 drive-strength = <6>;
3440 bias-disable;
3443 qup_spi11_cs: qup-spi11-cs-state {
3446 drive-strength = <6>;
3447 bias-disable;
3450 qup_spi11_data_clk: qup-spi11-data-clk-state {
3454 drive-strength = <6>;
3455 bias-disable;
3458 qup_spi12_cs: qup-spi12-cs-state {
3461 drive-strength = <6>;
3462 bias-disable;
3465 qup_spi12_data_clk: qup-spi12-data-clk-state {
3469 drive-strength = <6>;
3470 bias-disable;
3473 qup_spi13_cs: qup-spi13-cs-state {
3476 drive-strength = <6>;
3477 bias-disable;
3480 qup_spi13_data_clk: qup-spi13-data-clk-state {
3484 drive-strength = <6>;
3485 bias-disable;
3488 qup_spi15_cs: qup-spi15-cs-state {
3491 drive-strength = <6>;
3492 bias-disable;
3495 qup_spi15_data_clk: qup-spi15-data-clk-state {
3499 drive-strength = <6>;
3500 bias-disable;
3503 qup_uart7_default: qup-uart7-default-state {
3507 drive-strength = <2>;
3508 bias-disable;
3511 sdc2_sleep: sdc2-sleep-state {
3512 clk-pins {
3514 bias-disable;
3515 drive-strength = <2>;
3518 cmd-pins {
3520 bias-pull-up;
3521 drive-strength = <2>;
3524 data-pins {
3526 bias-pull-up;
3527 drive-strength = <2>;
3531 sdc2_default: sdc2-default-state {
3532 clk-pins {
3534 bias-disable;
3535 drive-strength = <16>;
3538 cmd-pins {
3540 bias-pull-up;
3541 drive-strength = <10>;
3544 data-pins {
3546 bias-pull-up;
3547 drive-strength = <10>;
3553 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3555 #iommu-cells = <2>;
3556 #global-interrupts = <1>;
3656 intc: interrupt-controller@17100000 {
3657 compatible = "arm,gic-v3";
3661 #interrupt-cells = <3>;
3662 interrupt-controller;
3663 #redistributor-regions = <1>;
3664 redistributor-stride = <0 0x40000>;
3666 #address-cells = <2>;
3667 #size-cells = <2>;
3669 gic_its: msi-controller@17140000 {
3670 compatible = "arm,gic-v3-its";
3672 msi-controller;
3673 #msi-cells = <1>;
3678 compatible = "arm,armv7-timer-mem";
3681 #address-cells = <1>;
3682 #size-cells = <1>;
3687 frame-number = <0>;
3694 frame-number = <1>;
3701 frame-number = <2>;
3708 frame-number = <3>;
3715 frame-number = <4>;
3722 frame-number = <5>;
3729 frame-number = <6>;
3737 compatible = "qcom,rpmh-rsc";
3742 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3746 qcom,tcs-offset = <0xd00>;
3747 qcom,drv-id = <2>;
3748 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
3750 power-domains = <&CLUSTER_PD>;
3752 apps_bcm_voter: bcm-voter {
3753 compatible = "qcom,bcm-voter";
3756 rpmhcc: clock-controller {
3757 compatible = "qcom,sm8550-rpmh-clk";
3758 #clock-cells = <1>;
3759 clock-names = "xo";
3763 rpmhpd: power-controller {
3764 compatible = "qcom,sm8550-rpmhpd";
3765 #power-domain-cells = <1>;
3766 operating-points-v2 = <&rpmhpd_opp_table>;
3768 rpmhpd_opp_table: opp-table {
3769 compatible = "operating-points-v2";
3771 rpmhpd_opp_ret: opp-16 {
3772 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3775 rpmhpd_opp_min_svs: opp-48 {
3776 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3779 rpmhpd_opp_low_svs_d2: opp-52 {
3780 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
3783 rpmhpd_opp_low_svs_d1: opp-56 {
3784 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3787 rpmhpd_opp_low_svs_d0: opp-60 {
3788 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
3791 rpmhpd_opp_low_svs: opp-64 {
3792 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3795 rpmhpd_opp_low_svs_l1: opp-80 {
3796 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
3799 rpmhpd_opp_svs: opp-128 {
3800 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3803 rpmhpd_opp_svs_l0: opp-144 {
3804 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
3807 rpmhpd_opp_svs_l1: opp-192 {
3808 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3811 rpmhpd_opp_nom: opp-256 {
3812 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3815 rpmhpd_opp_nom_l1: opp-320 {
3816 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3819 rpmhpd_opp_nom_l2: opp-336 {
3820 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3823 rpmhpd_opp_turbo: opp-384 {
3824 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3827 rpmhpd_opp_turbo_l1: opp-416 {
3828 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3835 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
3839 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3841 clock-names = "xo", "alternate";
3845 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3846 #freq-domain-cells = <1>;
3847 #clock-cells = <1>;
3851 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3856 operating-points-v2 = <&llcc_bwmon_opp_table>;
3858 llcc_bwmon_opp_table: opp-table {
3859 compatible = "operating-points-v2";
3861 opp-0 {
3862 opp-peak-kBps = <2086000>;
3865 opp-1 {
3866 opp-peak-kBps = <2929000>;
3869 opp-2 {
3870 opp-peak-kBps = <5931000>;
3873 opp-3 {
3874 opp-peak-kBps = <6515000>;
3877 opp-4 {
3878 opp-peak-kBps = <7980000>;
3881 opp-5 {
3882 opp-peak-kBps = <10437000>;
3885 opp-6 {
3886 opp-peak-kBps = <12157000>;
3889 opp-7 {
3890 opp-peak-kBps = <14060000>;
3893 opp-8 {
3894 opp-peak-kBps = <16113000>;
3900 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
3905 operating-points-v2 = <&cpu_bwmon_opp_table>;
3907 cpu_bwmon_opp_table: opp-table {
3908 compatible = "operating-points-v2";
3910 opp-0 {
3911 opp-peak-kBps = <4577000>;
3914 opp-1 {
3915 opp-peak-kBps = <7110000>;
3918 opp-2 {
3919 opp-peak-kBps = <9155000>;
3922 opp-3 {
3923 opp-peak-kBps = <12298000>;
3926 opp-4 {
3927 opp-peak-kBps = <14236000>;
3930 opp-5 {
3931 opp-peak-kBps = <16265000>;
3937 compatible = "qcom,sm8550-gem-noc";
3939 #interconnect-cells = <2>;
3940 qcom,bcm-voters = <&apps_bcm_voter>;
3943 system-cache-controller@25000000 {
3944 compatible = "qcom,sm8550-llcc";
3950 reg-names = "llcc0_base",
3959 compatible = "qcom,sm8550-adsp-pas";
3962 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3967 interrupt-names = "wdog", "fatal", "ready",
3968 "handover", "stop-ack";
3971 clock-names = "xo";
3973 power-domains = <&rpmhpd RPMHPD_LCX>,
3975 power-domain-names = "lcx", "lmx";
3979 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
3983 qcom,smem-states = <&smp2p_adsp_out 0>;
3984 qcom,smem-state-names = "stop";
3988 remoteproc_adsp_glink: glink-edge {
3989 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3996 qcom,remote-pid = <2>;
4000 qcom,glink-channels = "fastrpcglink-apps-dsp";
4002 #address-cells = <1>;
4003 #size-cells = <0>;
4005 compute-cb@3 {
4006 compatible = "qcom,fastrpc-compute-cb";
4012 compute-cb@4 {
4013 compatible = "qcom,fastrpc-compute-cb";
4019 compute-cb@5 {
4020 compatible = "qcom,fastrpc-compute-cb";
4026 compute-cb@6 {
4027 compatible = "qcom,fastrpc-compute-cb";
4033 compute-cb@7 {
4034 compatible = "qcom,fastrpc-compute-cb";
4043 qcom,glink-channels = "adsp_apps";
4046 #address-cells = <1>;
4047 #size-cells = <0>;
4052 #sound-dai-cells = <0>;
4053 qcom,protection-domain = "avs/audio",
4057 compatible = "qcom,q6apm-dais";
4063 compatible = "qcom,q6apm-lpass-dais";
4064 #sound-dai-cells = <1>;
4071 qcom,protection-domain = "avs/audio",
4074 q6prmcc: clock-controller {
4075 compatible = "qcom,q6prm-lpass-clocks";
4076 #clock-cells = <2>;
4084 compatible = "qcom,sm8550-nsp-noc";
4086 #interconnect-cells = <2>;
4087 qcom,bcm-voters = <&apps_bcm_voter>;
4091 compatible = "qcom,sm8550-cdsp-pas";
4094 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4099 interrupt-names = "wdog", "fatal", "ready",
4100 "handover", "stop-ack";
4103 clock-names = "xo";
4105 power-domains = <&rpmhpd RPMHPD_CX>,
4108 power-domain-names = "cx", "mxc", "nsp";
4112 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4116 qcom,smem-states = <&smp2p_cdsp_out 0>;
4117 qcom,smem-state-names = "stop";
4121 glink-edge {
4122 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4129 qcom,remote-pid = <5>;
4133 qcom,glink-channels = "fastrpcglink-apps-dsp";
4135 #address-cells = <1>;
4136 #size-cells = <0>;
4138 compute-cb@1 {
4139 compatible = "qcom,fastrpc-compute-cb";
4146 compute-cb@2 {
4147 compatible = "qcom,fastrpc-compute-cb";
4154 compute-cb@3 {
4155 compatible = "qcom,fastrpc-compute-cb";
4162 compute-cb@4 {
4163 compatible = "qcom,fastrpc-compute-cb";
4170 compute-cb@5 {
4171 compatible = "qcom,fastrpc-compute-cb";
4178 compute-cb@6 {
4179 compatible = "qcom,fastrpc-compute-cb";
4186 compute-cb@7 {
4187 compatible = "qcom,fastrpc-compute-cb";
4194 compute-cb@8 {
4195 compatible = "qcom,fastrpc-compute-cb";
4208 thermal-zones {
4209 aoss0-thermal {
4210 polling-delay-passive = <0>;
4211 polling-delay = <0>;
4212 thermal-sensors = <&tsens0 0>;
4215 thermal-engine-config {
4221 reset-mon-config {
4229 cpuss0-thermal {
4230 polling-delay-passive = <0>;
4231 polling-delay = <0>;
4232 thermal-sensors = <&tsens0 1>;
4235 thermal-engine-config {
4241 reset-mon-config {
4249 cpuss1-thermal {
4250 polling-delay-passive = <0>;
4251 polling-delay = <0>;
4252 thermal-sensors = <&tsens0 2>;
4255 thermal-engine-config {
4261 reset-mon-config {
4269 cpuss2-thermal {
4270 polling-delay-passive = <0>;
4271 polling-delay = <0>;
4272 thermal-sensors = <&tsens0 3>;
4275 thermal-engine-config {
4281 reset-mon-config {
4289 cpuss3-thermal {
4290 polling-delay-passive = <0>;
4291 polling-delay = <0>;
4292 thermal-sensors = <&tsens0 4>;
4295 thermal-engine-config {
4301 reset-mon-config {
4309 cpu3-top-thermal {
4310 polling-delay-passive = <0>;
4311 polling-delay = <0>;
4312 thermal-sensors = <&tsens0 5>;
4315 cpu3_top_alert0: trip-point0 {
4321 cpu3_top_alert1: trip-point1 {
4327 cpu3_top_crit: cpu-critical {
4335 cpu3-bottom-thermal {
4336 polling-delay-passive = <0>;
4337 polling-delay = <0>;
4338 thermal-sensors = <&tsens0 6>;
4341 cpu3_bottom_alert0: trip-point0 {
4347 cpu3_bottom_alert1: trip-point1 {
4353 cpu3_bottom_crit: cpu-critical {
4361 cpu4-top-thermal {
4362 polling-delay-passive = <0>;
4363 polling-delay = <0>;
4364 thermal-sensors = <&tsens0 7>;
4367 cpu4_top_alert0: trip-point0 {
4373 cpu4_top_alert1: trip-point1 {
4379 cpu4_top_crit: cpu-critical {
4387 cpu4-bottom-thermal {
4388 polling-delay-passive = <0>;
4389 polling-delay = <0>;
4390 thermal-sensors = <&tsens0 8>;
4393 cpu4_bottom_alert0: trip-point0 {
4399 cpu4_bottom_alert1: trip-point1 {
4405 cpu4_bottom_crit: cpu-critical {
4413 cpu5-top-thermal {
4414 polling-delay-passive = <0>;
4415 polling-delay = <0>;
4416 thermal-sensors = <&tsens0 9>;
4419 cpu5_top_alert0: trip-point0 {
4425 cpu5_top_alert1: trip-point1 {
4431 cpu5_top_crit: cpu-critical {
4439 cpu5-bottom-thermal {
4440 polling-delay-passive = <0>;
4441 polling-delay = <0>;
4442 thermal-sensors = <&tsens0 10>;
4445 cpu5_bottom_alert0: trip-point0 {
4451 cpu5_bottom_alert1: trip-point1 {
4457 cpu5_bottom_crit: cpu-critical {
4465 cpu6-top-thermal {
4466 polling-delay-passive = <0>;
4467 polling-delay = <0>;
4468 thermal-sensors = <&tsens0 11>;
4471 cpu6_top_alert0: trip-point0 {
4477 cpu6_top_alert1: trip-point1 {
4483 cpu6_top_crit: cpu-critical {
4491 cpu6-bottom-thermal {
4492 polling-delay-passive = <0>;
4493 polling-delay = <0>;
4494 thermal-sensors = <&tsens0 12>;
4497 cpu6_bottom_alert0: trip-point0 {
4503 cpu6_bottom_alert1: trip-point1 {
4509 cpu6_bottom_crit: cpu-critical {
4517 cpu7-top-thermal {
4518 polling-delay-passive = <0>;
4519 polling-delay = <0>;
4520 thermal-sensors = <&tsens0 13>;
4523 cpu7_top_alert0: trip-point0 {
4529 cpu7_top_alert1: trip-point1 {
4535 cpu7_top_crit: cpu-critical {
4543 cpu7-middle-thermal {
4544 polling-delay-passive = <0>;
4545 polling-delay = <0>;
4546 thermal-sensors = <&tsens0 14>;
4549 cpu7_middle_alert0: trip-point0 {
4555 cpu7_middle_alert1: trip-point1 {
4561 cpu7_middle_crit: cpu-critical {
4569 cpu7-bottom-thermal {
4570 polling-delay-passive = <0>;
4571 polling-delay = <0>;
4572 thermal-sensors = <&tsens0 15>;
4575 cpu7_bottom_alert0: trip-point0 {
4581 cpu7_bottom_alert1: trip-point1 {
4587 cpu7_bottom_crit: cpu-critical {
4595 aoss1-thermal {
4596 polling-delay-passive = <0>;
4597 polling-delay = <0>;
4598 thermal-sensors = <&tsens1 0>;
4601 thermal-engine-config {
4607 reset-mon-config {
4615 cpu0-thermal {
4616 polling-delay-passive = <0>;
4617 polling-delay = <0>;
4618 thermal-sensors = <&tsens1 1>;
4621 cpu0_alert0: trip-point0 {
4627 cpu0_alert1: trip-point1 {
4633 cpu0_crit: cpu-critical {
4641 cpu1-thermal {
4642 polling-delay-passive = <0>;
4643 polling-delay = <0>;
4644 thermal-sensors = <&tsens1 2>;
4647 cpu1_alert0: trip-point0 {
4653 cpu1_alert1: trip-point1 {
4659 cpu1_crit: cpu-critical {
4667 cpu2-thermal {
4668 polling-delay-passive = <0>;
4669 polling-delay = <0>;
4670 thermal-sensors = <&tsens1 3>;
4673 cpu2_alert0: trip-point0 {
4679 cpu2_alert1: trip-point1 {
4685 cpu2_crit: cpu-critical {
4693 cdsp0-thermal {
4694 polling-delay-passive = <10>;
4695 polling-delay = <0>;
4696 thermal-sensors = <&tsens2 4>;
4699 thermal-engine-config {
4705 thermal-hal-config {
4711 reset-mon-config {
4717 cdsp0_junction_config: junction-config {
4725 cdsp1-thermal {
4726 polling-delay-passive = <10>;
4727 polling-delay = <0>;
4728 thermal-sensors = <&tsens2 5>;
4731 thermal-engine-config {
4737 thermal-hal-config {
4743 reset-mon-config {
4749 cdsp1_junction_config: junction-config {
4757 cdsp2-thermal {
4758 polling-delay-passive = <10>;
4759 polling-delay = <0>;
4760 thermal-sensors = <&tsens2 6>;
4763 thermal-engine-config {
4769 thermal-hal-config {
4775 reset-mon-config {
4781 cdsp2_junction_config: junction-config {
4789 cdsp3-thermal {
4790 polling-delay-passive = <10>;
4791 polling-delay = <0>;
4792 thermal-sensors = <&tsens2 7>;
4795 thermal-engine-config {
4801 thermal-hal-config {
4807 reset-mon-config {
4813 cdsp3_junction_config: junction-config {
4821 video-thermal {
4822 polling-delay-passive = <0>;
4823 polling-delay = <0>;
4824 thermal-sensors = <&tsens1 8>;
4827 thermal-engine-config {
4833 reset-mon-config {
4841 mem-thermal {
4842 polling-delay-passive = <10>;
4843 polling-delay = <0>;
4844 thermal-sensors = <&tsens1 9>;
4847 thermal-engine-config {
4853 ddr_config0: ddr0-config {
4859 reset-mon-config {
4867 modem0-thermal {
4868 polling-delay-passive = <0>;
4869 polling-delay = <0>;
4870 thermal-sensors = <&tsens1 10>;
4873 thermal-engine-config {
4879 mdmss0_config0: mdmss0-config0 {
4885 mdmss0_config1: mdmss0-config1 {
4891 reset-mon-config {
4899 modem1-thermal {
4900 polling-delay-passive = <0>;
4901 polling-delay = <0>;
4902 thermal-sensors = <&tsens1 11>;
4905 thermal-engine-config {
4911 mdmss1_config0: mdmss1-config0 {
4917 mdmss1_config1: mdmss1-config1 {
4923 reset-mon-config {
4931 modem2-thermal {
4932 polling-delay-passive = <0>;
4933 polling-delay = <0>;
4934 thermal-sensors = <&tsens1 12>;
4937 thermal-engine-config {
4943 mdmss2_config0: mdmss2-config0 {
4949 mdmss2_config1: mdmss2-config1 {
4955 reset-mon-config {
4963 modem3-thermal {
4964 polling-delay-passive = <0>;
4965 polling-delay = <0>;
4966 thermal-sensors = <&tsens1 13>;
4969 thermal-engine-config {
4975 mdmss3_config0: mdmss3-config0 {
4981 mdmss3_config1: mdmss3-config1 {
4987 reset-mon-config {
4995 camera0-thermal {
4996 polling-delay-passive = <0>;
4997 polling-delay = <0>;
4998 thermal-sensors = <&tsens1 14>;
5001 thermal-engine-config {
5007 reset-mon-config {
5015 camera1-thermal {
5016 polling-delay-passive = <0>;
5017 polling-delay = <0>;
5018 thermal-sensors = <&tsens1 15>;
5021 thermal-engine-config {
5027 reset-mon-config {
5035 aoss2-thermal {
5036 polling-delay-passive = <0>;
5037 polling-delay = <0>;
5038 thermal-sensors = <&tsens2 0>;
5041 thermal-engine-config {
5047 reset-mon-config {
5055 gpuss-0-thermal {
5056 polling-delay-passive = <10>;
5057 polling-delay = <0>;
5058 thermal-sensors = <&tsens2 1>;
5061 thermal-engine-config {
5067 thermal-hal-config {
5073 reset-mon-config {
5079 gpu0_junction_config: junction-config {
5087 gpuss-1-thermal {
5088 polling-delay-passive = <10>;
5089 polling-delay = <0>;
5090 thermal-sensors = <&tsens2 2>;
5093 thermal-engine-config {
5099 thermal-hal-config {
5105 reset-mon-config {
5111 gpu1_junction_config: junction-config {
5119 gpuss-2-thermal {
5120 polling-delay-passive = <10>;
5121 polling-delay = <0>;
5122 thermal-sensors = <&tsens2 3>;
5125 thermal-engine-config {
5131 thermal-hal-config {
5137 reset-mon-config {
5143 gpu2_junction_config: junction-config {
5151 gpuss-3-thermal {
5152 polling-delay-passive = <10>;
5153 polling-delay = <0>;
5154 thermal-sensors = <&tsens2 4>;
5157 thermal-engine-config {
5163 thermal-hal-config {
5169 reset-mon-config {
5175 gpu3_junction_config: junction-config {
5183 gpuss-4-thermal {
5184 polling-delay-passive = <10>;
5185 polling-delay = <0>;
5186 thermal-sensors = <&tsens2 5>;
5189 thermal-engine-config {
5195 thermal-hal-config {
5201 reset-mon-config {
5207 gpu4_junction_config: junction-config {
5215 gpuss-5-thermal {
5216 polling-delay-passive = <10>;
5217 polling-delay = <0>;
5218 thermal-sensors = <&tsens2 6>;
5221 thermal-engine-config {
5227 thermal-hal-config {
5233 reset-mon-config {
5239 gpu5_junction_config: junction-config {
5247 gpuss-6-thermal {
5248 polling-delay-passive = <10>;
5249 polling-delay = <0>;
5250 thermal-sensors = <&tsens2 7>;
5253 thermal-engine-config {
5259 thermal-hal-config {
5265 reset-mon-config {
5271 gpu6_junction_config: junction-config {
5279 gpuss-7-thermal {
5280 polling-delay-passive = <10>;
5281 polling-delay = <0>;
5282 thermal-sensors = <&tsens2 8>;
5285 thermal-engine-config {
5291 thermal-hal-config {
5297 reset-mon-config {
5303 gpu7_junction_config: junction-config {
5313 compatible = "arm,armv8-timer";