Lines Matching +full:0 +full:x0c222000
36 #clock-cells = <0>;
41 #clock-cells = <0>;
45 #clock-cells = <0>;
53 #clock-cells = <0>;
62 #clock-cells = <0>;
68 #size-cells = <0>;
70 CPU0: cpu@0 {
73 reg = <0 0>;
74 clocks = <&cpufreq_hw 0>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
99 reg = <0 0x100>;
100 clocks = <&cpufreq_hw 0>;
105 qcom,freq-domain = <&cpufreq_hw 0>;
120 reg = <0 0x200>;
121 clocks = <&cpufreq_hw 0>;
126 qcom,freq-domain = <&cpufreq_hw 0>;
141 reg = <0 0x300>;
162 reg = <0 0x400>;
183 reg = <0 0x500>;
204 reg = <0 0x600>;
225 reg = <0 0x700>;
282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
285 arm,psci-suspend-param = <0x40000004>;
292 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
295 arm,psci-suspend-param = <0x40000004>;
302 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
305 arm,psci-suspend-param = <0x40000004>;
314 CLUSTER_SLEEP_0: cluster-sleep-0 {
316 arm,psci-suspend-param = <0x41000044>;
324 arm,psci-suspend-param = <0x4100c344>;
335 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
339 clk_virt: interconnect-0 {
354 reg = <0 0xa0000000 0 0>;
367 #power-domain-cells = <0>;
373 #power-domain-cells = <0>;
379 #power-domain-cells = <0>;
385 #power-domain-cells = <0>;
391 #power-domain-cells = <0>;
397 #power-domain-cells = <0>;
403 #power-domain-cells = <0>;
409 #power-domain-cells = <0>;
415 #power-domain-cells = <0>;
426 reg = <0 0x80000000 0 0xa00000>;
431 reg = <0 0x80a00000 0 0x400000>;
436 reg = <0 0x80e00000 0 0x3d0000>;
441 reg = <0 0xd8100000 0 0x40000>;
446 reg = <0 0x811d0000 0 0x30000>;
452 reg = <0 0x81a00000 0 0x260000>;
458 reg = <0 0x81c60000 0 0x20000>;
464 reg = <0 0x81c80000 0 0x74000>;
471 reg = <0 0x81d00000 0 0x200000>;
477 reg = <0 0x81f00000 0 0x20000>;
482 reg = <0 0x82600000 0 0x100000>;
487 reg = <0 0x82700000 0 0x100000>;
492 reg = <0 0x82800000 0 0x4600000>;
497 reg = <0 0x8a800000 0 0x10800000>;
502 reg = <0 0x9b000000 0 0x80000>;
507 reg = <0 0x9b080000 0 0x10000>;
512 reg = <0 0x9b090000 0 0xa000>;
517 reg = <0 0x9b09a000 0 0x2000>;
522 reg = <0 0x9b100000 0 0x180000>;
528 reg = <0 0x9b280000 0 0x60000>;
534 reg = <0 0x9b2e0000 0 0x20000>;
539 reg = <0 0x9b300000 0 0x800000>;
544 reg = <0 0x9bb00000 0 0x700000>;
549 reg = <0 0x9c200000 0 0x700000>;
554 reg = <0 0x9c900000 0 0x2000000>;
559 reg = <0 0x9e900000 0 0x80000>;
564 reg = <0 0x9e980000 0 0x80000>;
569 reg = <0 0x9ea00000 0 0x4080000>;
575 /* Linux kernel image is loaded at 0xa8000000 */
579 reg = <0x0 0xd4a80000 0x0 0x280000>;
587 reg = <0 0xd4d00000 0 0x3300000>;
592 reg = <0 0xd8000000 0 0x100000>;
597 reg = <0 0xd8140000 0 0x1c0000>;
602 reg = <0 0xd8300000 0 0x500000>;
607 reg = <0 0xd8800000 0 0x8a00000>;
612 reg = <0 0xe1200000 0 0x2740000>;
617 reg = <0 0xe6440000 0 0x279000>;
622 reg = <0 0xf3600000 0 0x4aee000>;
627 reg = <0 0xf80ee000 0 0x1000>;
632 reg = <0 0xf80ef000 0 0x9000>;
637 reg = <0 0xf80f8000 0 0x4000>;
642 reg = <0 0xf80fc000 0 0x4000>;
647 reg = <0 0xf8100000 0 0x100000>;
652 reg = <0 0xf8400000 0 0x4800000>;
657 reg = <0 0xfcc00000 0 0x4000>;
662 reg = <0 0xfcc04000 0 0x100000>;
667 reg = <0 0xfce00000 0 0x2900000>;
672 reg = <0 0xff700000 0 0x100000>;
686 qcom,local-pid = <0>;
710 qcom,local-pid = <0>;
734 qcom,local-pid = <0>;
760 soc: soc@0 {
762 ranges = <0 0 0 0 0x10 0>;
763 dma-ranges = <0 0 0 0 0x10 0>;
770 reg = <0 0x00100000 0 0x1f4200>;
778 <&ufs_mem_phy 0>,
786 reg = <0 0x00408000 0 0x1000>;
796 reg = <0 0x00800000 0 0x60000>;
810 dma-channel-mask = <0x3e>;
811 iommus = <&apps_smmu 0x436 0>;
817 reg = <0 0x008c0000 0 0x2000>;
822 iommus = <&apps_smmu 0x423 0>;
829 reg = <0 0x00880000 0 0x4000>;
833 pinctrl-0 = <&qup_i2c8_data_clk>;
836 #size-cells = <0>;
837 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
838 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
839 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
841 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
842 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
849 reg = <0 0x00880000 0 0x4000>;
854 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
855 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
856 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
857 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
859 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
860 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
863 #size-cells = <0>;
869 reg = <0 0x00884000 0 0x4000>;
873 pinctrl-0 = <&qup_i2c9_data_clk>;
876 #size-cells = <0>;
877 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
878 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
879 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
881 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
889 reg = <0 0x00884000 0 0x4000>;
894 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
895 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
896 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
897 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
903 #size-cells = <0>;
909 reg = <0 0x00888000 0 0x4000>;
913 pinctrl-0 = <&qup_i2c10_data_clk>;
916 #size-cells = <0>;
917 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
918 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
919 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
921 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
929 reg = <0 0x00888000 0 0x4000>;
934 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
939 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
943 #size-cells = <0>;
949 reg = <0 0x0088c000 0 0x4000>;
953 pinctrl-0 = <&qup_i2c11_data_clk>;
956 #size-cells = <0>;
957 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
958 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
959 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
961 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
969 reg = <0 0x0088c000 0 0x4000>;
974 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
975 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
976 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
977 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
979 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
983 #size-cells = <0>;
989 reg = <0 0x00890000 0 0x4000>;
993 pinctrl-0 = <&qup_i2c12_data_clk>;
996 #size-cells = <0>;
997 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
999 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1001 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1009 reg = <0 0x00890000 0 0x4000>;
1014 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1015 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1016 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1017 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1019 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1023 #size-cells = <0>;
1029 reg = <0 0x00894000 0 0x4000>;
1033 pinctrl-0 = <&qup_i2c13_data_clk>;
1036 #size-cells = <0>;
1037 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1038 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1039 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1041 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1049 reg = <0 0x00894000 0 0x4000>;
1054 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1055 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1056 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1057 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1059 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1063 #size-cells = <0>;
1069 reg = <0 0x0089c000 0 0x4000>;
1073 pinctrl-0 = <&qup_i2c15_data_clk>;
1076 #size-cells = <0>;
1077 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1078 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1079 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1081 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1089 reg = <0 0x0089c000 0 0x4000>;
1094 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1095 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1096 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1097 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1099 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1103 #size-cells = <0>;
1110 reg = <0x0 0x009c0000 0x0 0x2000>;
1120 reg = <0x0 0x00980000 0x0 0x4000>;
1125 pinctrl-0 = <&hub_i2c0_data_clk>;
1128 #size-cells = <0>;
1129 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1130 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1137 reg = <0x0 0x00984000 0x0 0x4000>;
1142 pinctrl-0 = <&hub_i2c1_data_clk>;
1145 #size-cells = <0>;
1146 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1154 reg = <0x0 0x00988000 0x0 0x4000>;
1159 pinctrl-0 = <&hub_i2c2_data_clk>;
1162 #size-cells = <0>;
1163 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1171 reg = <0x0 0x0098c000 0x0 0x4000>;
1176 pinctrl-0 = <&hub_i2c3_data_clk>;
1179 #size-cells = <0>;
1180 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1181 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1188 reg = <0x0 0x00990000 0x0 0x4000>;
1193 pinctrl-0 = <&hub_i2c4_data_clk>;
1196 #size-cells = <0>;
1197 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1198 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1205 reg = <0 0x00994000 0 0x4000>;
1210 pinctrl-0 = <&hub_i2c5_data_clk>;
1213 #size-cells = <0>;
1214 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1215 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1222 reg = <0 0x00998000 0 0x4000>;
1227 pinctrl-0 = <&hub_i2c6_data_clk>;
1230 #size-cells = <0>;
1231 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1232 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1239 reg = <0 0x0099c000 0 0x4000>;
1244 pinctrl-0 = <&hub_i2c7_data_clk>;
1247 #size-cells = <0>;
1248 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1249 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1256 reg = <0 0x009a0000 0 0x4000>;
1261 pinctrl-0 = <&hub_i2c8_data_clk>;
1264 #size-cells = <0>;
1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1266 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1273 reg = <0 0x009a4000 0 0x4000>;
1278 pinctrl-0 = <&hub_i2c9_data_clk>;
1281 #size-cells = <0>;
1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1283 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1292 reg = <0 0x00a00000 0 0x60000>;
1306 dma-channel-mask = <0x1e>;
1307 iommus = <&apps_smmu 0xb6 0>;
1313 reg = <0 0x00ac0000 0 0x2000>;
1318 iommus = <&apps_smmu 0xa3 0>;
1319 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1327 reg = <0 0x00a80000 0 0x4000>;
1331 pinctrl-0 = <&qup_i2c0_data_clk>;
1334 #size-cells = <0>;
1335 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1336 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1337 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1339 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1340 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1347 reg = <0 0x00a80000 0 0x4000>;
1352 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1353 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1354 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1355 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1357 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1358 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1361 #size-cells = <0>;
1367 reg = <0 0x00a84000 0 0x4000>;
1371 pinctrl-0 = <&qup_i2c1_data_clk>;
1374 #size-cells = <0>;
1375 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1376 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1377 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1379 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1387 reg = <0 0x00a84000 0 0x4000>;
1392 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1393 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1394 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1395 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1397 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1401 #size-cells = <0>;
1407 reg = <0 0x00a88000 0 0x4000>;
1411 pinctrl-0 = <&qup_i2c2_data_clk>;
1414 #size-cells = <0>;
1415 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1416 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1417 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1419 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1427 reg = <0 0x00a88000 0 0x4000>;
1432 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1433 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1434 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1435 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1437 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1441 #size-cells = <0>;
1447 reg = <0 0x00a8c000 0 0x4000>;
1451 pinctrl-0 = <&qup_i2c3_data_clk>;
1454 #size-cells = <0>;
1455 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1456 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1457 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1459 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1467 reg = <0 0x00a8c000 0 0x4000>;
1472 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1474 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1475 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1477 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1481 #size-cells = <0>;
1487 reg = <0 0x00a90000 0 0x4000>;
1491 pinctrl-0 = <&qup_i2c4_data_clk>;
1494 #size-cells = <0>;
1495 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1496 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1497 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1499 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1507 reg = <0 0x00a90000 0 0x4000>;
1512 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1513 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1514 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1515 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1517 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1521 #size-cells = <0>;
1527 reg = <0 0x00a94000 0 0x4000>;
1531 pinctrl-0 = <&qup_i2c5_data_clk>;
1533 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1534 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1535 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1537 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1541 #size-cells = <0>;
1547 reg = <0 0x00a94000 0 0x4000>;
1552 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1554 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1555 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1557 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1561 #size-cells = <0>;
1567 reg = <0 0x00a98000 0 0x4000>;
1571 pinctrl-0 = <&qup_i2c6_data_clk>;
1573 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1574 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1575 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1577 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1581 #size-cells = <0>;
1587 reg = <0 0x00a98000 0 0x4000>;
1592 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1593 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1594 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1595 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1597 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1601 #size-cells = <0>;
1607 reg = <0 0x00a9c000 0 0x4000>;
1611 pinctrl-0 = <&qup_uart7_default>;
1614 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1615 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1622 reg = <0 0x01500000 0 0x13080>;
1629 reg = <0 0x01600000 0 0x6200>;
1636 reg = <0 0x01680000 0 0x1d080>;
1643 reg = <0 0x016c0000 0 0x12200>;
1652 reg = <0 0x016e0000 0 0x14400>;
1661 reg = <0 0x01700000 0 0x1e400>;
1669 reg = <0 0x01780000 0 0x5b800>;
1677 reg = <0 0x01c00000 0 0x3000>,
1678 <0 0x60000000 0 0xf1d>,
1679 <0 0x60000f20 0 0xa8>,
1680 <0 0x60001000 0 0x1000>,
1681 <0 0x60100000 0 0x100000>;
1685 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1686 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1687 bus-range = <0x00 0xff>;
1691 linux,pci-domain = <0>;
1698 interrupt-map-mask = <0 0 0 0x7>;
1699 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1700 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1701 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1702 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1719 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1720 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1723 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1724 <0x100 &apps_smmu 0x1401 0x1>;
1739 reg = <0 0x01c06000 0 0x2000>;
1757 #clock-cells = <0>;
1760 #phy-cells = <0>;
1768 reg = <0x0 0x01c08000 0x0 0x3000>,
1769 <0x0 0x40000000 0x0 0xf1d>,
1770 <0x0 0x40000f20 0x0 0xa8>,
1771 <0x0 0x40001000 0x0 0x1000>,
1772 <0x0 0x40100000 0x0 0x100000>;
1776 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1777 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1778 bus-range = <0x00 0xff>;
1789 interrupt-map-mask = <0 0 0 0x7>;
1790 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1791 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1792 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1793 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1815 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1816 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1819 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1820 <0x100 &apps_smmu 0x1481 0x1>;
1836 reg = <0x0 0x01c0e000 0x0 0x2000>;
1855 #clock-cells = <0>;
1858 #phy-cells = <0>;
1865 reg = <0x0 0x01dc4000 0x0 0x28000>;
1868 qcom,ee = <0>;
1870 iommus = <&apps_smmu 0x480 0x0>,
1871 <&apps_smmu 0x481 0x0>;
1876 reg = <0x0 0x01dfa000 0x0 0x6000>;
1879 iommus = <&apps_smmu 0x480 0x0>,
1880 <&apps_smmu 0x481 0x0>;
1881 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1887 reg = <0x0 0x01d80000 0x0 0x2000>;
1894 resets = <&ufs_mem_hc 0>;
1898 #phy-cells = <0>;
1906 reg = <0x0 0x01d84000 0x0 0x3000>;
1918 iommus = <&apps_smmu 0x60 0x0>;
1921 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
1922 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
1943 <0 0>,
1944 <0 0>,
1947 <0 0>,
1948 <0 0>,
1949 <0 0>;
1958 reg = <0 0x01d88000 0 0x8000>;
1964 reg = <0 0x01f40000 0 0x20000>;
1970 reg = <0 0x01fc0000 0 0x30000>;
1978 reg = <0 0x03d90000 0 0xa000>;
1989 reg = <0x0 0x04080000 0x0 0x4040>;
1992 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2007 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2013 qcom,smem-states = <&smp2p_modem_out 0>;
2031 reg = <0 0x06aa0000 0 0x1000>;
2040 #clock-cells = <0>;
2043 pinctrl-0 = <&wsa2_swr_active>;
2049 reg = <0 0x06ab0000 0 0x10000>;
2058 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2059 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2060 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2061 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2062 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2063 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2064 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2065 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2066 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2069 #size-cells = <0>;
2076 reg = <0 0x06ac0000 0 0x1000>;
2086 #clock-cells = <0>;
2089 pinctrl-0 = <&rx_swr_active>;
2095 reg = <0 0x06ad0000 0 0x10000>;
2101 qcom,din-ports = <0>;
2104 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
2105 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
2106 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2107 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2108 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2109 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>;
2110 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>;
2111 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2112 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2115 #size-cells = <0>;
2122 reg = <0 0x06ae0000 0 0x1000>;
2132 #clock-cells = <0>;
2135 pinctrl-0 = <&tx_swr_active>;
2141 reg = <0 0x06b00000 0 0x1000>;
2151 #clock-cells = <0>;
2154 pinctrl-0 = <&wsa_swr_active>;
2160 reg = <0 0x06b10000 0 0x10000>;
2169 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2170 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2171 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2172 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2173 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2174 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2175 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2176 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2177 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2180 #size-cells = <0>;
2187 reg = <0 0x06d30000 0 0x10000>;
2196 qcom,dout-ports = <0>;
2197 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2198 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2199 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2200 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2201 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2202 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2203 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2204 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2205 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2208 #size-cells = <0>;
2215 reg = <0 0x06d44000 0 0x1000>;
2224 #clock-cells = <0>;
2231 reg = <0 0x06e80000 0 0x20000>,
2232 <0 0x07250000 0 0x10000>;
2235 gpio-ranges = <&lpass_tlmm 0 0 23>;
2348 reg = <0 0x07400000 0 0x19080>;
2355 reg = <0 0x07430000 0 0x3a200>;
2362 reg = <0 0x07e40000 0 0xe080>;
2369 reg = <0 0x08804000 0 0x1000>;
2379 iommus = <&apps_smmu 0x540 0>;
2380 qcom,dll-config = <0x0007642c>;
2381 qcom,ddr-config = <0x80040868>;
2385 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2386 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2392 sdhci-caps-mask = <0x3 0>;
2423 reg = <0 0x0aaf0000 0 0x10000>;
2435 reg = <0 0x0ae00000 0 0x1000>;
2451 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
2452 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2455 iommus = <&apps_smmu 0x1c00 0x2>;
2465 reg = <0 0x0ae01000 0 0x8f000>,
2466 <0 0x0aeb0000 0 0x2008>;
2470 interrupts = <0>;
2494 #size-cells = <0>;
2496 port@0 {
2497 reg = <0>;
2545 reg = <0 0xae90000 0 0x200>,
2546 <0 0xae90200 0 0x200>,
2547 <0 0xae90400 0 0xc00>,
2548 <0 0xae91000 0 0x400>,
2549 <0 0xae91400 0 0x400>;
2571 #sound-dai-cells = <0>;
2580 #size-cells = <0>;
2582 port@0 {
2583 reg = <0>;
2623 reg = <0 0x0ae94000 0 0x400>;
2646 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2655 #size-cells = <0>;
2661 #size-cells = <0>;
2663 port@0 {
2664 reg = <0>;
2699 reg = <0 0x0ae95000 0 0x200>,
2700 <0 0x0ae95200 0 0x280>,
2701 <0 0x0ae95500 0 0x400>;
2711 #phy-cells = <0>;
2718 reg = <0 0x0ae96000 0 0x400>;
2741 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2750 #size-cells = <0>;
2756 #size-cells = <0>;
2758 port@0 {
2759 reg = <0>;
2775 reg = <0 0x0ae97000 0 0x200>,
2776 <0 0x0ae97200 0 0x280>,
2777 <0 0x0ae97500 0 0x400>;
2787 #phy-cells = <0>;
2795 reg = <0 0x0af00000 0 0x20000>;
2800 <&mdss_dsi0_phy 0>,
2802 <&mdss_dsi1_phy 0>,
2806 <0>, /* dp1 */
2807 <0>,
2808 <0>, /* dp2 */
2809 <0>,
2810 <0>, /* dp3 */
2811 <0>;
2821 reg = <0x0 0x088e3000 0x0 0x154>;
2822 #phy-cells = <0>;
2834 reg = <0x0 0x088e8000 0x0 0x3000>;
2855 #size-cells = <0>;
2857 port@0 {
2858 reg = <0>;
2882 reg = <0x0 0x0a6f8800 0x0 0x400>;
2918 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2919 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2926 reg = <0x0 0x0a600000 0x0 0xcd00>;
2928 iommus = <&apps_smmu 0x40 0x0>;
2938 #size-cells = <0>;
2940 port@0 {
2941 reg = <0>;
2959 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
2960 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2970 reg = <0 0x0c271000 0 0x1000>, /* TM */
2971 <0 0x0c222000 0 0x1000>; /* SROT */
2981 reg = <0 0x0c272000 0 0x1000>, /* TM */
2982 <0 0x0c223000 0 0x1000>; /* SROT */
2992 reg = <0 0x0c273000 0 0x1000>, /* TM */
2993 <0 0x0c224000 0 0x1000>; /* SROT */
3003 reg = <0 0x0c300000 0 0x400>;
3009 #clock-cells = <0>;
3014 reg = <0 0x0c3f0000 0 0x400>;
3019 reg = <0 0x0c400000 0 0x3000>,
3020 <0 0x0c500000 0 0x400000>,
3021 <0 0x0c440000 0 0x80000>,
3022 <0 0x0c4c0000 0 0x20000>,
3023 <0 0x0c42d000 0 0x4000>;
3027 qcom,ee = <0>;
3028 qcom,channel = <0>;
3029 qcom,bus-id = <0>;
3031 #size-cells = <0>;
3038 reg = <0 0x0f100000 0 0x300000>;
3044 gpio-ranges = <&tlmm 0 0 211>;
3554 reg = <0 0x15000000 0 0x100000>;
3658 reg = <0 0x17100000 0 0x10000>, /* GICD */
3659 <0 0x17180000 0 0x200000>; /* GICR * 8 */
3664 redistributor-stride = <0 0x40000>;
3671 reg = <0 0x17140000 0 0x20000>;
3679 reg = <0 0x17420000 0 0x1000>;
3680 ranges = <0 0 0 0x20000000>;
3685 reg = <0x17421000 0x1000>,
3686 <0x17422000 0x1000>;
3687 frame-number = <0>;
3693 reg = <0x17423000 0x1000>;
3700 reg = <0x17425000 0x1000>;
3707 reg = <0x17427000 0x1000>;
3714 reg = <0x17429000 0x1000>;
3721 reg = <0x1742b000 0x1000>;
3728 reg = <0x1742d000 0x1000>;
3738 reg = <0 0x17a00000 0 0x10000>,
3739 <0 0x17a10000 0 0x10000>,
3740 <0 0x17a20000 0 0x10000>,
3741 <0 0x17a30000 0 0x10000>;
3742 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3746 qcom,tcs-offset = <0xd00>;
3749 <WAKE_TCS 2>, <CONTROL_TCS 0>;
3836 reg = <0 0x17d91000 0 0x1000>,
3837 <0 0x17d92000 0 0x1000>,
3838 <0 0x17d93000 0 0x1000>;
3845 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3852 reg = <0 0x24091000 0 0x1000>;
3861 opp-0 {
3901 reg = <0 0x240b6400 0 0x600>;
3910 opp-0 {
3938 reg = <0 0x24100000 0 0xbb800>;
3945 reg = <0 0x25000000 0 0x200000>,
3946 <0 0x25200000 0 0x200000>,
3947 <0 0x25400000 0 0x200000>,
3948 <0 0x25600000 0 0x200000>,
3949 <0 0x25800000 0 0x200000>;
3960 reg = <0x0 0x30000000 0x0 0x100>;
3963 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3977 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
3983 qcom,smem-states = <&smp2p_adsp_out 0>;
4003 #size-cells = <0>;
4008 iommus = <&apps_smmu 0x1003 0x80>,
4009 <&apps_smmu 0x1063 0x0>;
4015 iommus = <&apps_smmu 0x1004 0x80>,
4016 <&apps_smmu 0x1064 0x0>;
4022 iommus = <&apps_smmu 0x1005 0x80>,
4023 <&apps_smmu 0x1065 0x0>;
4029 iommus = <&apps_smmu 0x1006 0x80>,
4030 <&apps_smmu 0x1066 0x0>;
4036 iommus = <&apps_smmu 0x1007 0x80>,
4037 <&apps_smmu 0x1067 0x0>;
4047 #size-cells = <0>;
4052 #sound-dai-cells = <0>;
4058 iommus = <&apps_smmu 0x1001 0x80>,
4059 <&apps_smmu 0x1061 0x0>;
4085 reg = <0 0x320c0000 0 0xe080>;
4092 reg = <0x0 0x32300000 0x0 0x1400000>;
4095 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
4110 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4116 qcom,smem-states = <&smp2p_cdsp_out 0>;
4136 #size-cells = <0>;
4141 iommus = <&apps_smmu 0x1961 0x0>,
4142 <&apps_smmu 0x0c01 0x20>,
4143 <&apps_smmu 0x19c1 0x10>;
4149 iommus = <&apps_smmu 0x1962 0x0>,
4150 <&apps_smmu 0x0c02 0x20>,
4151 <&apps_smmu 0x19c2 0x10>;
4157 iommus = <&apps_smmu 0x1963 0x0>,
4158 <&apps_smmu 0x0c03 0x20>,
4159 <&apps_smmu 0x19c3 0x10>;
4165 iommus = <&apps_smmu 0x1964 0x0>,
4166 <&apps_smmu 0x0c04 0x20>,
4167 <&apps_smmu 0x19c4 0x10>;
4173 iommus = <&apps_smmu 0x1965 0x0>,
4174 <&apps_smmu 0x0c05 0x20>,
4175 <&apps_smmu 0x19c5 0x10>;
4181 iommus = <&apps_smmu 0x1966 0x0>,
4182 <&apps_smmu 0x0c06 0x20>,
4183 <&apps_smmu 0x19c6 0x10>;
4189 iommus = <&apps_smmu 0x1967 0x0>,
4190 <&apps_smmu 0x0c07 0x20>,
4191 <&apps_smmu 0x19c7 0x10>;
4197 iommus = <&apps_smmu 0x1968 0x0>,
4198 <&apps_smmu 0x0c08 0x20>,
4199 <&apps_smmu 0x19c8 0x10>;
4210 polling-delay-passive = <0>;
4211 polling-delay = <0>;
4212 thermal-sensors = <&tsens0 0>;
4230 polling-delay-passive = <0>;
4231 polling-delay = <0>;
4250 polling-delay-passive = <0>;
4251 polling-delay = <0>;
4270 polling-delay-passive = <0>;
4271 polling-delay = <0>;
4290 polling-delay-passive = <0>;
4291 polling-delay = <0>;
4310 polling-delay-passive = <0>;
4311 polling-delay = <0>;
4336 polling-delay-passive = <0>;
4337 polling-delay = <0>;
4362 polling-delay-passive = <0>;
4363 polling-delay = <0>;
4388 polling-delay-passive = <0>;
4389 polling-delay = <0>;
4414 polling-delay-passive = <0>;
4415 polling-delay = <0>;
4440 polling-delay-passive = <0>;
4441 polling-delay = <0>;
4466 polling-delay-passive = <0>;
4467 polling-delay = <0>;
4492 polling-delay-passive = <0>;
4493 polling-delay = <0>;
4518 polling-delay-passive = <0>;
4519 polling-delay = <0>;
4544 polling-delay-passive = <0>;
4545 polling-delay = <0>;
4570 polling-delay-passive = <0>;
4571 polling-delay = <0>;
4596 polling-delay-passive = <0>;
4597 polling-delay = <0>;
4598 thermal-sensors = <&tsens1 0>;
4616 polling-delay-passive = <0>;
4617 polling-delay = <0>;
4642 polling-delay-passive = <0>;
4643 polling-delay = <0>;
4668 polling-delay-passive = <0>;
4669 polling-delay = <0>;
4695 polling-delay = <0>;
4727 polling-delay = <0>;
4759 polling-delay = <0>;
4791 polling-delay = <0>;
4822 polling-delay-passive = <0>;
4823 polling-delay = <0>;
4843 polling-delay = <0>;
4868 polling-delay-passive = <0>;
4869 polling-delay = <0>;
4900 polling-delay-passive = <0>;
4901 polling-delay = <0>;
4932 polling-delay-passive = <0>;
4933 polling-delay = <0>;
4964 polling-delay-passive = <0>;
4965 polling-delay = <0>;
4996 polling-delay-passive = <0>;
4997 polling-delay = <0>;
5016 polling-delay-passive = <0>;
5017 polling-delay = <0>;
5036 polling-delay-passive = <0>;
5037 polling-delay = <0>;
5038 thermal-sensors = <&tsens2 0>;
5055 gpuss-0-thermal {
5057 polling-delay = <0>;
5089 polling-delay = <0>;
5121 polling-delay = <0>;
5153 polling-delay = <0>;
5185 polling-delay = <0>;
5217 polling-delay = <0>;
5249 polling-delay = <0>;
5281 polling-delay = <0>;