Lines Matching +full:0 +full:x008c0000
36 #clock-cells = <0>;
41 #clock-cells = <0>;
45 #clock-cells = <0>;
53 #clock-cells = <0>;
62 #clock-cells = <0>;
68 #size-cells = <0>;
70 CPU0: cpu@0 {
73 reg = <0 0>;
74 clocks = <&cpufreq_hw 0>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
99 reg = <0 0x100>;
100 clocks = <&cpufreq_hw 0>;
105 qcom,freq-domain = <&cpufreq_hw 0>;
120 reg = <0 0x200>;
121 clocks = <&cpufreq_hw 0>;
126 qcom,freq-domain = <&cpufreq_hw 0>;
141 reg = <0 0x300>;
162 reg = <0 0x400>;
183 reg = <0 0x500>;
204 reg = <0 0x600>;
225 reg = <0 0x700>;
282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
285 arm,psci-suspend-param = <0x40000004>;
292 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
295 arm,psci-suspend-param = <0x40000004>;
302 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
305 arm,psci-suspend-param = <0x40000004>;
314 CLUSTER_SLEEP_0: cluster-sleep-0 {
316 arm,psci-suspend-param = <0x41000044>;
324 arm,psci-suspend-param = <0x4100c344>;
335 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
339 clk_virt: interconnect-0 {
354 reg = <0 0xa0000000 0 0>;
367 #power-domain-cells = <0>;
373 #power-domain-cells = <0>;
379 #power-domain-cells = <0>;
385 #power-domain-cells = <0>;
391 #power-domain-cells = <0>;
397 #power-domain-cells = <0>;
403 #power-domain-cells = <0>;
409 #power-domain-cells = <0>;
415 #power-domain-cells = <0>;
426 reg = <0 0x80000000 0 0xa00000>;
431 reg = <0 0x80a00000 0 0x400000>;
436 reg = <0 0x80e00000 0 0x3d0000>;
441 reg = <0 0xd8100000 0 0x40000>;
446 reg = <0 0x811d0000 0 0x30000>;
452 reg = <0 0x81a00000 0 0x260000>;
458 reg = <0 0x81c60000 0 0x20000>;
464 reg = <0 0x81c80000 0 0x74000>;
471 reg = <0 0x81d00000 0 0x200000>;
477 reg = <0 0x81f00000 0 0x20000>;
482 reg = <0 0x82600000 0 0x100000>;
487 reg = <0 0x82700000 0 0x100000>;
492 reg = <0 0x82800000 0 0x4600000>;
497 reg = <0 0x8a800000 0 0x10800000>;
502 reg = <0 0x9b000000 0 0x80000>;
507 reg = <0 0x9b080000 0 0x10000>;
512 reg = <0 0x9b090000 0 0xa000>;
517 reg = <0 0x9b09a000 0 0x2000>;
522 reg = <0 0x9b100000 0 0x180000>;
528 reg = <0 0x9b280000 0 0x60000>;
534 reg = <0 0x9b2e0000 0 0x20000>;
539 reg = <0 0x9b300000 0 0x800000>;
544 reg = <0 0x9bb00000 0 0x700000>;
549 reg = <0 0x9c200000 0 0x700000>;
554 reg = <0 0x9c900000 0 0x2000000>;
559 reg = <0 0x9e900000 0 0x80000>;
564 reg = <0 0x9e980000 0 0x80000>;
569 reg = <0 0x9ea00000 0 0x4080000>;
575 /* Linux kernel image is loaded at 0xa8000000 */
579 reg = <0x0 0xd4a80000 0x0 0x280000>;
587 reg = <0 0xd4d00000 0 0x3300000>;
592 reg = <0 0xd8000000 0 0x100000>;
597 reg = <0 0xd8140000 0 0x1c0000>;
602 reg = <0 0xd8300000 0 0x500000>;
607 reg = <0 0xd8800000 0 0x8a00000>;
612 reg = <0 0xe1200000 0 0x2740000>;
617 reg = <0 0xe6440000 0 0x279000>;
622 reg = <0 0xf3600000 0 0x4aee000>;
627 reg = <0 0xf80ee000 0 0x1000>;
632 reg = <0 0xf80ef000 0 0x9000>;
637 reg = <0 0xf80f8000 0 0x4000>;
642 reg = <0 0xf80fc000 0 0x4000>;
647 reg = <0 0xf8100000 0 0x100000>;
652 reg = <0 0xf8400000 0 0x4800000>;
657 reg = <0 0xfcc00000 0 0x4000>;
662 reg = <0 0xfcc04000 0 0x100000>;
667 reg = <0 0xfce00000 0 0x2900000>;
672 reg = <0 0xff700000 0 0x100000>;
686 qcom,local-pid = <0>;
710 qcom,local-pid = <0>;
734 qcom,local-pid = <0>;
760 soc: soc@0 {
762 ranges = <0 0 0 0 0x10 0>;
763 dma-ranges = <0 0 0 0 0x10 0>;
770 reg = <0 0x00100000 0 0x1f4200>;
778 <&ufs_mem_phy 0>,
786 reg = <0 0x00408000 0 0x1000>;
796 reg = <0 0x00800000 0 0x60000>;
810 dma-channel-mask = <0x3e>;
811 iommus = <&apps_smmu 0x436 0>;
817 reg = <0 0x008c0000 0 0x2000>;
822 iommus = <&apps_smmu 0x423 0>;
829 reg = <0 0x00880000 0 0x4000>;
833 pinctrl-0 = <&qup_i2c8_data_clk>;
836 #size-cells = <0>;
837 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
838 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
839 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
841 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
842 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
849 reg = <0 0x00880000 0 0x4000>;
854 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
855 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
856 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
857 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
859 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
860 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
863 #size-cells = <0>;
869 reg = <0 0x00884000 0 0x4000>;
873 pinctrl-0 = <&qup_i2c9_data_clk>;
876 #size-cells = <0>;
877 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
878 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
879 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
881 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
889 reg = <0 0x00884000 0 0x4000>;
894 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
895 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
896 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
897 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
903 #size-cells = <0>;
909 reg = <0 0x00888000 0 0x4000>;
913 pinctrl-0 = <&qup_i2c10_data_clk>;
916 #size-cells = <0>;
917 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
918 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
919 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
921 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
929 reg = <0 0x00888000 0 0x4000>;
934 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
939 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
943 #size-cells = <0>;
949 reg = <0 0x0088c000 0 0x4000>;
953 pinctrl-0 = <&qup_i2c11_data_clk>;
956 #size-cells = <0>;
957 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
958 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
959 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
961 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
969 reg = <0 0x0088c000 0 0x4000>;
974 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
975 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
976 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
977 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
979 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
983 #size-cells = <0>;
989 reg = <0 0x00890000 0 0x4000>;
993 pinctrl-0 = <&qup_i2c12_data_clk>;
996 #size-cells = <0>;
997 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
999 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1001 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1009 reg = <0 0x00890000 0 0x4000>;
1014 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1015 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1016 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1017 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1019 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1023 #size-cells = <0>;
1029 reg = <0 0x00894000 0 0x4000>;
1033 pinctrl-0 = <&qup_i2c13_data_clk>;
1036 #size-cells = <0>;
1037 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1038 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1039 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1041 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1049 reg = <0 0x00894000 0 0x4000>;
1054 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1055 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1056 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1057 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1059 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1063 #size-cells = <0>;
1069 reg = <0 0x898000 0 0x4000>;
1073 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1075 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1076 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
1083 reg = <0 0x0089c000 0 0x4000>;
1087 pinctrl-0 = <&qup_i2c15_data_clk>;
1090 #size-cells = <0>;
1091 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1092 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1093 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1095 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1103 reg = <0 0x0089c000 0 0x4000>;
1108 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1109 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1110 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1111 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1113 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1117 #size-cells = <0>;
1124 reg = <0x0 0x009c0000 0x0 0x2000>;
1134 reg = <0x0 0x00980000 0x0 0x4000>;
1139 pinctrl-0 = <&hub_i2c0_data_clk>;
1142 #size-cells = <0>;
1143 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1144 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1151 reg = <0x0 0x00984000 0x0 0x4000>;
1156 pinctrl-0 = <&hub_i2c1_data_clk>;
1159 #size-cells = <0>;
1160 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1161 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1168 reg = <0x0 0x00988000 0x0 0x4000>;
1173 pinctrl-0 = <&hub_i2c2_data_clk>;
1176 #size-cells = <0>;
1177 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1178 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1185 reg = <0x0 0x0098c000 0x0 0x4000>;
1190 pinctrl-0 = <&hub_i2c3_data_clk>;
1193 #size-cells = <0>;
1194 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1195 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1202 reg = <0x0 0x00990000 0x0 0x4000>;
1207 pinctrl-0 = <&hub_i2c4_data_clk>;
1210 #size-cells = <0>;
1211 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1212 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1219 reg = <0 0x00994000 0 0x4000>;
1224 pinctrl-0 = <&hub_i2c5_data_clk>;
1227 #size-cells = <0>;
1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1229 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1236 reg = <0 0x00998000 0 0x4000>;
1241 pinctrl-0 = <&hub_i2c6_data_clk>;
1244 #size-cells = <0>;
1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1253 reg = <0 0x0099c000 0 0x4000>;
1258 pinctrl-0 = <&hub_i2c7_data_clk>;
1261 #size-cells = <0>;
1262 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1263 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1270 reg = <0 0x009a0000 0 0x4000>;
1275 pinctrl-0 = <&hub_i2c8_data_clk>;
1278 #size-cells = <0>;
1279 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1280 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1287 reg = <0 0x009a4000 0 0x4000>;
1292 pinctrl-0 = <&hub_i2c9_data_clk>;
1295 #size-cells = <0>;
1296 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1297 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1306 reg = <0 0x00a00000 0 0x60000>;
1320 dma-channel-mask = <0x1e>;
1321 iommus = <&apps_smmu 0xb6 0>;
1327 reg = <0 0x00ac0000 0 0x2000>;
1332 iommus = <&apps_smmu 0xa3 0>;
1333 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1341 reg = <0 0x00a80000 0 0x4000>;
1345 pinctrl-0 = <&qup_i2c0_data_clk>;
1348 #size-cells = <0>;
1349 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1350 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1351 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1353 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1354 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1361 reg = <0 0x00a80000 0 0x4000>;
1366 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1367 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1368 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1369 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1371 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1372 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1375 #size-cells = <0>;
1381 reg = <0 0x00a84000 0 0x4000>;
1385 pinctrl-0 = <&qup_i2c1_data_clk>;
1388 #size-cells = <0>;
1389 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1390 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1391 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1393 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1401 reg = <0 0x00a84000 0 0x4000>;
1406 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1407 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1408 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1409 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1411 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1415 #size-cells = <0>;
1421 reg = <0 0x00a88000 0 0x4000>;
1425 pinctrl-0 = <&qup_i2c2_data_clk>;
1428 #size-cells = <0>;
1429 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1430 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1431 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1433 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1441 reg = <0 0x00a88000 0 0x4000>;
1446 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1447 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1448 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1449 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1451 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1455 #size-cells = <0>;
1461 reg = <0 0x00a8c000 0 0x4000>;
1465 pinctrl-0 = <&qup_i2c3_data_clk>;
1468 #size-cells = <0>;
1469 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1470 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1471 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1473 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1481 reg = <0 0x00a8c000 0 0x4000>;
1486 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1487 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1488 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1489 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1491 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1495 #size-cells = <0>;
1501 reg = <0 0x00a90000 0 0x4000>;
1505 pinctrl-0 = <&qup_i2c4_data_clk>;
1508 #size-cells = <0>;
1509 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1510 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1511 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1513 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1521 reg = <0 0x00a90000 0 0x4000>;
1526 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1527 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1528 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1529 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1531 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1535 #size-cells = <0>;
1541 reg = <0 0x00a94000 0 0x4000>;
1545 pinctrl-0 = <&qup_i2c5_data_clk>;
1547 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1548 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1549 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1551 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1555 #size-cells = <0>;
1561 reg = <0 0x00a94000 0 0x4000>;
1566 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1567 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1568 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1569 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1571 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1575 #size-cells = <0>;
1581 reg = <0 0x00a98000 0 0x4000>;
1585 pinctrl-0 = <&qup_i2c6_data_clk>;
1587 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1588 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1589 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1591 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1595 #size-cells = <0>;
1601 reg = <0 0x00a98000 0 0x4000>;
1606 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1607 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1608 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1609 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1611 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1615 #size-cells = <0>;
1621 reg = <0 0x00a9c000 0 0x4000>;
1625 pinctrl-0 = <&qup_uart7_default>;
1628 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1629 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1636 reg = <0 0x01500000 0 0x13080>;
1643 reg = <0 0x01600000 0 0x6200>;
1650 reg = <0 0x01680000 0 0x1d080>;
1657 reg = <0 0x016c0000 0 0x12200>;
1666 reg = <0 0x016e0000 0 0x14400>;
1675 reg = <0 0x01700000 0 0x1e400>;
1683 reg = <0 0x01780000 0 0x5b800>;
1691 reg = <0 0x01c00000 0 0x3000>,
1692 <0 0x60000000 0 0xf1d>,
1693 <0 0x60000f20 0 0xa8>,
1694 <0 0x60001000 0 0x1000>,
1695 <0 0x60100000 0 0x100000>;
1699 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1700 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1701 bus-range = <0x00 0xff>;
1705 linux,pci-domain = <0>;
1712 interrupt-map-mask = <0 0 0 0x7>;
1713 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1714 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1715 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1716 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1733 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1734 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1737 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1738 <0x100 &apps_smmu 0x1401 0x1>;
1753 reg = <0 0x01c06000 0 0x2000>;
1771 #clock-cells = <0>;
1774 #phy-cells = <0>;
1782 reg = <0x0 0x01c08000 0x0 0x3000>,
1783 <0x0 0x40000000 0x0 0xf1d>,
1784 <0x0 0x40000f20 0x0 0xa8>,
1785 <0x0 0x40001000 0x0 0x1000>,
1786 <0x0 0x40100000 0x0 0x100000>;
1790 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1791 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1792 bus-range = <0x00 0xff>;
1803 interrupt-map-mask = <0 0 0 0x7>;
1804 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1805 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1806 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1807 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1829 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1830 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1833 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1834 <0x100 &apps_smmu 0x1481 0x1>;
1850 reg = <0x0 0x01c0e000 0x0 0x2000>;
1869 #clock-cells = <0>;
1872 #phy-cells = <0>;
1879 reg = <0x0 0x01dc4000 0x0 0x28000>;
1882 qcom,ee = <0>;
1886 iommus = <&apps_smmu 0x480 0x0>,
1887 <&apps_smmu 0x481 0x0>;
1892 reg = <0x0 0x01dfa000 0x0 0x6000>;
1895 iommus = <&apps_smmu 0x480 0x0>,
1896 <&apps_smmu 0x481 0x0>;
1897 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1903 reg = <0x0 0x01d80000 0x0 0x2000>;
1910 resets = <&ufs_mem_hc 0>;
1914 #phy-cells = <0>;
1922 reg = <0x0 0x01d84000 0x0 0x3000>;
1934 iommus = <&apps_smmu 0x60 0x0>;
1937 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
1938 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
1959 <0 0>,
1960 <0 0>,
1963 <0 0>,
1964 <0 0>,
1965 <0 0>;
1974 reg = <0 0x01d88000 0 0x8000>;
1980 reg = <0 0x01f40000 0 0x20000>;
1986 reg = <0 0x01fc0000 0 0x30000>;
1994 reg = <0 0x03d90000 0 0xa000>;
2005 reg = <0x0 0x04080000 0x0 0x10000>;
2008 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2023 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2029 qcom,smem-states = <&smp2p_modem_out 0>;
2047 reg = <0x0 0x06800000 0x0 0x10000>;
2050 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2064 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
2070 qcom,smem-states = <&smp2p_adsp_out 0>;
2091 #size-cells = <0>;
2096 iommus = <&apps_smmu 0x1003 0x80>,
2097 <&apps_smmu 0x1063 0x0>;
2104 iommus = <&apps_smmu 0x1004 0x80>,
2105 <&apps_smmu 0x1064 0x0>;
2112 iommus = <&apps_smmu 0x1005 0x80>,
2113 <&apps_smmu 0x1065 0x0>;
2120 iommus = <&apps_smmu 0x1006 0x80>,
2121 <&apps_smmu 0x1066 0x0>;
2128 iommus = <&apps_smmu 0x1007 0x80>,
2129 <&apps_smmu 0x1067 0x0>;
2140 #size-cells = <0>;
2145 #sound-dai-cells = <0>;
2151 iommus = <&apps_smmu 0x1001 0x80>,
2152 <&apps_smmu 0x1061 0x0>;
2178 reg = <0 0x06aa0000 0 0x1000>;
2187 #clock-cells = <0>;
2190 pinctrl-0 = <&wsa2_swr_active>;
2196 reg = <0 0x06ab0000 0 0x10000>;
2205 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2206 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2207 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2208 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2209 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2210 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2211 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2212 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2213 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2216 #size-cells = <0>;
2223 reg = <0 0x06ac0000 0 0x1000>;
2233 #clock-cells = <0>;
2236 pinctrl-0 = <&rx_swr_active>;
2242 reg = <0 0x06ad0000 0 0x10000>;
2248 qcom,din-ports = <0>;
2251 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
2252 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
2253 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2254 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2255 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2256 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>;
2257 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>;
2258 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2259 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2262 #size-cells = <0>;
2269 reg = <0 0x06ae0000 0 0x1000>;
2279 #clock-cells = <0>;
2282 pinctrl-0 = <&tx_swr_active>;
2288 reg = <0 0x06b00000 0 0x1000>;
2298 #clock-cells = <0>;
2301 pinctrl-0 = <&wsa_swr_active>;
2307 reg = <0 0x06b10000 0 0x10000>;
2316 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2317 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2318 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2319 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2320 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2321 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2322 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2323 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2324 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2327 #size-cells = <0>;
2334 reg = <0 0x06d30000 0 0x10000>;
2343 qcom,dout-ports = <0>;
2344 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2345 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2346 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2347 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2348 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2349 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2350 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2351 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2352 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2355 #size-cells = <0>;
2362 reg = <0 0x06d44000 0 0x1000>;
2371 #clock-cells = <0>;
2378 reg = <0 0x06e80000 0 0x20000>,
2379 <0 0x07250000 0 0x10000>;
2382 gpio-ranges = <&lpass_tlmm 0 0 23>;
2495 reg = <0 0x07400000 0 0x19080>;
2502 reg = <0 0x07430000 0 0x3a200>;
2509 reg = <0 0x07e40000 0 0xe080>;
2516 reg = <0 0x08804000 0 0x1000>;
2526 iommus = <&apps_smmu 0x540 0>;
2527 qcom,dll-config = <0x0007642c>;
2528 qcom,ddr-config = <0x80040868>;
2532 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2533 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2539 sdhci-caps-mask = <0x3 0>;
2570 reg = <0 0x0aaf0000 0 0x10000>;
2582 reg = <0 0x0ae00000 0 0x1000>;
2598 interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>;
2601 iommus = <&apps_smmu 0x1c00 0x2>;
2611 reg = <0 0x0ae01000 0 0x8f000>,
2612 <0 0x0aeb0000 0 0x2008>;
2616 interrupts = <0>;
2640 #size-cells = <0>;
2642 port@0 {
2643 reg = <0>;
2691 reg = <0 0xae90000 0 0x200>,
2692 <0 0xae90200 0 0x200>,
2693 <0 0xae90400 0 0xc00>,
2694 <0 0xae91000 0 0x400>,
2695 <0 0xae91400 0 0x400>;
2717 #sound-dai-cells = <0>;
2726 #size-cells = <0>;
2728 port@0 {
2729 reg = <0>;
2769 reg = <0 0x0ae94000 0 0x400>;
2792 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2801 #size-cells = <0>;
2807 #size-cells = <0>;
2809 port@0 {
2810 reg = <0>;
2845 reg = <0 0x0ae95000 0 0x200>,
2846 <0 0x0ae95200 0 0x280>,
2847 <0 0x0ae95500 0 0x400>;
2857 #phy-cells = <0>;
2864 reg = <0 0x0ae96000 0 0x400>;
2887 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2896 #size-cells = <0>;
2902 #size-cells = <0>;
2904 port@0 {
2905 reg = <0>;
2921 reg = <0 0x0ae97000 0 0x200>,
2922 <0 0x0ae97200 0 0x280>,
2923 <0 0x0ae97500 0 0x400>;
2933 #phy-cells = <0>;
2941 reg = <0 0x0af00000 0 0x20000>;
2946 <&mdss_dsi0_phy 0>,
2948 <&mdss_dsi1_phy 0>,
2952 <0>, /* dp1 */
2953 <0>,
2954 <0>, /* dp2 */
2955 <0>,
2956 <0>, /* dp3 */
2957 <0>;
2967 reg = <0x0 0x088e3000 0x0 0x154>;
2968 #phy-cells = <0>;
2980 reg = <0x0 0x088e8000 0x0 0x3000>;
3001 #size-cells = <0>;
3003 port@0 {
3004 reg = <0>;
3028 reg = <0x0 0x0a6f8800 0x0 0x400>;
3064 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3065 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3072 reg = <0x0 0x0a600000 0x0 0xcd00>;
3074 iommus = <&apps_smmu 0x40 0x0>;
3084 #size-cells = <0>;
3086 port@0 {
3087 reg = <0>;
3105 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3106 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3116 reg = <0 0x0c271000 0 0x1000>, /* TM */
3117 <0 0x0c222000 0 0x1000>; /* SROT */
3127 reg = <0 0x0c272000 0 0x1000>, /* TM */
3128 <0 0x0c223000 0 0x1000>; /* SROT */
3138 reg = <0 0x0c273000 0 0x1000>, /* TM */
3139 <0 0x0c224000 0 0x1000>; /* SROT */
3149 reg = <0 0x0c300000 0 0x400>;
3155 #clock-cells = <0>;
3160 reg = <0 0x0c3f0000 0 0x400>;
3165 reg = <0 0x0c400000 0 0x3000>,
3166 <0 0x0c500000 0 0x400000>,
3167 <0 0x0c440000 0 0x80000>,
3168 <0 0x0c4c0000 0 0x20000>,
3169 <0 0x0c42d000 0 0x4000>;
3173 qcom,ee = <0>;
3174 qcom,channel = <0>;
3175 qcom,bus-id = <0>;
3177 #size-cells = <0>;
3184 reg = <0 0x0f100000 0 0x300000>;
3190 gpio-ranges = <&tlmm 0 0 211>;
3716 reg = <0 0x15000000 0 0x100000>;
3820 reg = <0 0x17100000 0 0x10000>, /* GICD */
3821 <0 0x17180000 0 0x200000>; /* GICR * 8 */
3826 redistributor-stride = <0 0x40000>;
3833 reg = <0 0x17140000 0 0x20000>;
3841 reg = <0 0x17420000 0 0x1000>;
3842 ranges = <0 0 0 0x20000000>;
3847 reg = <0x17421000 0x1000>,
3848 <0x17422000 0x1000>;
3849 frame-number = <0>;
3855 reg = <0x17423000 0x1000>;
3862 reg = <0x17425000 0x1000>;
3869 reg = <0x17427000 0x1000>;
3876 reg = <0x17429000 0x1000>;
3883 reg = <0x1742b000 0x1000>;
3890 reg = <0x1742d000 0x1000>;
3900 reg = <0 0x17a00000 0 0x10000>,
3901 <0 0x17a10000 0 0x10000>,
3902 <0 0x17a20000 0 0x10000>,
3903 <0 0x17a30000 0 0x10000>;
3904 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3908 qcom,tcs-offset = <0xd00>;
3911 <WAKE_TCS 2>, <CONTROL_TCS 0>;
3998 reg = <0 0x17d91000 0 0x1000>,
3999 <0 0x17d92000 0 0x1000>,
4000 <0 0x17d93000 0 0x1000>;
4007 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4014 reg = <0 0x24091000 0 0x1000>;
4023 opp-0 {
4063 reg = <0 0x240b6400 0 0x600>;
4072 opp-0 {
4100 reg = <0 0x24100000 0 0xbb800>;
4107 reg = <0 0x25000000 0 0x200000>,
4108 <0 0x25200000 0 0x200000>,
4109 <0 0x25400000 0 0x200000>,
4110 <0 0x25600000 0 0x200000>,
4111 <0 0x25800000 0 0x200000>;
4122 reg = <0 0x320c0000 0 0xe080>;
4129 reg = <0x0 0x32300000 0x0 0x10000>;
4132 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
4147 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4153 qcom,smem-states = <&smp2p_cdsp_out 0>;
4174 #size-cells = <0>;
4179 iommus = <&apps_smmu 0x1961 0x0>,
4180 <&apps_smmu 0x0c01 0x20>,
4181 <&apps_smmu 0x19c1 0x10>;
4188 iommus = <&apps_smmu 0x1962 0x0>,
4189 <&apps_smmu 0x0c02 0x20>,
4190 <&apps_smmu 0x19c2 0x10>;
4197 iommus = <&apps_smmu 0x1963 0x0>,
4198 <&apps_smmu 0x0c03 0x20>,
4199 <&apps_smmu 0x19c3 0x10>;
4206 iommus = <&apps_smmu 0x1964 0x0>,
4207 <&apps_smmu 0x0c04 0x20>,
4208 <&apps_smmu 0x19c4 0x10>;
4215 iommus = <&apps_smmu 0x1965 0x0>,
4216 <&apps_smmu 0x0c05 0x20>,
4217 <&apps_smmu 0x19c5 0x10>;
4224 iommus = <&apps_smmu 0x1966 0x0>,
4225 <&apps_smmu 0x0c06 0x20>,
4226 <&apps_smmu 0x19c6 0x10>;
4233 iommus = <&apps_smmu 0x1967 0x0>,
4234 <&apps_smmu 0x0c07 0x20>,
4235 <&apps_smmu 0x19c7 0x10>;
4242 iommus = <&apps_smmu 0x1968 0x0>,
4243 <&apps_smmu 0x0c08 0x20>,
4244 <&apps_smmu 0x19c8 0x10>;
4256 polling-delay-passive = <0>;
4257 polling-delay = <0>;
4258 thermal-sensors = <&tsens0 0>;
4276 polling-delay-passive = <0>;
4277 polling-delay = <0>;
4296 polling-delay-passive = <0>;
4297 polling-delay = <0>;
4316 polling-delay-passive = <0>;
4317 polling-delay = <0>;
4336 polling-delay-passive = <0>;
4337 polling-delay = <0>;
4356 polling-delay-passive = <0>;
4357 polling-delay = <0>;
4382 polling-delay-passive = <0>;
4383 polling-delay = <0>;
4408 polling-delay-passive = <0>;
4409 polling-delay = <0>;
4434 polling-delay-passive = <0>;
4435 polling-delay = <0>;
4460 polling-delay-passive = <0>;
4461 polling-delay = <0>;
4486 polling-delay-passive = <0>;
4487 polling-delay = <0>;
4512 polling-delay-passive = <0>;
4513 polling-delay = <0>;
4538 polling-delay-passive = <0>;
4539 polling-delay = <0>;
4564 polling-delay-passive = <0>;
4565 polling-delay = <0>;
4590 polling-delay-passive = <0>;
4591 polling-delay = <0>;
4616 polling-delay-passive = <0>;
4617 polling-delay = <0>;
4642 polling-delay-passive = <0>;
4643 polling-delay = <0>;
4644 thermal-sensors = <&tsens1 0>;
4662 polling-delay-passive = <0>;
4663 polling-delay = <0>;
4688 polling-delay-passive = <0>;
4689 polling-delay = <0>;
4714 polling-delay-passive = <0>;
4715 polling-delay = <0>;
4741 polling-delay = <0>;
4773 polling-delay = <0>;
4805 polling-delay = <0>;
4837 polling-delay = <0>;
4868 polling-delay-passive = <0>;
4869 polling-delay = <0>;
4889 polling-delay = <0>;
4914 polling-delay-passive = <0>;
4915 polling-delay = <0>;
4946 polling-delay-passive = <0>;
4947 polling-delay = <0>;
4978 polling-delay-passive = <0>;
4979 polling-delay = <0>;
5010 polling-delay-passive = <0>;
5011 polling-delay = <0>;
5042 polling-delay-passive = <0>;
5043 polling-delay = <0>;
5062 polling-delay-passive = <0>;
5063 polling-delay = <0>;
5082 polling-delay-passive = <0>;
5083 polling-delay = <0>;
5084 thermal-sensors = <&tsens2 0>;
5101 gpuss-0-thermal {
5103 polling-delay = <0>;
5135 polling-delay = <0>;
5167 polling-delay = <0>;
5199 polling-delay = <0>;
5231 polling-delay = <0>;
5263 polling-delay = <0>;
5295 polling-delay = <0>;
5327 polling-delay = <0>;