Lines Matching +full:polling +full:- +full:delay +full:- +full:passive
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/mailbox/qcom-ipcc.h>
15 #include <dt-bindings/phy/phy-qcom-qmp.h>
16 #include <dt-bindings/power/qcom,rpmhpd.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/interconnect/qcom,icc.h>
19 #include <dt-bindings/interconnect/qcom,sm8450.h>
20 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <76800000>;
40 sleep_clk: sleep-clk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32000>;
48 #address-cells = <2>;
49 #size-cells = <0>;
55 enable-method = "psci";
56 next-level-cache = <&L2_0>;
57 power-domains = <&CPU_PD0>;
58 power-domain-names = "psci";
59 qcom,freq-domain = <&cpufreq_hw 0>;
60 #cooling-cells = <2>;
62 L2_0: l2-cache {
64 cache-level = <2>;
65 cache-unified;
66 next-level-cache = <&L3_0>;
67 L3_0: l3-cache {
69 cache-level = <3>;
70 cache-unified;
79 enable-method = "psci";
80 next-level-cache = <&L2_100>;
81 power-domains = <&CPU_PD1>;
82 power-domain-names = "psci";
83 qcom,freq-domain = <&cpufreq_hw 0>;
84 #cooling-cells = <2>;
86 L2_100: l2-cache {
88 cache-level = <2>;
89 cache-unified;
90 next-level-cache = <&L3_0>;
98 enable-method = "psci";
99 next-level-cache = <&L2_200>;
100 power-domains = <&CPU_PD2>;
101 power-domain-names = "psci";
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 #cooling-cells = <2>;
105 L2_200: l2-cache {
107 cache-level = <2>;
108 cache-unified;
109 next-level-cache = <&L3_0>;
117 enable-method = "psci";
118 next-level-cache = <&L2_300>;
119 power-domains = <&CPU_PD3>;
120 power-domain-names = "psci";
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 #cooling-cells = <2>;
124 L2_300: l2-cache {
126 cache-level = <2>;
127 cache-unified;
128 next-level-cache = <&L3_0>;
136 enable-method = "psci";
137 next-level-cache = <&L2_400>;
138 power-domains = <&CPU_PD4>;
139 power-domain-names = "psci";
140 qcom,freq-domain = <&cpufreq_hw 1>;
141 #cooling-cells = <2>;
143 L2_400: l2-cache {
145 cache-level = <2>;
146 cache-unified;
147 next-level-cache = <&L3_0>;
155 enable-method = "psci";
156 next-level-cache = <&L2_500>;
157 power-domains = <&CPU_PD5>;
158 power-domain-names = "psci";
159 qcom,freq-domain = <&cpufreq_hw 1>;
160 #cooling-cells = <2>;
162 L2_500: l2-cache {
164 cache-level = <2>;
165 cache-unified;
166 next-level-cache = <&L3_0>;
174 enable-method = "psci";
175 next-level-cache = <&L2_600>;
176 power-domains = <&CPU_PD6>;
177 power-domain-names = "psci";
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 #cooling-cells = <2>;
181 L2_600: l2-cache {
183 cache-level = <2>;
184 cache-unified;
185 next-level-cache = <&L3_0>;
193 enable-method = "psci";
194 next-level-cache = <&L2_700>;
195 power-domains = <&CPU_PD7>;
196 power-domain-names = "psci";
197 qcom,freq-domain = <&cpufreq_hw 2>;
198 #cooling-cells = <2>;
200 L2_700: l2-cache {
202 cache-level = <2>;
203 cache-unified;
204 next-level-cache = <&L3_0>;
208 cpu-map {
244 idle-states {
245 entry-method = "psci";
247 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
248 compatible = "arm,idle-state";
249 idle-state-name = "silver-rail-power-collapse";
250 arm,psci-suspend-param = <0x40000004>;
251 entry-latency-us = <800>;
252 exit-latency-us = <750>;
253 min-residency-us = <4090>;
254 local-timer-stop;
257 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
258 compatible = "arm,idle-state";
259 idle-state-name = "gold-rail-power-collapse";
260 arm,psci-suspend-param = <0x40000004>;
261 entry-latency-us = <600>;
262 exit-latency-us = <1550>;
263 min-residency-us = <4791>;
264 local-timer-stop;
268 domain-idle-states {
269 CLUSTER_SLEEP_0: cluster-sleep-0 {
270 compatible = "domain-idle-state";
271 arm,psci-suspend-param = <0x41000044>;
272 entry-latency-us = <1050>;
273 exit-latency-us = <2500>;
274 min-residency-us = <5309>;
277 CLUSTER_SLEEP_1: cluster-sleep-1 {
278 compatible = "domain-idle-state";
279 arm,psci-suspend-param = <0x4100c344>;
280 entry-latency-us = <2700>;
281 exit-latency-us = <3500>;
282 min-residency-us = <13959>;
289 compatible = "qcom,scm-sm8450", "qcom,scm";
290 qcom,dload-mode = <&tcsr 0x13000>;
292 #reset-cells = <1>;
296 clk_virt: interconnect-0 {
297 compatible = "qcom,sm8450-clk-virt";
298 #interconnect-cells = <2>;
299 qcom,bcm-voters = <&apps_bcm_voter>;
302 mc_virt: interconnect-1 {
303 compatible = "qcom,sm8450-mc-virt";
304 #interconnect-cells = <2>;
305 qcom,bcm-voters = <&apps_bcm_voter>;
315 compatible = "arm,armv8-pmuv3";
320 compatible = "arm,psci-1.0";
323 CPU_PD0: power-domain-cpu0 {
324 #power-domain-cells = <0>;
325 power-domains = <&CLUSTER_PD>;
326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
329 CPU_PD1: power-domain-cpu1 {
330 #power-domain-cells = <0>;
331 power-domains = <&CLUSTER_PD>;
332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
335 CPU_PD2: power-domain-cpu2 {
336 #power-domain-cells = <0>;
337 power-domains = <&CLUSTER_PD>;
338 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
341 CPU_PD3: power-domain-cpu3 {
342 #power-domain-cells = <0>;
343 power-domains = <&CLUSTER_PD>;
344 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
347 CPU_PD4: power-domain-cpu4 {
348 #power-domain-cells = <0>;
349 power-domains = <&CLUSTER_PD>;
350 domain-idle-states = <&BIG_CPU_SLEEP_0>;
353 CPU_PD5: power-domain-cpu5 {
354 #power-domain-cells = <0>;
355 power-domains = <&CLUSTER_PD>;
356 domain-idle-states = <&BIG_CPU_SLEEP_0>;
359 CPU_PD6: power-domain-cpu6 {
360 #power-domain-cells = <0>;
361 power-domains = <&CLUSTER_PD>;
362 domain-idle-states = <&BIG_CPU_SLEEP_0>;
365 CPU_PD7: power-domain-cpu7 {
366 #power-domain-cells = <0>;
367 power-domains = <&CLUSTER_PD>;
368 domain-idle-states = <&BIG_CPU_SLEEP_0>;
371 CLUSTER_PD: power-domain-cpu-cluster0 {
372 #power-domain-cells = <0>;
373 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 qup_opp_table_100mhz: opp-table-qup {
378 compatible = "operating-points-v2";
380 opp-50000000 {
381 opp-hz = /bits/ 64 <50000000>;
382 required-opps = <&rpmhpd_opp_min_svs>;
385 opp-75000000 {
386 opp-hz = /bits/ 64 <75000000>;
387 required-opps = <&rpmhpd_opp_low_svs>;
390 opp-100000000 {
391 opp-hz = /bits/ 64 <100000000>;
392 required-opps = <&rpmhpd_opp_svs>;
396 reserved_memory: reserved-memory {
397 #address-cells = <2>;
398 #size-cells = <2>;
403 no-map;
408 no-map;
413 no-map;
418 no-map;
423 no-map;
427 compatible = "qcom,cmd-db";
429 no-map;
434 no-map;
439 no-map;
444 no-map;
449 no-map;
457 no-map;
462 no-map;
467 no-map;
472 no-map;
477 no-map;
482 no-map;
487 no-map;
492 no-map;
497 no-map;
502 no-map;
507 no-map;
513 no-map;
519 no-map;
524 no-map;
529 no-map;
534 no-map;
538 compatible = "qcom,rmtfs-mem";
540 no-map;
542 qcom,client-id = <1>;
548 no-map;
553 no-map;
562 no-map;
567 no-map;
572 no-map;
577 no-map;
582 no-map;
587 no-map;
592 no-map;
597 no-map;
602 no-map;
607 no-map;
612 no-map;
617 no-map;
622 no-map;
627 no-map;
631 smp2p-adsp {
634 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
640 qcom,local-pid = <0>;
641 qcom,remote-pid = <2>;
643 smp2p_adsp_out: master-kernel {
644 qcom,entry-name = "master-kernel";
645 #qcom,smem-state-cells = <1>;
648 smp2p_adsp_in: slave-kernel {
649 qcom,entry-name = "slave-kernel";
650 interrupt-controller;
651 #interrupt-cells = <2>;
655 smp2p-cdsp {
658 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
664 qcom,local-pid = <0>;
665 qcom,remote-pid = <5>;
667 smp2p_cdsp_out: master-kernel {
668 qcom,entry-name = "master-kernel";
669 #qcom,smem-state-cells = <1>;
672 smp2p_cdsp_in: slave-kernel {
673 qcom,entry-name = "slave-kernel";
674 interrupt-controller;
675 #interrupt-cells = <2>;
679 smp2p-modem {
682 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
688 qcom,local-pid = <0>;
689 qcom,remote-pid = <1>;
691 smp2p_modem_out: master-kernel {
692 qcom,entry-name = "master-kernel";
693 #qcom,smem-state-cells = <1>;
696 smp2p_modem_in: slave-kernel {
697 qcom,entry-name = "slave-kernel";
698 interrupt-controller;
699 #interrupt-cells = <2>;
702 ipa_smp2p_out: ipa-ap-to-modem {
703 qcom,entry-name = "ipa";
704 #qcom,smem-state-cells = <1>;
707 ipa_smp2p_in: ipa-modem-to-ap {
708 qcom,entry-name = "ipa";
709 interrupt-controller;
710 #interrupt-cells = <2>;
714 smp2p-slpi {
717 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
723 qcom,local-pid = <0>;
724 qcom,remote-pid = <3>;
726 smp2p_slpi_out: master-kernel {
727 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells = <1>;
731 smp2p_slpi_in: slave-kernel {
732 qcom,entry-name = "slave-kernel";
733 interrupt-controller;
734 #interrupt-cells = <2>;
739 #address-cells = <2>;
740 #size-cells = <2>;
742 dma-ranges = <0 0 0 0 0x10 0>;
743 compatible = "simple-bus";
745 gcc: clock-controller@100000 {
746 compatible = "qcom,gcc-sm8450";
748 #clock-cells = <1>;
749 #reset-cells = <1>;
750 #power-domain-cells = <1>;
760 clock-names = "bi_tcxo",
771 gpi_dma2: dma-controller@800000 {
772 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
773 #dma-cells = <3>;
787 dma-channels = <12>;
788 dma-channel-mask = <0x7e>;
794 compatible = "qcom,geni-se-qup";
796 clock-names = "m-ahb", "s-ahb";
800 #address-cells = <2>;
801 #size-cells = <2>;
806 compatible = "qcom,geni-i2c";
808 clock-names = "se";
810 pinctrl-names = "default";
811 pinctrl-0 = <&qup_i2c15_data_clk>;
813 #address-cells = <1>;
814 #size-cells = <0>;
818 interconnect-names = "qup-core", "qup-config", "qup-memory";
821 dma-names = "tx", "rx";
826 compatible = "qcom,geni-spi";
828 clock-names = "se";
831 pinctrl-names = "default";
832 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
835 interconnect-names = "qup-core", "qup-config";
838 dma-names = "tx", "rx";
839 #address-cells = <1>;
840 #size-cells = <0>;
845 compatible = "qcom,geni-i2c";
847 clock-names = "se";
849 pinctrl-names = "default";
850 pinctrl-0 = <&qup_i2c16_data_clk>;
852 #address-cells = <1>;
853 #size-cells = <0>;
857 interconnect-names = "qup-core", "qup-config", "qup-memory";
860 dma-names = "tx", "rx";
865 compatible = "qcom,geni-spi";
867 clock-names = "se";
870 pinctrl-names = "default";
871 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
874 interconnect-names = "qup-core", "qup-config";
877 dma-names = "tx", "rx";
878 #address-cells = <1>;
879 #size-cells = <0>;
884 compatible = "qcom,geni-i2c";
886 clock-names = "se";
888 pinctrl-names = "default";
889 pinctrl-0 = <&qup_i2c17_data_clk>;
891 #address-cells = <1>;
892 #size-cells = <0>;
896 interconnect-names = "qup-core", "qup-config", "qup-memory";
899 dma-names = "tx", "rx";
904 compatible = "qcom,geni-spi";
906 clock-names = "se";
909 pinctrl-names = "default";
910 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
913 interconnect-names = "qup-core", "qup-config";
916 dma-names = "tx", "rx";
917 #address-cells = <1>;
918 #size-cells = <0>;
923 compatible = "qcom,geni-i2c";
925 clock-names = "se";
927 pinctrl-names = "default";
928 pinctrl-0 = <&qup_i2c18_data_clk>;
930 #address-cells = <1>;
931 #size-cells = <0>;
935 interconnect-names = "qup-core", "qup-config", "qup-memory";
938 dma-names = "tx", "rx";
943 compatible = "qcom,geni-spi";
945 clock-names = "se";
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
952 interconnect-names = "qup-core", "qup-config";
955 dma-names = "tx", "rx";
956 #address-cells = <1>;
957 #size-cells = <0>;
962 compatible = "qcom,geni-i2c";
964 clock-names = "se";
966 pinctrl-names = "default";
967 pinctrl-0 = <&qup_i2c19_data_clk>;
969 #address-cells = <1>;
970 #size-cells = <0>;
974 interconnect-names = "qup-core", "qup-config", "qup-memory";
977 dma-names = "tx", "rx";
982 compatible = "qcom,geni-spi";
984 clock-names = "se";
987 pinctrl-names = "default";
988 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
991 interconnect-names = "qup-core", "qup-config";
994 dma-names = "tx", "rx";
995 #address-cells = <1>;
996 #size-cells = <0>;
1001 compatible = "qcom,geni-i2c";
1003 clock-names = "se";
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&qup_i2c20_data_clk>;
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1013 interconnect-names = "qup-core", "qup-config", "qup-memory";
1016 dma-names = "tx", "rx";
1021 compatible = "qcom,geni-uart";
1023 clock-names = "se";
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&qup_uart20_default>;
1032 interconnect-names = "qup-core",
1033 "qup-config";
1038 compatible = "qcom,geni-spi";
1040 clock-names = "se";
1043 pinctrl-names = "default";
1044 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1047 interconnect-names = "qup-core", "qup-config";
1050 dma-names = "tx", "rx";
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1057 compatible = "qcom,geni-i2c";
1059 clock-names = "se";
1061 pinctrl-names = "default";
1062 pinctrl-0 = <&qup_i2c21_data_clk>;
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1069 interconnect-names = "qup-core", "qup-config", "qup-memory";
1072 dma-names = "tx", "rx";
1077 compatible = "qcom,geni-spi";
1079 clock-names = "se";
1082 pinctrl-names = "default";
1083 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1086 interconnect-names = "qup-core", "qup-config";
1089 dma-names = "tx", "rx";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1096 gpi_dma0: dma-controller@900000 {
1097 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1098 #dma-cells = <3>;
1112 dma-channels = <12>;
1113 dma-channel-mask = <0x7e>;
1119 compatible = "qcom,geni-se-qup";
1121 clock-names = "m-ahb", "s-ahb";
1126 interconnect-names = "qup-core";
1127 #address-cells = <2>;
1128 #size-cells = <2>;
1133 compatible = "qcom,geni-i2c";
1135 clock-names = "se";
1137 pinctrl-names = "default";
1138 pinctrl-0 = <&qup_i2c0_data_clk>;
1140 #address-cells = <1>;
1141 #size-cells = <0>;
1145 interconnect-names = "qup-core", "qup-config", "qup-memory";
1148 dma-names = "tx", "rx";
1153 compatible = "qcom,geni-spi";
1155 clock-names = "se";
1158 pinctrl-names = "default";
1159 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1160 power-domains = <&rpmhpd RPMHPD_CX>;
1161 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnect-names = "qup-core", "qup-config", "qup-memory";
1168 dma-names = "tx", "rx";
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1175 compatible = "qcom,geni-i2c";
1177 clock-names = "se";
1179 pinctrl-names = "default";
1180 pinctrl-0 = <&qup_i2c1_data_clk>;
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1187 interconnect-names = "qup-core", "qup-config", "qup-memory";
1190 dma-names = "tx", "rx";
1195 compatible = "qcom,geni-spi";
1197 clock-names = "se";
1200 pinctrl-names = "default";
1201 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnect-names = "qup-core", "qup-config", "qup-memory";
1208 dma-names = "tx", "rx";
1209 #address-cells = <1>;
1210 #size-cells = <0>;
1215 compatible = "qcom,geni-i2c";
1217 clock-names = "se";
1219 pinctrl-names = "default";
1220 pinctrl-0 = <&qup_i2c2_data_clk>;
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1227 interconnect-names = "qup-core", "qup-config", "qup-memory";
1230 dma-names = "tx", "rx";
1235 compatible = "qcom,geni-spi";
1237 clock-names = "se";
1240 pinctrl-names = "default";
1241 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnect-names = "qup-core", "qup-config", "qup-memory";
1248 dma-names = "tx", "rx";
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1256 compatible = "qcom,geni-i2c";
1258 clock-names = "se";
1260 pinctrl-names = "default";
1261 pinctrl-0 = <&qup_i2c3_data_clk>;
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1268 interconnect-names = "qup-core", "qup-config", "qup-memory";
1271 dma-names = "tx", "rx";
1276 compatible = "qcom,geni-spi";
1278 clock-names = "se";
1281 pinctrl-names = "default";
1282 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnect-names = "qup-core", "qup-config", "qup-memory";
1289 dma-names = "tx", "rx";
1290 #address-cells = <1>;
1291 #size-cells = <0>;
1296 compatible = "qcom,geni-i2c";
1298 clock-names = "se";
1300 pinctrl-names = "default";
1301 pinctrl-0 = <&qup_i2c4_data_clk>;
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1308 interconnect-names = "qup-core", "qup-config", "qup-memory";
1311 dma-names = "tx", "rx";
1316 compatible = "qcom,geni-spi";
1318 clock-names = "se";
1321 pinctrl-names = "default";
1322 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1323 power-domains = <&rpmhpd RPMHPD_CX>;
1324 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnect-names = "qup-core", "qup-config", "qup-memory";
1331 dma-names = "tx", "rx";
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1338 compatible = "qcom,geni-i2c";
1340 clock-names = "se";
1342 pinctrl-names = "default";
1343 pinctrl-0 = <&qup_i2c5_data_clk>;
1345 #address-cells = <1>;
1346 #size-cells = <0>;
1350 interconnect-names = "qup-core", "qup-config", "qup-memory";
1353 dma-names = "tx", "rx";
1358 compatible = "qcom,geni-spi";
1360 clock-names = "se";
1363 pinctrl-names = "default";
1364 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnect-names = "qup-core", "qup-config", "qup-memory";
1371 dma-names = "tx", "rx";
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1379 compatible = "qcom,geni-i2c";
1381 clock-names = "se";
1383 pinctrl-names = "default";
1384 pinctrl-0 = <&qup_i2c6_data_clk>;
1386 #address-cells = <1>;
1387 #size-cells = <0>;
1391 interconnect-names = "qup-core", "qup-config", "qup-memory";
1394 dma-names = "tx", "rx";
1399 compatible = "qcom,geni-spi";
1401 clock-names = "se";
1404 pinctrl-names = "default";
1405 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnect-names = "qup-core", "qup-config", "qup-memory";
1412 dma-names = "tx", "rx";
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1419 compatible = "qcom,geni-debug-uart";
1421 clock-names = "se";
1423 pinctrl-names = "default";
1424 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1430 interconnect-names = "qup-core",
1431 "qup-config";
1436 gpi_dma1: dma-controller@a00000 {
1437 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1438 #dma-cells = <3>;
1452 dma-channels = <12>;
1453 dma-channel-mask = <0x7e>;
1459 compatible = "qcom,geni-se-qup";
1461 clock-names = "m-ahb", "s-ahb";
1466 interconnect-names = "qup-core";
1467 #address-cells = <2>;
1468 #size-cells = <2>;
1473 compatible = "qcom,geni-i2c";
1475 clock-names = "se";
1477 pinctrl-names = "default";
1478 pinctrl-0 = <&qup_i2c8_data_clk>;
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1485 interconnect-names = "qup-core", "qup-config", "qup-memory";
1488 dma-names = "tx", "rx";
1493 compatible = "qcom,geni-spi";
1495 clock-names = "se";
1498 pinctrl-names = "default";
1499 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnect-names = "qup-core", "qup-config", "qup-memory";
1506 dma-names = "tx", "rx";
1507 #address-cells = <1>;
1508 #size-cells = <0>;
1513 compatible = "qcom,geni-i2c";
1515 clock-names = "se";
1517 pinctrl-names = "default";
1518 pinctrl-0 = <&qup_i2c9_data_clk>;
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1525 interconnect-names = "qup-core", "qup-config", "qup-memory";
1528 dma-names = "tx", "rx";
1533 compatible = "qcom,geni-spi";
1535 clock-names = "se";
1538 pinctrl-names = "default";
1539 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnect-names = "qup-core", "qup-config", "qup-memory";
1546 dma-names = "tx", "rx";
1547 #address-cells = <1>;
1548 #size-cells = <0>;
1553 compatible = "qcom,geni-i2c";
1555 clock-names = "se";
1557 pinctrl-names = "default";
1558 pinctrl-0 = <&qup_i2c10_data_clk>;
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1565 interconnect-names = "qup-core", "qup-config", "qup-memory";
1568 dma-names = "tx", "rx";
1573 compatible = "qcom,geni-spi";
1575 clock-names = "se";
1578 pinctrl-names = "default";
1579 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnect-names = "qup-core", "qup-config", "qup-memory";
1586 dma-names = "tx", "rx";
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1593 compatible = "qcom,geni-i2c";
1595 clock-names = "se";
1597 pinctrl-names = "default";
1598 pinctrl-0 = <&qup_i2c11_data_clk>;
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1605 interconnect-names = "qup-core", "qup-config", "qup-memory";
1608 dma-names = "tx", "rx";
1613 compatible = "qcom,geni-spi";
1615 clock-names = "se";
1618 pinctrl-names = "default";
1619 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnect-names = "qup-core", "qup-config", "qup-memory";
1626 dma-names = "tx", "rx";
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1633 compatible = "qcom,geni-i2c";
1635 clock-names = "se";
1637 pinctrl-names = "default";
1638 pinctrl-0 = <&qup_i2c12_data_clk>;
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1645 interconnect-names = "qup-core", "qup-config", "qup-memory";
1648 dma-names = "tx", "rx";
1653 compatible = "qcom,geni-spi";
1655 clock-names = "se";
1658 pinctrl-names = "default";
1659 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnect-names = "qup-core", "qup-config", "qup-memory";
1666 dma-names = "tx", "rx";
1667 #address-cells = <1>;
1668 #size-cells = <0>;
1673 compatible = "qcom,geni-i2c";
1675 clock-names = "se";
1677 pinctrl-names = "default";
1678 pinctrl-0 = <&qup_i2c13_data_clk>;
1683 interconnect-names = "qup-core", "qup-config", "qup-memory";
1686 dma-names = "tx", "rx";
1687 #address-cells = <1>;
1688 #size-cells = <0>;
1693 compatible = "qcom,geni-spi";
1695 clock-names = "se";
1698 pinctrl-names = "default";
1699 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnect-names = "qup-core", "qup-config", "qup-memory";
1706 dma-names = "tx", "rx";
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1713 compatible = "qcom,geni-i2c";
1715 clock-names = "se";
1717 pinctrl-names = "default";
1718 pinctrl-0 = <&qup_i2c14_data_clk>;
1723 interconnect-names = "qup-core", "qup-config", "qup-memory";
1726 dma-names = "tx", "rx";
1727 #address-cells = <1>;
1728 #size-cells = <0>;
1733 compatible = "qcom,geni-spi";
1735 clock-names = "se";
1738 pinctrl-names = "default";
1739 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnect-names = "qup-core", "qup-config", "qup-memory";
1746 dma-names = "tx", "rx";
1747 #address-cells = <1>;
1748 #size-cells = <0>;
1754 compatible = "qcom,sm8450-prng-ee", "qcom,prng-ee";
1759 compatible = "qcom,pcie-sm8450-pcie0";
1765 reg-names = "parf", "dbi", "elbi", "atu", "config";
1767 linux,pci-domain = <0>;
1768 bus-range = <0x00 0xff>;
1769 num-lanes = <1>;
1771 #address-cells = <3>;
1772 #size-cells = <2>;
1777 msi-map = <0x0 &gic_its 0x5980 0x1>,
1779 msi-map-mask = <0xff00>;
1781 interrupt-names = "msi";
1782 #interrupt-cells = <1>;
1783 interrupt-map-mask = <0 0 0 0x7>;
1784 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1801 clock-names = "pipe",
1814 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1818 reset-names = "pci";
1820 power-domains = <&gcc PCIE_0_GDSC>;
1823 phy-names = "pciephy";
1825 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1826 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1828 pinctrl-names = "default";
1829 pinctrl-0 = <&pcie0_default_state>;
1835 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1837 #address-cells = <2>;
1838 #size-cells = <2>;
1844 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1847 reset-names = "phy";
1849 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1850 assigned-clock-rates = <100000000>;
1860 clock-names = "pipe0";
1862 #clock-cells = <0>;
1863 #phy-cells = <0>;
1864 clock-output-names = "pcie_0_pipe_clk";
1869 compatible = "qcom,pcie-sm8450-pcie1";
1875 reg-names = "parf", "dbi", "elbi", "atu", "config";
1877 linux,pci-domain = <1>;
1878 bus-range = <0x00 0xff>;
1879 num-lanes = <2>;
1881 #address-cells = <3>;
1882 #size-cells = <2>;
1887 msi-map = <0x0 &gic_its 0x5a00 0x1>,
1889 msi-map-mask = <0xff00>;
1891 interrupt-names = "msi";
1892 #interrupt-cells = <1>;
1893 interrupt-map-mask = <0 0 0 0x7>;
1894 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1910 clock-names = "pipe",
1922 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1926 reset-names = "pci";
1928 power-domains = <&gcc PCIE_1_GDSC>;
1931 phy-names = "pciephy";
1933 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1934 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1936 pinctrl-names = "default";
1937 pinctrl-0 = <&pcie1_default_state>;
1943 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1945 #address-cells = <2>;
1946 #size-cells = <2>;
1952 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1955 reset-names = "phy";
1957 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1958 assigned-clock-rates = <100000000>;
1970 clock-names = "pipe0";
1972 #clock-cells = <0>;
1973 #phy-cells = <0>;
1974 clock-output-names = "pcie_1_pipe_clk";
1979 compatible = "qcom,sm8450-config-noc";
1981 #interconnect-cells = <2>;
1982 qcom,bcm-voters = <&apps_bcm_voter>;
1986 compatible = "qcom,sm8450-system-noc";
1988 #interconnect-cells = <2>;
1989 qcom,bcm-voters = <&apps_bcm_voter>;
1993 compatible = "qcom,sm8450-pcie-anoc";
1995 #interconnect-cells = <2>;
1996 qcom,bcm-voters = <&apps_bcm_voter>;
2000 compatible = "qcom,sm8450-aggre1-noc";
2002 #interconnect-cells = <2>;
2005 qcom,bcm-voters = <&apps_bcm_voter>;
2009 compatible = "qcom,sm8450-aggre2-noc";
2011 #interconnect-cells = <2>;
2012 qcom,bcm-voters = <&apps_bcm_voter>;
2020 compatible = "qcom,sm8450-mmss-noc";
2022 #interconnect-cells = <2>;
2023 qcom,bcm-voters = <&apps_bcm_voter>;
2027 compatible = "qcom,tcsr-mutex";
2029 #hwlock-cells = <1>;
2033 compatible = "qcom,sm8450-tcsr", "syscon";
2038 compatible = "qcom,sm8450-usb-hs-phy",
2039 "qcom,usb-snps-hs-7nm-phy";
2042 #phy-cells = <0>;
2045 clock-names = "ref";
2051 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2058 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2062 reset-names = "phy", "common";
2064 #clock-cells = <1>;
2065 #phy-cells = <1>;
2070 #address-cells = <1>;
2071 #size-cells = <0>;
2097 compatible = "qcom,sm8450-slpi-pas";
2100 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2105 interrupt-names = "wdog", "fatal", "ready",
2106 "handover", "stop-ack";
2109 clock-names = "xo";
2111 power-domains = <&rpmhpd RPMHPD_LCX>,
2113 power-domain-names = "lcx", "lmx";
2115 memory-region = <&slpi_mem>;
2119 qcom,smem-states = <&smp2p_slpi_out 0>;
2120 qcom,smem-state-names = "stop";
2124 glink-edge {
2125 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2132 qcom,remote-pid = <3>;
2136 qcom,glink-channels = "fastrpcglink-apps-dsp";
2138 #address-cells = <1>;
2139 #size-cells = <0>;
2141 compute-cb@1 {
2142 compatible = "qcom,fastrpc-compute-cb";
2147 compute-cb@2 {
2148 compatible = "qcom,fastrpc-compute-cb";
2153 compute-cb@3 {
2154 compatible = "qcom,fastrpc-compute-cb";
2157 /* note: shared-cb = <4> in downstream */
2164 compatible = "qcom,sm8450-lpass-wsa-macro";
2171 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2172 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2174 assigned-clock-rates = <19200000>, <19200000>;
2176 #clock-cells = <0>;
2177 clock-output-names = "wsa2-mclk";
2178 pinctrl-names = "default";
2179 pinctrl-0 = <&wsa2_swr_active>;
2180 #sound-dai-cells = <1>;
2184 compatible = "qcom,soundwire-v1.7.0";
2188 clock-names = "iface";
2191 qcom,din-ports = <2>;
2192 qcom,dout-ports = <6>;
2194 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2195 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2196 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2197 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2198 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2199 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2200 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2201 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2202 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2204 #address-cells = <2>;
2205 #size-cells = <0>;
2206 #sound-dai-cells = <1>;
2211 compatible = "qcom,sm8450-lpass-rx-macro";
2218 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2220 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2222 assigned-clock-rates = <19200000>, <19200000>;
2224 #clock-cells = <0>;
2225 clock-output-names = "mclk";
2226 pinctrl-names = "default";
2227 pinctrl-0 = <&rx_swr_active>;
2228 #sound-dai-cells = <1>;
2232 compatible = "qcom,soundwire-v1.7.0";
2236 clock-names = "iface";
2238 qcom,din-ports = <0>;
2239 qcom,dout-ports = <5>;
2241 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2242 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2243 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2244 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2245 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2246 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2247 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2248 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2249 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2251 #address-cells = <2>;
2252 #size-cells = <0>;
2253 #sound-dai-cells = <1>;
2258 compatible = "qcom,sm8450-lpass-tx-macro";
2265 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2266 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2268 assigned-clock-rates = <19200000>, <19200000>;
2270 #clock-cells = <0>;
2271 clock-output-names = "mclk";
2272 pinctrl-names = "default";
2273 pinctrl-0 = <&tx_swr_active>;
2274 #sound-dai-cells = <1>;
2278 compatible = "qcom,sm8450-lpass-wsa-macro";
2285 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2287 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2289 assigned-clock-rates = <19200000>, <19200000>;
2291 #clock-cells = <0>;
2292 clock-output-names = "mclk";
2293 pinctrl-names = "default";
2294 pinctrl-0 = <&wsa_swr_active>;
2295 #sound-dai-cells = <1>;
2299 compatible = "qcom,soundwire-v1.7.0";
2303 clock-names = "iface";
2306 qcom,din-ports = <2>;
2307 qcom,dout-ports = <6>;
2309 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2310 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2311 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2312 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2313 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2314 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2315 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2316 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2317 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2319 #address-cells = <2>;
2320 #size-cells = <0>;
2321 #sound-dai-cells = <1>;
2326 compatible = "qcom,soundwire-v1.7.0";
2330 interrupt-names = "core", "wakeup";
2333 clock-names = "iface";
2336 qcom,din-ports = <4>;
2337 qcom,dout-ports = <0>;
2338 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2339 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2340 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2341 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2342 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2343 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2344 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2345 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2346 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2348 #address-cells = <2>;
2349 #size-cells = <0>;
2350 #sound-dai-cells = <1>;
2355 compatible = "qcom,sm8450-lpass-va-macro";
2361 clock-names = "mclk", "macro", "dcodec", "npl";
2362 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2363 assigned-clock-rates = <19200000>;
2365 #clock-cells = <0>;
2366 clock-output-names = "fsgen";
2367 #sound-dai-cells = <1>;
2372 compatible = "qcom,sm8450-adsp-pas";
2375 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2380 interrupt-names = "wdog", "fatal", "ready",
2381 "handover", "stop-ack";
2384 clock-names = "xo";
2386 power-domains = <&rpmhpd RPMHPD_LCX>,
2388 power-domain-names = "lcx", "lmx";
2390 memory-region = <&adsp_mem>;
2394 qcom,smem-states = <&smp2p_adsp_out 0>;
2395 qcom,smem-state-names = "stop";
2399 remoteproc_adsp_glink: glink-edge {
2400 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2407 qcom,remote-pid = <2>;
2411 qcom,glink-channels = "adsp_apps";
2414 #address-cells = <1>;
2415 #size-cells = <0>;
2420 #sound-dai-cells = <0>;
2421 qcom,protection-domain = "avs/audio",
2425 compatible = "qcom,q6apm-dais";
2430 compatible = "qcom,q6apm-lpass-dais";
2431 #sound-dai-cells = <1>;
2438 qcom,protection-domain = "avs/audio",
2441 q6prmcc: clock-controller {
2442 compatible = "qcom,q6prm-lpass-clocks";
2443 #clock-cells = <2>;
2450 qcom,glink-channels = "fastrpcglink-apps-dsp";
2452 #address-cells = <1>;
2453 #size-cells = <0>;
2455 compute-cb@3 {
2456 compatible = "qcom,fastrpc-compute-cb";
2461 compute-cb@4 {
2462 compatible = "qcom,fastrpc-compute-cb";
2467 compute-cb@5 {
2468 compatible = "qcom,fastrpc-compute-cb";
2477 compatible = "qcom,sm8450-cdsp-pas";
2480 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2485 interrupt-names = "wdog", "fatal", "ready",
2486 "handover", "stop-ack";
2489 clock-names = "xo";
2491 power-domains = <&rpmhpd RPMHPD_CX>,
2493 power-domain-names = "cx", "mxc";
2495 memory-region = <&cdsp_mem>;
2499 qcom,smem-states = <&smp2p_cdsp_out 0>;
2500 qcom,smem-state-names = "stop";
2504 glink-edge {
2505 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2512 qcom,remote-pid = <5>;
2516 qcom,glink-channels = "fastrpcglink-apps-dsp";
2518 #address-cells = <1>;
2519 #size-cells = <0>;
2521 compute-cb@1 {
2522 compatible = "qcom,fastrpc-compute-cb";
2528 compute-cb@2 {
2529 compatible = "qcom,fastrpc-compute-cb";
2535 compute-cb@3 {
2536 compatible = "qcom,fastrpc-compute-cb";
2542 compute-cb@4 {
2543 compatible = "qcom,fastrpc-compute-cb";
2549 compute-cb@5 {
2550 compatible = "qcom,fastrpc-compute-cb";
2556 compute-cb@6 {
2557 compatible = "qcom,fastrpc-compute-cb";
2563 compute-cb@7 {
2564 compatible = "qcom,fastrpc-compute-cb";
2570 compute-cb@8 {
2571 compatible = "qcom,fastrpc-compute-cb";
2583 compatible = "qcom,sm8450-mpss-pas";
2586 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2592 interrupt-names = "wdog", "fatal", "ready", "handover",
2593 "stop-ack", "shutdown-ack";
2596 clock-names = "xo";
2598 power-domains = <&rpmhpd RPMHPD_CX>,
2600 power-domain-names = "cx", "mss";
2602 memory-region = <&mpss_mem>;
2606 qcom,smem-states = <&smp2p_modem_out 0>;
2607 qcom,smem-state-names = "stop";
2611 glink-edge {
2612 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2618 qcom,remote-pid = <1>;
2622 videocc: clock-controller@aaf0000 {
2623 compatible = "qcom,sm8450-videocc";
2627 power-domains = <&rpmhpd RPMHPD_MMCX>;
2628 required-opps = <&rpmhpd_opp_low_svs>;
2629 #clock-cells = <1>;
2630 #reset-cells = <1>;
2631 #power-domain-cells = <1>;
2635 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2638 power-domains = <&camcc TITAN_TOP_GDSC>;
2645 clock-names = "camnoc_axi",
2650 pinctrl-0 = <&cci0_default &cci1_default>;
2651 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2652 pinctrl-names = "default", "sleep";
2655 #address-cells = <1>;
2656 #size-cells = <0>;
2658 cci0_i2c0: i2c-bus@0 {
2660 clock-frequency = <1000000>;
2661 #address-cells = <1>;
2662 #size-cells = <0>;
2665 cci0_i2c1: i2c-bus@1 {
2667 clock-frequency = <1000000>;
2668 #address-cells = <1>;
2669 #size-cells = <0>;
2674 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2677 power-domains = <&camcc TITAN_TOP_GDSC>;
2684 clock-names = "camnoc_axi",
2689 pinctrl-0 = <&cci2_default &cci3_default>;
2690 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
2691 pinctrl-names = "default", "sleep";
2694 #address-cells = <1>;
2695 #size-cells = <0>;
2697 cci1_i2c0: i2c-bus@0 {
2699 clock-frequency = <1000000>;
2700 #address-cells = <1>;
2701 #size-cells = <0>;
2704 cci1_i2c1: i2c-bus@1 {
2706 clock-frequency = <1000000>;
2707 #address-cells = <1>;
2708 #size-cells = <0>;
2712 camcc: clock-controller@ade0000 {
2713 compatible = "qcom,sm8450-camcc";
2719 power-domains = <&rpmhpd RPMHPD_MMCX>;
2720 required-opps = <&rpmhpd_opp_low_svs>;
2721 #clock-cells = <1>;
2722 #reset-cells = <1>;
2723 #power-domain-cells = <1>;
2727 mdss: display-subsystem@ae00000 {
2728 compatible = "qcom,sm8450-mdss";
2730 reg-names = "mdss";
2737 interconnect-names = "mdp0-mem",
2738 "mdp1-mem",
2739 "cpu-cfg";
2743 power-domains = <&dispcc MDSS_GDSC>;
2751 interrupt-controller;
2752 #interrupt-cells = <1>;
2756 #address-cells = <2>;
2757 #size-cells = <2>;
2762 mdss_mdp: display-controller@ae01000 {
2763 compatible = "qcom,sm8450-dpu";
2766 reg-names = "mdp", "vbif";
2774 clock-names = "bus",
2781 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2782 assigned-clock-rates = <19200000>;
2784 operating-points-v2 = <&mdp_opp_table>;
2785 power-domains = <&rpmhpd RPMHPD_MMCX>;
2787 interrupt-parent = <&mdss>;
2791 #address-cells = <1>;
2792 #size-cells = <0>;
2797 remote-endpoint = <&mdss_dsi0_in>;
2804 remote-endpoint = <&mdss_dsi1_in>;
2811 remote-endpoint = <&mdss_dp0_in>;
2816 mdp_opp_table: opp-table {
2817 compatible = "operating-points-v2";
2819 opp-172000000 {
2820 opp-hz = /bits/ 64 <172000000>;
2821 required-opps = <&rpmhpd_opp_low_svs_d1>;
2824 opp-200000000 {
2825 opp-hz = /bits/ 64 <200000000>;
2826 required-opps = <&rpmhpd_opp_low_svs>;
2829 opp-325000000 {
2830 opp-hz = /bits/ 64 <325000000>;
2831 required-opps = <&rpmhpd_opp_svs>;
2834 opp-375000000 {
2835 opp-hz = /bits/ 64 <375000000>;
2836 required-opps = <&rpmhpd_opp_svs_l1>;
2839 opp-500000000 {
2840 opp-hz = /bits/ 64 <500000000>;
2841 required-opps = <&rpmhpd_opp_nom>;
2846 mdss_dp0: displayport-controller@ae90000 {
2847 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
2853 interrupt-parent = <&mdss>;
2860 clock-names = "core_iface",
2866 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2868 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2872 phy-names = "dp";
2874 #sound-dai-cells = <0>;
2876 operating-points-v2 = <&dp_opp_table>;
2877 power-domains = <&rpmhpd RPMHPD_MMCX>;
2882 #address-cells = <1>;
2883 #size-cells = <0>;
2888 remote-endpoint = <&dpu_intf0_out>;
2893 dp_opp_table: opp-table {
2894 compatible = "operating-points-v2";
2896 opp-160000000 {
2897 opp-hz = /bits/ 64 <160000000>;
2898 required-opps = <&rpmhpd_opp_low_svs>;
2901 opp-270000000 {
2902 opp-hz = /bits/ 64 <270000000>;
2903 required-opps = <&rpmhpd_opp_svs>;
2906 opp-540000000 {
2907 opp-hz = /bits/ 64 <540000000>;
2908 required-opps = <&rpmhpd_opp_svs_l1>;
2911 opp-810000000 {
2912 opp-hz = /bits/ 64 <810000000>;
2913 required-opps = <&rpmhpd_opp_nom>;
2919 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2921 reg-names = "dsi_ctrl";
2923 interrupt-parent = <&mdss>;
2932 clock-names = "byte",
2939 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2940 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2942 operating-points-v2 = <&mdss_dsi_opp_table>;
2943 power-domains = <&rpmhpd RPMHPD_MMCX>;
2946 phy-names = "dsi";
2948 #address-cells = <1>;
2949 #size-cells = <0>;
2954 #address-cells = <1>;
2955 #size-cells = <0>;
2960 remote-endpoint = <&dpu_intf1_out>;
2971 mdss_dsi_opp_table: opp-table {
2972 compatible = "operating-points-v2";
2974 opp-187500000 {
2975 opp-hz = /bits/ 64 <187500000>;
2976 required-opps = <&rpmhpd_opp_low_svs>;
2979 opp-300000000 {
2980 opp-hz = /bits/ 64 <300000000>;
2981 required-opps = <&rpmhpd_opp_svs>;
2984 opp-358000000 {
2985 opp-hz = /bits/ 64 <358000000>;
2986 required-opps = <&rpmhpd_opp_svs_l1>;
2992 compatible = "qcom,sm8450-dsi-phy-5nm";
2996 reg-names = "dsi_phy",
3000 #clock-cells = <1>;
3001 #phy-cells = <0>;
3005 clock-names = "iface", "ref";
3011 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3013 reg-names = "dsi_ctrl";
3015 interrupt-parent = <&mdss>;
3024 clock-names = "byte",
3031 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3032 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3034 operating-points-v2 = <&mdss_dsi_opp_table>;
3035 power-domains = <&rpmhpd RPMHPD_MMCX>;
3038 phy-names = "dsi";
3040 #address-cells = <1>;
3041 #size-cells = <0>;
3046 #address-cells = <1>;
3047 #size-cells = <0>;
3052 remote-endpoint = <&dpu_intf2_out>;
3065 compatible = "qcom,sm8450-dsi-phy-5nm";
3069 reg-names = "dsi_phy",
3073 #clock-cells = <1>;
3074 #phy-cells = <0>;
3078 clock-names = "iface", "ref";
3084 dispcc: clock-controller@af00000 {
3085 compatible = "qcom,sm8450-dispcc";
3103 power-domains = <&rpmhpd RPMHPD_MMCX>;
3104 required-opps = <&rpmhpd_opp_low_svs>;
3105 #clock-cells = <1>;
3106 #reset-cells = <1>;
3107 #power-domain-cells = <1>;
3111 pdc: interrupt-controller@b220000 {
3112 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3114 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3116 #interrupt-cells = <2>;
3117 interrupt-parent = <&intc>;
3118 interrupt-controller;
3121 tsens0: thermal-sensor@c263000 {
3122 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3128 interrupt-names = "uplow", "critical";
3129 #thermal-sensor-cells = <1>;
3132 tsens1: thermal-sensor@c265000 {
3133 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3139 interrupt-names = "uplow", "critical";
3140 #thermal-sensor-cells = <1>;
3143 aoss_qmp: power-management@c300000 {
3144 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3146 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3150 #clock-cells = <0>;
3154 compatible = "qcom,rpmh-stats";
3159 compatible = "qcom,spmi-pmic-arb";
3165 reg-names = "core",
3170 interrupt-names = "periph_irq";
3171 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3174 interrupt-controller;
3175 #interrupt-cells = <4>;
3176 #address-cells = <2>;
3177 #size-cells = <0>;
3181 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3184 interrupt-controller;
3185 #interrupt-cells = <3>;
3186 #mbox-cells = <2>;
3190 compatible = "qcom,sm8450-tlmm";
3193 gpio-controller;
3194 #gpio-cells = <2>;
3195 interrupt-controller;
3196 #interrupt-cells = <2>;
3197 gpio-ranges = <&tlmm 0 0 211>;
3198 wakeup-parent = <&pdc>;
3200 sdc2_default_state: sdc2-default-state {
3201 clk-pins {
3203 drive-strength = <16>;
3204 bias-disable;
3207 cmd-pins {
3209 drive-strength = <16>;
3210 bias-pull-up;
3213 data-pins {
3215 drive-strength = <16>;
3216 bias-pull-up;
3220 sdc2_sleep_state: sdc2-sleep-state {
3221 clk-pins {
3223 drive-strength = <2>;
3224 bias-disable;
3227 cmd-pins {
3229 drive-strength = <2>;
3230 bias-pull-up;
3233 data-pins {
3235 drive-strength = <2>;
3236 bias-pull-up;
3240 cci0_default: cci0-default-state {
3244 drive-strength = <2>;
3245 bias-pull-up;
3248 cci0_sleep: cci0-sleep-state {
3252 drive-strength = <2>;
3253 bias-pull-down;
3256 cci1_default: cci1-default-state {
3260 drive-strength = <2>;
3261 bias-pull-up;
3264 cci1_sleep: cci1-sleep-state {
3268 drive-strength = <2>;
3269 bias-pull-down;
3272 cci2_default: cci2-default-state {
3276 drive-strength = <2>;
3277 bias-pull-up;
3280 cci2_sleep: cci2-sleep-state {
3284 drive-strength = <2>;
3285 bias-pull-down;
3288 cci3_default: cci3-default-state {
3292 drive-strength = <2>;
3293 bias-pull-up;
3296 cci3_sleep: cci3-sleep-state {
3300 drive-strength = <2>;
3301 bias-pull-down;
3304 pcie0_default_state: pcie0-default-state {
3305 perst-pins {
3308 drive-strength = <2>;
3309 bias-pull-down;
3312 clkreq-pins {
3315 drive-strength = <2>;
3316 bias-pull-up;
3319 wake-pins {
3322 drive-strength = <2>;
3323 bias-pull-up;
3327 pcie1_default_state: pcie1-default-state {
3328 perst-pins {
3331 drive-strength = <2>;
3332 bias-pull-down;
3335 clkreq-pins {
3338 drive-strength = <2>;
3339 bias-pull-up;
3342 wake-pins {
3345 drive-strength = <2>;
3346 bias-pull-up;
3350 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3355 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3360 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3365 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3370 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3375 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3380 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3385 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3390 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3395 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3400 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3405 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3410 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3413 drive-strength = <2>;
3414 bias-pull-up;
3417 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3420 drive-strength = <2>;
3421 bias-pull-up;
3424 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3429 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3434 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3439 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3444 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3449 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3454 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3459 qup_spi0_cs: qup-spi0-cs-state {
3464 qup_spi0_data_clk: qup-spi0-data-clk-state {
3469 qup_spi1_cs: qup-spi1-cs-state {
3474 qup_spi1_data_clk: qup-spi1-data-clk-state {
3479 qup_spi2_cs: qup-spi2-cs-state {
3484 qup_spi2_data_clk: qup-spi2-data-clk-state {
3489 qup_spi3_cs: qup-spi3-cs-state {
3494 qup_spi3_data_clk: qup-spi3-data-clk-state {
3499 qup_spi4_cs: qup-spi4-cs-state {
3502 drive-strength = <6>;
3503 bias-disable;
3506 qup_spi4_data_clk: qup-spi4-data-clk-state {
3511 qup_spi5_cs: qup-spi5-cs-state {
3516 qup_spi5_data_clk: qup-spi5-data-clk-state {
3521 qup_spi6_cs: qup-spi6-cs-state {
3526 qup_spi6_data_clk: qup-spi6-data-clk-state {
3531 qup_spi8_cs: qup-spi8-cs-state {
3536 qup_spi8_data_clk: qup-spi8-data-clk-state {
3541 qup_spi9_cs: qup-spi9-cs-state {
3546 qup_spi9_data_clk: qup-spi9-data-clk-state {
3551 qup_spi10_cs: qup-spi10-cs-state {
3556 qup_spi10_data_clk: qup-spi10-data-clk-state {
3561 qup_spi11_cs: qup-spi11-cs-state {
3566 qup_spi11_data_clk: qup-spi11-data-clk-state {
3571 qup_spi12_cs: qup-spi12-cs-state {
3576 qup_spi12_data_clk: qup-spi12-data-clk-state {
3581 qup_spi13_cs: qup-spi13-cs-state {
3586 qup_spi13_data_clk: qup-spi13-data-clk-state {
3591 qup_spi14_cs: qup-spi14-cs-state {
3596 qup_spi14_data_clk: qup-spi14-data-clk-state {
3601 qup_spi15_cs: qup-spi15-cs-state {
3606 qup_spi15_data_clk: qup-spi15-data-clk-state {
3611 qup_spi16_cs: qup-spi16-cs-state {
3616 qup_spi16_data_clk: qup-spi16-data-clk-state {
3621 qup_spi17_cs: qup-spi17-cs-state {
3626 qup_spi17_data_clk: qup-spi17-data-clk-state {
3631 qup_spi18_cs: qup-spi18-cs-state {
3634 drive-strength = <6>;
3635 bias-disable;
3638 qup_spi18_data_clk: qup-spi18-data-clk-state {
3641 drive-strength = <6>;
3642 bias-disable;
3645 qup_spi19_cs: qup-spi19-cs-state {
3648 drive-strength = <6>;
3649 bias-disable;
3652 qup_spi19_data_clk: qup-spi19-data-clk-state {
3655 drive-strength = <6>;
3656 bias-disable;
3659 qup_spi20_cs: qup-spi20-cs-state {
3664 qup_spi20_data_clk: qup-spi20-data-clk-state {
3669 qup_spi21_cs: qup-spi21-cs-state {
3674 qup_spi21_data_clk: qup-spi21-data-clk-state {
3679 qup_uart7_rx: qup-uart7-rx-state {
3682 drive-strength = <2>;
3683 bias-disable;
3686 qup_uart7_tx: qup-uart7-tx-state {
3689 drive-strength = <2>;
3690 bias-disable;
3693 qup_uart20_default: qup-uart20-default-state {
3700 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
3703 gpio-controller;
3704 #gpio-cells = <2>;
3705 gpio-ranges = <&lpass_tlmm 0 0 23>;
3709 clock-names = "core", "audio";
3711 tx_swr_active: tx-swr-active-state {
3712 clk-pins {
3715 drive-strength = <2>;
3716 slew-rate = <1>;
3717 bias-disable;
3720 data-pins {
3723 drive-strength = <2>;
3724 slew-rate = <1>;
3725 bias-bus-hold;
3729 rx_swr_active: rx-swr-active-state {
3730 clk-pins {
3733 drive-strength = <2>;
3734 slew-rate = <1>;
3735 bias-disable;
3738 data-pins {
3741 drive-strength = <2>;
3742 slew-rate = <1>;
3743 bias-bus-hold;
3747 dmic01_default: dmic01-default-state {
3748 clk-pins {
3751 drive-strength = <8>;
3752 output-high;
3755 data-pins {
3758 drive-strength = <8>;
3762 dmic02_default: dmic02-default-state {
3763 clk-pins {
3766 drive-strength = <8>;
3767 output-high;
3770 data-pins {
3773 drive-strength = <8>;
3777 wsa_swr_active: wsa-swr-active-state {
3778 clk-pins {
3781 drive-strength = <2>;
3782 slew-rate = <1>;
3783 bias-disable;
3786 data-pins {
3789 drive-strength = <2>;
3790 slew-rate = <1>;
3791 bias-bus-hold;
3795 wsa2_swr_active: wsa2-swr-active-state {
3796 clk-pins {
3799 drive-strength = <2>;
3800 slew-rate = <1>;
3801 bias-disable;
3804 data-pins {
3807 drive-strength = <2>;
3808 slew-rate = <1>;
3809 bias-bus-hold;
3815 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
3819 #address-cells = <1>;
3820 #size-cells = <1>;
3822 pil-reloc@94c {
3823 compatible = "qcom,pil-reloc-info";
3829 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
3831 #iommu-cells = <2>;
3832 #global-interrupts = <1>;
3932 intc: interrupt-controller@17100000 {
3933 compatible = "arm,gic-v3";
3934 #interrupt-cells = <3>;
3935 interrupt-controller;
3936 #redistributor-regions = <1>;
3937 redistributor-stride = <0x0 0x40000>;
3941 #address-cells = <2>;
3942 #size-cells = <2>;
3945 gic_its: msi-controller@17140000 {
3946 compatible = "arm,gic-v3-its";
3948 msi-controller;
3949 #msi-cells = <1>;
3954 compatible = "arm,armv7-timer-mem";
3955 #address-cells = <1>;
3956 #size-cells = <1>;
3959 clock-frequency = <19200000>;
3962 frame-number = <0>;
3970 frame-number = <1>;
3977 frame-number = <2>;
3984 frame-number = <3>;
3991 frame-number = <4>;
3998 frame-number = <5>;
4005 frame-number = <6>;
4014 compatible = "qcom,rpmh-rsc";
4019 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4023 qcom,tcs-offset = <0xd00>;
4024 qcom,drv-id = <2>;
4025 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4027 power-domains = <&CLUSTER_PD>;
4029 apps_bcm_voter: bcm-voter {
4030 compatible = "qcom,bcm-voter";
4033 rpmhcc: clock-controller {
4034 compatible = "qcom,sm8450-rpmh-clk";
4035 #clock-cells = <1>;
4036 clock-names = "xo";
4040 rpmhpd: power-controller {
4041 compatible = "qcom,sm8450-rpmhpd";
4042 #power-domain-cells = <1>;
4043 operating-points-v2 = <&rpmhpd_opp_table>;
4045 rpmhpd_opp_table: opp-table {
4046 compatible = "operating-points-v2";
4049 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4053 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4057 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4061 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4065 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4069 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4073 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4077 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4081 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4085 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4089 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4093 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4097 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4101 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4108 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4112 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4114 clock-names = "xo", "alternate";
4118 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4119 #freq-domain-cells = <1>;
4120 #clock-cells = <1>;
4124 compatible = "qcom,sm8450-gem-noc";
4126 #interconnect-cells = <2>;
4127 qcom,bcm-voters = <&apps_bcm_voter>;
4130 system-cache-controller@19200000 {
4131 compatible = "qcom,sm8450-llcc";
4135 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4141 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4142 "jedec,ufs-2.0";
4146 phy-names = "ufsphy";
4147 lanes-per-direction = <2>;
4148 #reset-cells = <1>;
4150 reset-names = "rst";
4152 power-domains = <&gcc UFS_PHY_GDSC>;
4155 dma-coherent;
4159 interconnect-names = "ufs-ddr", "cpu-ufs";
4160 clock-names =
4178 freq-table-hz =
4193 compatible = "qcom,sm8450-qmp-ufs-phy";
4195 #address-cells = <2>;
4196 #size-cells = <2>;
4198 clock-names = "ref", "ref_aux", "qref";
4203 power-domains = <&gcc UFS_PHY_GDSC>;
4206 reset-names = "ufsphy";
4215 #clock-cells = <1>;
4216 #phy-cells = <0>;
4221 compatible = "qcom,sm8450-inline-crypto-engine",
4222 "qcom,inline-crypto-engine";
4227 cryptobam: dma-controller@1dc4000 {
4228 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4231 #dma-cells = <1>;
4233 qcom,controlled-remotely;
4242 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4245 dma-names = "rx", "tx";
4252 interconnect-names = "memory";
4256 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4261 interrupt-names = "hc_irq", "pwr_irq";
4266 clock-names = "iface", "core", "xo";
4270 interconnect-names = "sdhc-ddr","cpu-sdhc";
4272 power-domains = <&rpmhpd RPMHPD_CX>;
4273 operating-points-v2 = <&sdhc2_opp_table>;
4274 bus-width = <4>;
4275 dma-coherent;
4277 /* Forbid SDR104/SDR50 - broken hw! */
4278 sdhci-caps-mask = <0x3 0x0>;
4282 sdhc2_opp_table: opp-table {
4283 compatible = "operating-points-v2";
4285 opp-100000000 {
4286 opp-hz = /bits/ 64 <100000000>;
4287 required-opps = <&rpmhpd_opp_low_svs>;
4290 opp-202000000 {
4291 opp-hz = /bits/ 64 <202000000>;
4292 required-opps = <&rpmhpd_opp_svs_l1>;
4298 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4301 #address-cells = <2>;
4302 #size-cells = <2>;
4311 clock-names = "cfg_noc",
4318 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4320 assigned-clock-rates = <19200000>, <200000000>;
4322 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4326 interrupt-names = "hs_phy_irq",
4331 power-domains = <&gcc USB30_PRIM_GDSC>;
4337 interconnect-names = "usb-ddr", "apps-usb";
4347 phy-names = "usb2-phy", "usb3-phy";
4350 #address-cells = <1>;
4351 #size-cells = <0>;
4371 compatible = "qcom,sm8450-nsp-noc";
4373 #interconnect-cells = <2>;
4374 qcom,bcm-voters = <&apps_bcm_voter>;
4378 compatible = "qcom,sm8450-lpass-ag-noc";
4380 #interconnect-cells = <2>;
4381 qcom,bcm-voters = <&apps_bcm_voter>;
4388 thermal-zones {
4389 aoss0-thermal {
4390 polling-delay-passive = <0>;
4391 polling-delay = <0>;
4392 thermal-sensors = <&tsens0 0>;
4395 thermal-engine-config {
4398 type = "passive";
4401 reset-mon-cfg {
4404 type = "passive";
4409 cpuss0-thermal {
4410 polling-delay-passive = <0>;
4411 polling-delay = <0>;
4412 thermal-sensors = <&tsens0 1>;
4415 thermal-engine-config {
4418 type = "passive";
4421 reset-mon-cfg {
4424 type = "passive";
4429 cpuss1-thermal {
4430 polling-delay-passive = <0>;
4431 polling-delay = <0>;
4432 thermal-sensors = <&tsens0 2>;
4435 thermal-engine-config {
4438 type = "passive";
4441 reset-mon-cfg {
4444 type = "passive";
4449 cpuss3-thermal {
4450 polling-delay-passive = <0>;
4451 polling-delay = <0>;
4452 thermal-sensors = <&tsens0 3>;
4455 thermal-engine-config {
4458 type = "passive";
4461 reset-mon-cfg {
4464 type = "passive";
4469 cpuss4-thermal {
4470 polling-delay-passive = <0>;
4471 polling-delay = <0>;
4472 thermal-sensors = <&tsens0 4>;
4475 thermal-engine-config {
4478 type = "passive";
4481 reset-mon-cfg {
4484 type = "passive";
4489 cpu4-top-thermal {
4490 polling-delay-passive = <0>;
4491 polling-delay = <0>;
4492 thermal-sensors = <&tsens0 5>;
4495 cpu4_top_alert0: trip-point0 {
4498 type = "passive";
4501 cpu4_top_alert1: trip-point1 {
4504 type = "passive";
4507 cpu4_top_crit: cpu-crit {
4515 cpu4-bottom-thermal {
4516 polling-delay-passive = <0>;
4517 polling-delay = <0>;
4518 thermal-sensors = <&tsens0 6>;
4521 cpu4_bottom_alert0: trip-point0 {
4524 type = "passive";
4527 cpu4_bottom_alert1: trip-point1 {
4530 type = "passive";
4533 cpu4_bottom_crit: cpu-crit {
4541 cpu5-top-thermal {
4542 polling-delay-passive = <0>;
4543 polling-delay = <0>;
4544 thermal-sensors = <&tsens0 7>;
4547 cpu5_top_alert0: trip-point0 {
4550 type = "passive";
4553 cpu5_top_alert1: trip-point1 {
4556 type = "passive";
4559 cpu5_top_crit: cpu-crit {
4567 cpu5-bottom-thermal {
4568 polling-delay-passive = <0>;
4569 polling-delay = <0>;
4570 thermal-sensors = <&tsens0 8>;
4573 cpu5_bottom_alert0: trip-point0 {
4576 type = "passive";
4579 cpu5_bottom_alert1: trip-point1 {
4582 type = "passive";
4585 cpu5_bottom_crit: cpu-crit {
4593 cpu6-top-thermal {
4594 polling-delay-passive = <0>;
4595 polling-delay = <0>;
4596 thermal-sensors = <&tsens0 9>;
4599 cpu6_top_alert0: trip-point0 {
4602 type = "passive";
4605 cpu6_top_alert1: trip-point1 {
4608 type = "passive";
4611 cpu6_top_crit: cpu-crit {
4619 cpu6-bottom-thermal {
4620 polling-delay-passive = <0>;
4621 polling-delay = <0>;
4622 thermal-sensors = <&tsens0 10>;
4625 cpu6_bottom_alert0: trip-point0 {
4628 type = "passive";
4631 cpu6_bottom_alert1: trip-point1 {
4634 type = "passive";
4637 cpu6_bottom_crit: cpu-crit {
4645 cpu7-top-thermal {
4646 polling-delay-passive = <0>;
4647 polling-delay = <0>;
4648 thermal-sensors = <&tsens0 11>;
4651 cpu7_top_alert0: trip-point0 {
4654 type = "passive";
4657 cpu7_top_alert1: trip-point1 {
4660 type = "passive";
4663 cpu7_top_crit: cpu-crit {
4671 cpu7-middle-thermal {
4672 polling-delay-passive = <0>;
4673 polling-delay = <0>;
4674 thermal-sensors = <&tsens0 12>;
4677 cpu7_middle_alert0: trip-point0 {
4680 type = "passive";
4683 cpu7_middle_alert1: trip-point1 {
4686 type = "passive";
4689 cpu7_middle_crit: cpu-crit {
4697 cpu7-bottom-thermal {
4698 polling-delay-passive = <0>;
4699 polling-delay = <0>;
4700 thermal-sensors = <&tsens0 13>;
4703 cpu7_bottom_alert0: trip-point0 {
4706 type = "passive";
4709 cpu7_bottom_alert1: trip-point1 {
4712 type = "passive";
4715 cpu7_bottom_crit: cpu-crit {
4723 gpu-top-thermal {
4724 polling-delay-passive = <10>;
4725 polling-delay = <0>;
4726 thermal-sensors = <&tsens0 14>;
4729 thermal-engine-config {
4732 type = "passive";
4735 thermal-hal-config {
4738 type = "passive";
4741 reset-mon-cfg {
4744 type = "passive";
4747 gpu0_tj_cfg: tj-cfg {
4750 type = "passive";
4755 gpu-bottom-thermal {
4756 polling-delay-passive = <10>;
4757 polling-delay = <0>;
4758 thermal-sensors = <&tsens0 15>;
4761 thermal-engine-config {
4764 type = "passive";
4767 thermal-hal-config {
4770 type = "passive";
4773 reset-mon-cfg {
4776 type = "passive";
4779 gpu1_tj_cfg: tj-cfg {
4782 type = "passive";
4787 aoss1-thermal {
4788 polling-delay-passive = <0>;
4789 polling-delay = <0>;
4790 thermal-sensors = <&tsens1 0>;
4793 thermal-engine-config {
4796 type = "passive";
4799 reset-mon-cfg {
4802 type = "passive";
4807 cpu0-thermal {
4808 polling-delay-passive = <0>;
4809 polling-delay = <0>;
4810 thermal-sensors = <&tsens1 1>;
4813 cpu0_alert0: trip-point0 {
4816 type = "passive";
4819 cpu0_alert1: trip-point1 {
4822 type = "passive";
4825 cpu0_crit: cpu-crit {
4833 cpu1-thermal {
4834 polling-delay-passive = <0>;
4835 polling-delay = <0>;
4836 thermal-sensors = <&tsens1 2>;
4839 cpu1_alert0: trip-point0 {
4842 type = "passive";
4845 cpu1_alert1: trip-point1 {
4848 type = "passive";
4851 cpu1_crit: cpu-crit {
4859 cpu2-thermal {
4860 polling-delay-passive = <0>;
4861 polling-delay = <0>;
4862 thermal-sensors = <&tsens1 3>;
4865 cpu2_alert0: trip-point0 {
4868 type = "passive";
4871 cpu2_alert1: trip-point1 {
4874 type = "passive";
4877 cpu2_crit: cpu-crit {
4885 cpu3-thermal {
4886 polling-delay-passive = <0>;
4887 polling-delay = <0>;
4888 thermal-sensors = <&tsens1 4>;
4891 cpu3_alert0: trip-point0 {
4894 type = "passive";
4897 cpu3_alert1: trip-point1 {
4900 type = "passive";
4903 cpu3_crit: cpu-crit {
4911 cdsp0-thermal {
4912 polling-delay-passive = <10>;
4913 polling-delay = <0>;
4914 thermal-sensors = <&tsens1 5>;
4917 thermal-engine-config {
4920 type = "passive";
4923 thermal-hal-config {
4926 type = "passive";
4929 reset-mon-cfg {
4932 type = "passive";
4935 cdsp_0_config: junction-config {
4938 type = "passive";
4943 cdsp1-thermal {
4944 polling-delay-passive = <10>;
4945 polling-delay = <0>;
4946 thermal-sensors = <&tsens1 6>;
4949 thermal-engine-config {
4952 type = "passive";
4955 thermal-hal-config {
4958 type = "passive";
4961 reset-mon-cfg {
4964 type = "passive";
4967 cdsp_1_config: junction-config {
4970 type = "passive";
4975 cdsp2-thermal {
4976 polling-delay-passive = <10>;
4977 polling-delay = <0>;
4978 thermal-sensors = <&tsens1 7>;
4981 thermal-engine-config {
4984 type = "passive";
4987 thermal-hal-config {
4990 type = "passive";
4993 reset-mon-cfg {
4996 type = "passive";
4999 cdsp_2_config: junction-config {
5002 type = "passive";
5007 video-thermal {
5008 polling-delay-passive = <0>;
5009 polling-delay = <0>;
5010 thermal-sensors = <&tsens1 8>;
5013 thermal-engine-config {
5016 type = "passive";
5019 reset-mon-cfg {
5022 type = "passive";
5027 mem-thermal {
5028 polling-delay-passive = <10>;
5029 polling-delay = <0>;
5030 thermal-sensors = <&tsens1 9>;
5033 thermal-engine-config {
5036 type = "passive";
5039 ddr_config0: ddr0-config {
5042 type = "passive";
5045 reset-mon-cfg {
5048 type = "passive";
5053 modem0-thermal {
5054 polling-delay-passive = <0>;
5055 polling-delay = <0>;
5056 thermal-sensors = <&tsens1 10>;
5059 thermal-engine-config {
5062 type = "passive";
5065 mdmss0_config0: mdmss0-config0 {
5068 type = "passive";
5071 mdmss0_config1: mdmss0-config1 {
5074 type = "passive";
5077 reset-mon-cfg {
5080 type = "passive";
5085 modem1-thermal {
5086 polling-delay-passive = <0>;
5087 polling-delay = <0>;
5088 thermal-sensors = <&tsens1 11>;
5091 thermal-engine-config {
5094 type = "passive";
5097 mdmss1_config0: mdmss1-config0 {
5100 type = "passive";
5103 mdmss1_config1: mdmss1-config1 {
5106 type = "passive";
5109 reset-mon-cfg {
5112 type = "passive";
5117 modem2-thermal {
5118 polling-delay-passive = <0>;
5119 polling-delay = <0>;
5120 thermal-sensors = <&tsens1 12>;
5123 thermal-engine-config {
5126 type = "passive";
5129 mdmss2_config0: mdmss2-config0 {
5132 type = "passive";
5135 mdmss2_config1: mdmss2-config1 {
5138 type = "passive";
5141 reset-mon-cfg {
5144 type = "passive";
5149 modem3-thermal {
5150 polling-delay-passive = <0>;
5151 polling-delay = <0>;
5152 thermal-sensors = <&tsens1 13>;
5155 thermal-engine-config {
5158 type = "passive";
5161 mdmss3_config0: mdmss3-config0 {
5164 type = "passive";
5167 mdmss3_config1: mdmss3-config1 {
5170 type = "passive";
5173 reset-mon-cfg {
5176 type = "passive";
5181 camera0-thermal {
5182 polling-delay-passive = <0>;
5183 polling-delay = <0>;
5184 thermal-sensors = <&tsens1 14>;
5187 thermal-engine-config {
5190 type = "passive";
5193 reset-mon-cfg {
5196 type = "passive";
5201 camera1-thermal {
5202 polling-delay-passive = <0>;
5203 polling-delay = <0>;
5204 thermal-sensors = <&tsens1 15>;
5207 thermal-engine-config {
5210 type = "passive";
5213 reset-mon-cfg {
5216 type = "passive";
5223 compatible = "arm,armv8-timer";
5228 clock-frequency = <19200000>;