Lines Matching +full:msm8996 +full:- +full:cci
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/mailbox/qcom-ipcc.h>
15 #include <dt-bindings/phy/phy-qcom-qmp.h>
16 #include <dt-bindings/power/qcom,rpmhpd.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/interconnect/qcom,icc.h>
19 #include <dt-bindings/interconnect/qcom,sm8450.h>
20 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <76800000>;
40 sleep_clk: sleep-clk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32764>;
48 #address-cells = <2>;
49 #size-cells = <0>;
55 enable-method = "psci";
56 next-level-cache = <&L2_0>;
57 power-domains = <&CPU_PD0>;
58 power-domain-names = "psci";
59 qcom,freq-domain = <&cpufreq_hw 0>;
60 #cooling-cells = <2>;
62 L2_0: l2-cache {
64 cache-level = <2>;
65 cache-unified;
66 next-level-cache = <&L3_0>;
67 L3_0: l3-cache {
69 cache-level = <3>;
70 cache-unified;
79 enable-method = "psci";
80 next-level-cache = <&L2_100>;
81 power-domains = <&CPU_PD1>;
82 power-domain-names = "psci";
83 qcom,freq-domain = <&cpufreq_hw 0>;
84 #cooling-cells = <2>;
86 L2_100: l2-cache {
88 cache-level = <2>;
89 cache-unified;
90 next-level-cache = <&L3_0>;
98 enable-method = "psci";
99 next-level-cache = <&L2_200>;
100 power-domains = <&CPU_PD2>;
101 power-domain-names = "psci";
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 #cooling-cells = <2>;
105 L2_200: l2-cache {
107 cache-level = <2>;
108 cache-unified;
109 next-level-cache = <&L3_0>;
117 enable-method = "psci";
118 next-level-cache = <&L2_300>;
119 power-domains = <&CPU_PD3>;
120 power-domain-names = "psci";
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 #cooling-cells = <2>;
124 L2_300: l2-cache {
126 cache-level = <2>;
127 cache-unified;
128 next-level-cache = <&L3_0>;
136 enable-method = "psci";
137 next-level-cache = <&L2_400>;
138 power-domains = <&CPU_PD4>;
139 power-domain-names = "psci";
140 qcom,freq-domain = <&cpufreq_hw 1>;
141 #cooling-cells = <2>;
143 L2_400: l2-cache {
145 cache-level = <2>;
146 cache-unified;
147 next-level-cache = <&L3_0>;
155 enable-method = "psci";
156 next-level-cache = <&L2_500>;
157 power-domains = <&CPU_PD5>;
158 power-domain-names = "psci";
159 qcom,freq-domain = <&cpufreq_hw 1>;
160 #cooling-cells = <2>;
162 L2_500: l2-cache {
164 cache-level = <2>;
165 cache-unified;
166 next-level-cache = <&L3_0>;
174 enable-method = "psci";
175 next-level-cache = <&L2_600>;
176 power-domains = <&CPU_PD6>;
177 power-domain-names = "psci";
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 #cooling-cells = <2>;
181 L2_600: l2-cache {
183 cache-level = <2>;
184 cache-unified;
185 next-level-cache = <&L3_0>;
193 enable-method = "psci";
194 next-level-cache = <&L2_700>;
195 power-domains = <&CPU_PD7>;
196 power-domain-names = "psci";
197 qcom,freq-domain = <&cpufreq_hw 2>;
198 #cooling-cells = <2>;
200 L2_700: l2-cache {
202 cache-level = <2>;
203 cache-unified;
204 next-level-cache = <&L3_0>;
208 cpu-map {
244 idle-states {
245 entry-method = "psci";
247 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
248 compatible = "arm,idle-state";
249 idle-state-name = "silver-rail-power-collapse";
250 arm,psci-suspend-param = <0x40000004>;
251 entry-latency-us = <800>;
252 exit-latency-us = <750>;
253 min-residency-us = <4090>;
254 local-timer-stop;
257 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
258 compatible = "arm,idle-state";
259 idle-state-name = "gold-rail-power-collapse";
260 arm,psci-suspend-param = <0x40000004>;
261 entry-latency-us = <600>;
262 exit-latency-us = <1550>;
263 min-residency-us = <4791>;
264 local-timer-stop;
268 domain-idle-states {
269 CLUSTER_SLEEP_0: cluster-sleep-0 {
270 compatible = "domain-idle-state";
271 arm,psci-suspend-param = <0x41000044>;
272 entry-latency-us = <1050>;
273 exit-latency-us = <2500>;
274 min-residency-us = <5309>;
277 CLUSTER_SLEEP_1: cluster-sleep-1 {
278 compatible = "domain-idle-state";
279 arm,psci-suspend-param = <0x4100c344>;
280 entry-latency-us = <2700>;
281 exit-latency-us = <3500>;
282 min-residency-us = <13959>;
289 compatible = "qcom,scm-sm8450", "qcom,scm";
290 qcom,dload-mode = <&tcsr 0x13000>;
292 #reset-cells = <1>;
296 clk_virt: interconnect-0 {
297 compatible = "qcom,sm8450-clk-virt";
298 #interconnect-cells = <2>;
299 qcom,bcm-voters = <&apps_bcm_voter>;
302 mc_virt: interconnect-1 {
303 compatible = "qcom,sm8450-mc-virt";
304 #interconnect-cells = <2>;
305 qcom,bcm-voters = <&apps_bcm_voter>;
315 compatible = "arm,armv8-pmuv3";
320 compatible = "arm,psci-1.0";
323 CPU_PD0: power-domain-cpu0 {
324 #power-domain-cells = <0>;
325 power-domains = <&CLUSTER_PD>;
326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
329 CPU_PD1: power-domain-cpu1 {
330 #power-domain-cells = <0>;
331 power-domains = <&CLUSTER_PD>;
332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
335 CPU_PD2: power-domain-cpu2 {
336 #power-domain-cells = <0>;
337 power-domains = <&CLUSTER_PD>;
338 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
341 CPU_PD3: power-domain-cpu3 {
342 #power-domain-cells = <0>;
343 power-domains = <&CLUSTER_PD>;
344 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
347 CPU_PD4: power-domain-cpu4 {
348 #power-domain-cells = <0>;
349 power-domains = <&CLUSTER_PD>;
350 domain-idle-states = <&BIG_CPU_SLEEP_0>;
353 CPU_PD5: power-domain-cpu5 {
354 #power-domain-cells = <0>;
355 power-domains = <&CLUSTER_PD>;
356 domain-idle-states = <&BIG_CPU_SLEEP_0>;
359 CPU_PD6: power-domain-cpu6 {
360 #power-domain-cells = <0>;
361 power-domains = <&CLUSTER_PD>;
362 domain-idle-states = <&BIG_CPU_SLEEP_0>;
365 CPU_PD7: power-domain-cpu7 {
366 #power-domain-cells = <0>;
367 power-domains = <&CLUSTER_PD>;
368 domain-idle-states = <&BIG_CPU_SLEEP_0>;
371 CLUSTER_PD: power-domain-cpu-cluster0 {
372 #power-domain-cells = <0>;
373 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 qup_opp_table_100mhz: opp-table-qup {
378 compatible = "operating-points-v2";
380 opp-50000000 {
381 opp-hz = /bits/ 64 <50000000>;
382 required-opps = <&rpmhpd_opp_min_svs>;
385 opp-75000000 {
386 opp-hz = /bits/ 64 <75000000>;
387 required-opps = <&rpmhpd_opp_low_svs>;
390 opp-100000000 {
391 opp-hz = /bits/ 64 <100000000>;
392 required-opps = <&rpmhpd_opp_svs>;
396 reserved_memory: reserved-memory {
397 #address-cells = <2>;
398 #size-cells = <2>;
403 no-map;
408 no-map;
413 no-map;
418 no-map;
423 no-map;
427 compatible = "qcom,cmd-db";
429 no-map;
434 no-map;
439 no-map;
444 no-map;
449 no-map;
457 no-map;
462 no-map;
467 no-map;
472 no-map;
477 no-map;
482 no-map;
487 no-map;
492 no-map;
497 no-map;
502 no-map;
507 no-map;
513 no-map;
519 no-map;
524 no-map;
529 no-map;
534 no-map;
538 compatible = "qcom,rmtfs-mem";
540 no-map;
542 qcom,client-id = <1>;
548 no-map;
553 no-map;
562 no-map;
567 no-map;
572 no-map;
577 no-map;
582 no-map;
587 no-map;
592 no-map;
597 no-map;
602 no-map;
607 no-map;
612 no-map;
617 no-map;
622 no-map;
627 no-map;
631 smp2p-adsp {
634 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
640 qcom,local-pid = <0>;
641 qcom,remote-pid = <2>;
643 smp2p_adsp_out: master-kernel {
644 qcom,entry-name = "master-kernel";
645 #qcom,smem-state-cells = <1>;
648 smp2p_adsp_in: slave-kernel {
649 qcom,entry-name = "slave-kernel";
650 interrupt-controller;
651 #interrupt-cells = <2>;
655 smp2p-cdsp {
658 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
664 qcom,local-pid = <0>;
665 qcom,remote-pid = <5>;
667 smp2p_cdsp_out: master-kernel {
668 qcom,entry-name = "master-kernel";
669 #qcom,smem-state-cells = <1>;
672 smp2p_cdsp_in: slave-kernel {
673 qcom,entry-name = "slave-kernel";
674 interrupt-controller;
675 #interrupt-cells = <2>;
679 smp2p-modem {
682 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
688 qcom,local-pid = <0>;
689 qcom,remote-pid = <1>;
691 smp2p_modem_out: master-kernel {
692 qcom,entry-name = "master-kernel";
693 #qcom,smem-state-cells = <1>;
696 smp2p_modem_in: slave-kernel {
697 qcom,entry-name = "slave-kernel";
698 interrupt-controller;
699 #interrupt-cells = <2>;
702 ipa_smp2p_out: ipa-ap-to-modem {
703 qcom,entry-name = "ipa";
704 #qcom,smem-state-cells = <1>;
707 ipa_smp2p_in: ipa-modem-to-ap {
708 qcom,entry-name = "ipa";
709 interrupt-controller;
710 #interrupt-cells = <2>;
714 smp2p-slpi {
717 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
723 qcom,local-pid = <0>;
724 qcom,remote-pid = <3>;
726 smp2p_slpi_out: master-kernel {
727 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells = <1>;
731 smp2p_slpi_in: slave-kernel {
732 qcom,entry-name = "slave-kernel";
733 interrupt-controller;
734 #interrupt-cells = <2>;
739 #address-cells = <2>;
740 #size-cells = <2>;
742 dma-ranges = <0 0 0 0 0x10 0>;
743 compatible = "simple-bus";
745 gcc: clock-controller@100000 {
746 compatible = "qcom,gcc-sm8450";
748 #clock-cells = <1>;
749 #reset-cells = <1>;
750 #power-domain-cells = <1>;
760 clock-names = "bi_tcxo",
771 gpi_dma2: dma-controller@800000 {
772 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
773 #dma-cells = <3>;
787 dma-channels = <12>;
788 dma-channel-mask = <0x7e>;
794 compatible = "qcom,geni-se-qup";
796 clock-names = "m-ahb", "s-ahb";
800 #address-cells = <2>;
801 #size-cells = <2>;
806 compatible = "qcom,geni-i2c";
808 clock-names = "se";
810 pinctrl-names = "default";
811 pinctrl-0 = <&qup_i2c15_data_clk>;
813 #address-cells = <1>;
814 #size-cells = <0>;
818 interconnect-names = "qup-core", "qup-config", "qup-memory";
821 dma-names = "tx", "rx";
826 compatible = "qcom,geni-spi";
828 clock-names = "se";
831 pinctrl-names = "default";
832 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
835 interconnect-names = "qup-core", "qup-config";
838 dma-names = "tx", "rx";
839 #address-cells = <1>;
840 #size-cells = <0>;
845 compatible = "qcom,geni-i2c";
847 clock-names = "se";
849 pinctrl-names = "default";
850 pinctrl-0 = <&qup_i2c16_data_clk>;
852 #address-cells = <1>;
853 #size-cells = <0>;
857 interconnect-names = "qup-core", "qup-config", "qup-memory";
860 dma-names = "tx", "rx";
865 compatible = "qcom,geni-spi";
867 clock-names = "se";
870 pinctrl-names = "default";
871 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
874 interconnect-names = "qup-core", "qup-config";
877 dma-names = "tx", "rx";
878 #address-cells = <1>;
879 #size-cells = <0>;
884 compatible = "qcom,geni-i2c";
886 clock-names = "se";
888 pinctrl-names = "default";
889 pinctrl-0 = <&qup_i2c17_data_clk>;
891 #address-cells = <1>;
892 #size-cells = <0>;
896 interconnect-names = "qup-core", "qup-config", "qup-memory";
899 dma-names = "tx", "rx";
904 compatible = "qcom,geni-spi";
906 clock-names = "se";
909 pinctrl-names = "default";
910 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
913 interconnect-names = "qup-core", "qup-config";
916 dma-names = "tx", "rx";
917 #address-cells = <1>;
918 #size-cells = <0>;
923 compatible = "qcom,geni-i2c";
925 clock-names = "se";
927 pinctrl-names = "default";
928 pinctrl-0 = <&qup_i2c18_data_clk>;
930 #address-cells = <1>;
931 #size-cells = <0>;
935 interconnect-names = "qup-core", "qup-config", "qup-memory";
938 dma-names = "tx", "rx";
943 compatible = "qcom,geni-spi";
945 clock-names = "se";
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
952 interconnect-names = "qup-core", "qup-config";
955 dma-names = "tx", "rx";
956 #address-cells = <1>;
957 #size-cells = <0>;
962 compatible = "qcom,geni-i2c";
964 clock-names = "se";
966 pinctrl-names = "default";
967 pinctrl-0 = <&qup_i2c19_data_clk>;
969 #address-cells = <1>;
970 #size-cells = <0>;
974 interconnect-names = "qup-core", "qup-config", "qup-memory";
977 dma-names = "tx", "rx";
982 compatible = "qcom,geni-spi";
984 clock-names = "se";
987 pinctrl-names = "default";
988 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
991 interconnect-names = "qup-core", "qup-config";
994 dma-names = "tx", "rx";
995 #address-cells = <1>;
996 #size-cells = <0>;
1001 compatible = "qcom,geni-i2c";
1003 clock-names = "se";
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&qup_i2c20_data_clk>;
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1013 interconnect-names = "qup-core", "qup-config", "qup-memory";
1016 dma-names = "tx", "rx";
1021 compatible = "qcom,geni-uart";
1023 clock-names = "se";
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&qup_uart20_default>;
1032 interconnect-names = "qup-core",
1033 "qup-config";
1038 compatible = "qcom,geni-spi";
1040 clock-names = "se";
1043 pinctrl-names = "default";
1044 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1047 interconnect-names = "qup-core", "qup-config";
1050 dma-names = "tx", "rx";
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1057 compatible = "qcom,geni-i2c";
1059 clock-names = "se";
1061 pinctrl-names = "default";
1062 pinctrl-0 = <&qup_i2c21_data_clk>;
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1069 interconnect-names = "qup-core", "qup-config", "qup-memory";
1072 dma-names = "tx", "rx";
1077 compatible = "qcom,geni-spi";
1079 clock-names = "se";
1082 pinctrl-names = "default";
1083 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1086 interconnect-names = "qup-core", "qup-config";
1089 dma-names = "tx", "rx";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1096 gpi_dma0: dma-controller@900000 {
1097 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1098 #dma-cells = <3>;
1112 dma-channels = <12>;
1113 dma-channel-mask = <0x7e>;
1119 compatible = "qcom,geni-se-qup";
1121 clock-names = "m-ahb", "s-ahb";
1126 interconnect-names = "qup-core";
1127 #address-cells = <2>;
1128 #size-cells = <2>;
1133 compatible = "qcom,geni-i2c";
1135 clock-names = "se";
1137 pinctrl-names = "default";
1138 pinctrl-0 = <&qup_i2c0_data_clk>;
1140 #address-cells = <1>;
1141 #size-cells = <0>;
1145 interconnect-names = "qup-core", "qup-config", "qup-memory";
1148 dma-names = "tx", "rx";
1153 compatible = "qcom,geni-spi";
1155 clock-names = "se";
1158 pinctrl-names = "default";
1159 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1160 power-domains = <&rpmhpd RPMHPD_CX>;
1161 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnect-names = "qup-core", "qup-config", "qup-memory";
1168 dma-names = "tx", "rx";
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1175 compatible = "qcom,geni-i2c";
1177 clock-names = "se";
1179 pinctrl-names = "default";
1180 pinctrl-0 = <&qup_i2c1_data_clk>;
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1187 interconnect-names = "qup-core", "qup-config", "qup-memory";
1190 dma-names = "tx", "rx";
1195 compatible = "qcom,geni-spi";
1197 clock-names = "se";
1200 pinctrl-names = "default";
1201 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnect-names = "qup-core", "qup-config", "qup-memory";
1208 dma-names = "tx", "rx";
1209 #address-cells = <1>;
1210 #size-cells = <0>;
1215 compatible = "qcom,geni-i2c";
1217 clock-names = "se";
1219 pinctrl-names = "default";
1220 pinctrl-0 = <&qup_i2c2_data_clk>;
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1227 interconnect-names = "qup-core", "qup-config", "qup-memory";
1230 dma-names = "tx", "rx";
1235 compatible = "qcom,geni-spi";
1237 clock-names = "se";
1240 pinctrl-names = "default";
1241 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnect-names = "qup-core", "qup-config", "qup-memory";
1248 dma-names = "tx", "rx";
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1256 compatible = "qcom,geni-i2c";
1258 clock-names = "se";
1260 pinctrl-names = "default";
1261 pinctrl-0 = <&qup_i2c3_data_clk>;
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1268 interconnect-names = "qup-core", "qup-config", "qup-memory";
1271 dma-names = "tx", "rx";
1276 compatible = "qcom,geni-spi";
1278 clock-names = "se";
1281 pinctrl-names = "default";
1282 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnect-names = "qup-core", "qup-config", "qup-memory";
1289 dma-names = "tx", "rx";
1290 #address-cells = <1>;
1291 #size-cells = <0>;
1296 compatible = "qcom,geni-i2c";
1298 clock-names = "se";
1300 pinctrl-names = "default";
1301 pinctrl-0 = <&qup_i2c4_data_clk>;
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1308 interconnect-names = "qup-core", "qup-config", "qup-memory";
1311 dma-names = "tx", "rx";
1316 compatible = "qcom,geni-spi";
1318 clock-names = "se";
1321 pinctrl-names = "default";
1322 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1323 power-domains = <&rpmhpd RPMHPD_CX>;
1324 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnect-names = "qup-core", "qup-config", "qup-memory";
1331 dma-names = "tx", "rx";
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1338 compatible = "qcom,geni-i2c";
1340 clock-names = "se";
1342 pinctrl-names = "default";
1343 pinctrl-0 = <&qup_i2c5_data_clk>;
1345 #address-cells = <1>;
1346 #size-cells = <0>;
1350 interconnect-names = "qup-core", "qup-config", "qup-memory";
1353 dma-names = "tx", "rx";
1358 compatible = "qcom,geni-spi";
1360 clock-names = "se";
1363 pinctrl-names = "default";
1364 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnect-names = "qup-core", "qup-config", "qup-memory";
1371 dma-names = "tx", "rx";
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1379 compatible = "qcom,geni-i2c";
1381 clock-names = "se";
1383 pinctrl-names = "default";
1384 pinctrl-0 = <&qup_i2c6_data_clk>;
1386 #address-cells = <1>;
1387 #size-cells = <0>;
1391 interconnect-names = "qup-core", "qup-config", "qup-memory";
1394 dma-names = "tx", "rx";
1399 compatible = "qcom,geni-spi";
1401 clock-names = "se";
1404 pinctrl-names = "default";
1405 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnect-names = "qup-core", "qup-config", "qup-memory";
1412 dma-names = "tx", "rx";
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1419 compatible = "qcom,geni-debug-uart";
1421 clock-names = "se";
1423 pinctrl-names = "default";
1424 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1430 interconnect-names = "qup-core",
1431 "qup-config";
1436 gpi_dma1: dma-controller@a00000 {
1437 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1438 #dma-cells = <3>;
1452 dma-channels = <12>;
1453 dma-channel-mask = <0x7e>;
1459 compatible = "qcom,geni-se-qup";
1461 clock-names = "m-ahb", "s-ahb";
1466 interconnect-names = "qup-core";
1467 #address-cells = <2>;
1468 #size-cells = <2>;
1473 compatible = "qcom,geni-i2c";
1475 clock-names = "se";
1477 pinctrl-names = "default";
1478 pinctrl-0 = <&qup_i2c8_data_clk>;
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1485 interconnect-names = "qup-core", "qup-config", "qup-memory";
1488 dma-names = "tx", "rx";
1493 compatible = "qcom,geni-spi";
1495 clock-names = "se";
1498 pinctrl-names = "default";
1499 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnect-names = "qup-core", "qup-config", "qup-memory";
1506 dma-names = "tx", "rx";
1507 #address-cells = <1>;
1508 #size-cells = <0>;
1513 compatible = "qcom,geni-i2c";
1515 clock-names = "se";
1517 pinctrl-names = "default";
1518 pinctrl-0 = <&qup_i2c9_data_clk>;
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1525 interconnect-names = "qup-core", "qup-config", "qup-memory";
1528 dma-names = "tx", "rx";
1533 compatible = "qcom,geni-spi";
1535 clock-names = "se";
1538 pinctrl-names = "default";
1539 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnect-names = "qup-core", "qup-config", "qup-memory";
1546 dma-names = "tx", "rx";
1547 #address-cells = <1>;
1548 #size-cells = <0>;
1553 compatible = "qcom,geni-i2c";
1555 clock-names = "se";
1557 pinctrl-names = "default";
1558 pinctrl-0 = <&qup_i2c10_data_clk>;
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1565 interconnect-names = "qup-core", "qup-config", "qup-memory";
1568 dma-names = "tx", "rx";
1573 compatible = "qcom,geni-spi";
1575 clock-names = "se";
1578 pinctrl-names = "default";
1579 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnect-names = "qup-core", "qup-config", "qup-memory";
1586 dma-names = "tx", "rx";
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1593 compatible = "qcom,geni-i2c";
1595 clock-names = "se";
1597 pinctrl-names = "default";
1598 pinctrl-0 = <&qup_i2c11_data_clk>;
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1605 interconnect-names = "qup-core", "qup-config", "qup-memory";
1608 dma-names = "tx", "rx";
1613 compatible = "qcom,geni-spi";
1615 clock-names = "se";
1618 pinctrl-names = "default";
1619 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnect-names = "qup-core", "qup-config", "qup-memory";
1626 dma-names = "tx", "rx";
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1633 compatible = "qcom,geni-i2c";
1635 clock-names = "se";
1637 pinctrl-names = "default";
1638 pinctrl-0 = <&qup_i2c12_data_clk>;
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1645 interconnect-names = "qup-core", "qup-config", "qup-memory";
1648 dma-names = "tx", "rx";
1653 compatible = "qcom,geni-spi";
1655 clock-names = "se";
1658 pinctrl-names = "default";
1659 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnect-names = "qup-core", "qup-config", "qup-memory";
1666 dma-names = "tx", "rx";
1667 #address-cells = <1>;
1668 #size-cells = <0>;
1673 compatible = "qcom,geni-i2c";
1675 clock-names = "se";
1677 pinctrl-names = "default";
1678 pinctrl-0 = <&qup_i2c13_data_clk>;
1683 interconnect-names = "qup-core", "qup-config", "qup-memory";
1686 dma-names = "tx", "rx";
1687 #address-cells = <1>;
1688 #size-cells = <0>;
1693 compatible = "qcom,geni-spi";
1695 clock-names = "se";
1698 pinctrl-names = "default";
1699 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnect-names = "qup-core", "qup-config", "qup-memory";
1706 dma-names = "tx", "rx";
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1713 compatible = "qcom,geni-i2c";
1715 clock-names = "se";
1717 pinctrl-names = "default";
1718 pinctrl-0 = <&qup_i2c14_data_clk>;
1723 interconnect-names = "qup-core", "qup-config", "qup-memory";
1726 dma-names = "tx", "rx";
1727 #address-cells = <1>;
1728 #size-cells = <0>;
1733 compatible = "qcom,geni-spi";
1735 clock-names = "se";
1738 pinctrl-names = "default";
1739 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnect-names = "qup-core", "qup-config", "qup-memory";
1746 dma-names = "tx", "rx";
1747 #address-cells = <1>;
1748 #size-cells = <0>;
1754 compatible = "qcom,sm8450-prng-ee", "qcom,prng-ee";
1759 compatible = "qcom,pcie-sm8450-pcie0";
1765 reg-names = "parf", "dbi", "elbi", "atu", "config";
1767 linux,pci-domain = <0>;
1768 bus-range = <0x00 0xff>;
1769 num-lanes = <1>;
1771 #address-cells = <3>;
1772 #size-cells = <2>;
1777 msi-map = <0x0 &gic_its 0x5980 0x1>,
1779 msi-map-mask = <0xff00>;
1781 interrupt-names = "msi";
1782 #interrupt-cells = <1>;
1783 interrupt-map-mask = <0 0 0 0x7>;
1784 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1801 clock-names = "pipe",
1814 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1818 reset-names = "pci";
1820 power-domains = <&gcc PCIE_0_GDSC>;
1823 phy-names = "pciephy";
1825 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1826 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1828 pinctrl-names = "default";
1829 pinctrl-0 = <&pcie0_default_state>;
1835 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1837 #address-cells = <2>;
1838 #size-cells = <2>;
1844 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1847 reset-names = "phy";
1849 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1850 assigned-clock-rates = <100000000>;
1860 clock-names = "pipe0";
1862 #clock-cells = <0>;
1863 #phy-cells = <0>;
1864 clock-output-names = "pcie_0_pipe_clk";
1869 compatible = "qcom,pcie-sm8450-pcie1";
1875 reg-names = "parf", "dbi", "elbi", "atu", "config";
1877 linux,pci-domain = <1>;
1878 bus-range = <0x00 0xff>;
1879 num-lanes = <2>;
1881 #address-cells = <3>;
1882 #size-cells = <2>;
1887 msi-map = <0x0 &gic_its 0x5a00 0x1>,
1889 msi-map-mask = <0xff00>;
1891 interrupt-names = "msi";
1892 #interrupt-cells = <1>;
1893 interrupt-map-mask = <0 0 0 0x7>;
1894 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1910 clock-names = "pipe",
1922 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1926 reset-names = "pci";
1928 power-domains = <&gcc PCIE_1_GDSC>;
1931 phy-names = "pciephy";
1933 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1934 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1936 pinctrl-names = "default";
1937 pinctrl-0 = <&pcie1_default_state>;
1943 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1945 #address-cells = <2>;
1946 #size-cells = <2>;
1952 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1955 reset-names = "phy";
1957 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1958 assigned-clock-rates = <100000000>;
1970 clock-names = "pipe0";
1972 #clock-cells = <0>;
1973 #phy-cells = <0>;
1974 clock-output-names = "pcie_1_pipe_clk";
1979 compatible = "qcom,sm8450-config-noc";
1981 #interconnect-cells = <2>;
1982 qcom,bcm-voters = <&apps_bcm_voter>;
1986 compatible = "qcom,sm8450-system-noc";
1988 #interconnect-cells = <2>;
1989 qcom,bcm-voters = <&apps_bcm_voter>;
1993 compatible = "qcom,sm8450-pcie-anoc";
1995 #interconnect-cells = <2>;
1996 qcom,bcm-voters = <&apps_bcm_voter>;
2000 compatible = "qcom,sm8450-aggre1-noc";
2002 #interconnect-cells = <2>;
2005 qcom,bcm-voters = <&apps_bcm_voter>;
2009 compatible = "qcom,sm8450-aggre2-noc";
2011 #interconnect-cells = <2>;
2012 qcom,bcm-voters = <&apps_bcm_voter>;
2020 compatible = "qcom,sm8450-mmss-noc";
2022 #interconnect-cells = <2>;
2023 qcom,bcm-voters = <&apps_bcm_voter>;
2027 compatible = "qcom,tcsr-mutex";
2029 #hwlock-cells = <1>;
2033 compatible = "qcom,sm8450-tcsr", "syscon";
2038 compatible = "qcom,sm8450-usb-hs-phy",
2039 "qcom,usb-snps-hs-7nm-phy";
2042 #phy-cells = <0>;
2045 clock-names = "ref";
2051 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2058 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2062 reset-names = "phy", "common";
2064 #clock-cells = <1>;
2065 #phy-cells = <1>;
2070 #address-cells = <1>;
2071 #size-cells = <0>;
2097 compatible = "qcom,sm8450-slpi-pas";
2100 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2105 interrupt-names = "wdog", "fatal", "ready",
2106 "handover", "stop-ack";
2109 clock-names = "xo";
2111 power-domains = <&rpmhpd RPMHPD_LCX>,
2113 power-domain-names = "lcx", "lmx";
2115 memory-region = <&slpi_mem>;
2119 qcom,smem-states = <&smp2p_slpi_out 0>;
2120 qcom,smem-state-names = "stop";
2124 glink-edge {
2125 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2132 qcom,remote-pid = <3>;
2136 qcom,glink-channels = "fastrpcglink-apps-dsp";
2138 qcom,non-secure-domain;
2139 #address-cells = <1>;
2140 #size-cells = <0>;
2142 compute-cb@1 {
2143 compatible = "qcom,fastrpc-compute-cb";
2148 compute-cb@2 {
2149 compatible = "qcom,fastrpc-compute-cb";
2154 compute-cb@3 {
2155 compatible = "qcom,fastrpc-compute-cb";
2158 /* note: shared-cb = <4> in downstream */
2165 compatible = "qcom,sm8450-adsp-pas";
2168 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2173 interrupt-names = "wdog", "fatal", "ready",
2174 "handover", "stop-ack";
2177 clock-names = "xo";
2179 power-domains = <&rpmhpd RPMHPD_LCX>,
2181 power-domain-names = "lcx", "lmx";
2183 memory-region = <&adsp_mem>;
2187 qcom,smem-states = <&smp2p_adsp_out 0>;
2188 qcom,smem-state-names = "stop";
2192 remoteproc_adsp_glink: glink-edge {
2193 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2200 qcom,remote-pid = <2>;
2204 qcom,glink-channels = "adsp_apps";
2207 #address-cells = <1>;
2208 #size-cells = <0>;
2213 #sound-dai-cells = <0>;
2214 qcom,protection-domain = "avs/audio",
2218 compatible = "qcom,q6apm-dais";
2223 compatible = "qcom,q6apm-lpass-dais";
2224 #sound-dai-cells = <1>;
2231 qcom,protection-domain = "avs/audio",
2234 q6prmcc: clock-controller {
2235 compatible = "qcom,q6prm-lpass-clocks";
2236 #clock-cells = <2>;
2243 qcom,glink-channels = "fastrpcglink-apps-dsp";
2245 qcom,non-secure-domain;
2246 #address-cells = <1>;
2247 #size-cells = <0>;
2249 compute-cb@3 {
2250 compatible = "qcom,fastrpc-compute-cb";
2255 compute-cb@4 {
2256 compatible = "qcom,fastrpc-compute-cb";
2261 compute-cb@5 {
2262 compatible = "qcom,fastrpc-compute-cb";
2271 compatible = "qcom,sm8450-lpass-wsa-macro";
2278 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2279 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2281 assigned-clock-rates = <19200000>, <19200000>;
2283 #clock-cells = <0>;
2284 clock-output-names = "wsa2-mclk";
2285 pinctrl-names = "default";
2286 pinctrl-0 = <&wsa2_swr_active>;
2287 #sound-dai-cells = <1>;
2291 compatible = "qcom,soundwire-v1.7.0";
2295 clock-names = "iface";
2298 qcom,din-ports = <2>;
2299 qcom,dout-ports = <6>;
2301 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2302 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2303 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2304 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2305 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2306 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2307 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2308 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2309 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2311 #address-cells = <2>;
2312 #size-cells = <0>;
2313 #sound-dai-cells = <1>;
2318 compatible = "qcom,sm8450-lpass-rx-macro";
2325 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2327 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2329 assigned-clock-rates = <19200000>, <19200000>;
2331 #clock-cells = <0>;
2332 clock-output-names = "mclk";
2333 pinctrl-names = "default";
2334 pinctrl-0 = <&rx_swr_active>;
2335 #sound-dai-cells = <1>;
2339 compatible = "qcom,soundwire-v1.7.0";
2343 clock-names = "iface";
2345 qcom,din-ports = <0>;
2346 qcom,dout-ports = <5>;
2348 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2349 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2350 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2351 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2352 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2353 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2354 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2355 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2356 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2358 #address-cells = <2>;
2359 #size-cells = <0>;
2360 #sound-dai-cells = <1>;
2365 compatible = "qcom,sm8450-lpass-tx-macro";
2372 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2373 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2375 assigned-clock-rates = <19200000>, <19200000>;
2377 #clock-cells = <0>;
2378 clock-output-names = "mclk";
2379 pinctrl-names = "default";
2380 pinctrl-0 = <&tx_swr_active>;
2381 #sound-dai-cells = <1>;
2385 compatible = "qcom,sm8450-lpass-wsa-macro";
2392 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2394 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2396 assigned-clock-rates = <19200000>, <19200000>;
2398 #clock-cells = <0>;
2399 clock-output-names = "mclk";
2400 pinctrl-names = "default";
2401 pinctrl-0 = <&wsa_swr_active>;
2402 #sound-dai-cells = <1>;
2406 compatible = "qcom,soundwire-v1.7.0";
2410 clock-names = "iface";
2413 qcom,din-ports = <2>;
2414 qcom,dout-ports = <6>;
2416 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2417 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2418 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2419 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2420 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2421 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2422 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2423 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2424 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2426 #address-cells = <2>;
2427 #size-cells = <0>;
2428 #sound-dai-cells = <1>;
2433 compatible = "qcom,soundwire-v1.7.0";
2437 interrupt-names = "core", "wakeup";
2440 clock-names = "iface";
2443 qcom,din-ports = <4>;
2444 qcom,dout-ports = <0>;
2445 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2446 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2447 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2448 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2449 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2450 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2451 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2452 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2453 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2455 #address-cells = <2>;
2456 #size-cells = <0>;
2457 #sound-dai-cells = <1>;
2462 compatible = "qcom,sm8450-lpass-va-macro";
2468 clock-names = "mclk", "macro", "dcodec", "npl";
2469 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2470 assigned-clock-rates = <19200000>;
2472 #clock-cells = <0>;
2473 clock-output-names = "fsgen";
2474 #sound-dai-cells = <1>;
2479 compatible = "qcom,sm8450-cdsp-pas";
2482 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2487 interrupt-names = "wdog", "fatal", "ready",
2488 "handover", "stop-ack";
2491 clock-names = "xo";
2493 power-domains = <&rpmhpd RPMHPD_CX>,
2495 power-domain-names = "cx", "mxc";
2497 memory-region = <&cdsp_mem>;
2501 qcom,smem-states = <&smp2p_cdsp_out 0>;
2502 qcom,smem-state-names = "stop";
2506 glink-edge {
2507 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2514 qcom,remote-pid = <5>;
2518 qcom,glink-channels = "fastrpcglink-apps-dsp";
2520 qcom,non-secure-domain;
2521 #address-cells = <1>;
2522 #size-cells = <0>;
2524 compute-cb@1 {
2525 compatible = "qcom,fastrpc-compute-cb";
2531 compute-cb@2 {
2532 compatible = "qcom,fastrpc-compute-cb";
2538 compute-cb@3 {
2539 compatible = "qcom,fastrpc-compute-cb";
2545 compute-cb@4 {
2546 compatible = "qcom,fastrpc-compute-cb";
2552 compute-cb@5 {
2553 compatible = "qcom,fastrpc-compute-cb";
2559 compute-cb@6 {
2560 compatible = "qcom,fastrpc-compute-cb";
2566 compute-cb@7 {
2567 compatible = "qcom,fastrpc-compute-cb";
2573 compute-cb@8 {
2574 compatible = "qcom,fastrpc-compute-cb";
2586 compatible = "qcom,sm8450-mpss-pas";
2589 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2595 interrupt-names = "wdog", "fatal", "ready", "handover",
2596 "stop-ack", "shutdown-ack";
2599 clock-names = "xo";
2601 power-domains = <&rpmhpd RPMHPD_CX>,
2603 power-domain-names = "cx", "mss";
2605 memory-region = <&mpss_mem>;
2609 qcom,smem-states = <&smp2p_modem_out 0>;
2610 qcom,smem-state-names = "stop";
2614 glink-edge {
2615 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2621 qcom,remote-pid = <1>;
2625 videocc: clock-controller@aaf0000 {
2626 compatible = "qcom,sm8450-videocc";
2630 power-domains = <&rpmhpd RPMHPD_MMCX>;
2631 required-opps = <&rpmhpd_opp_low_svs>;
2632 #clock-cells = <1>;
2633 #reset-cells = <1>;
2634 #power-domain-cells = <1>;
2637 cci0: cci@ac15000 {
2638 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2641 power-domains = <&camcc TITAN_TOP_GDSC>;
2648 clock-names = "camnoc_axi",
2651 "cci",
2653 pinctrl-0 = <&cci0_default &cci1_default>;
2654 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2655 pinctrl-names = "default", "sleep";
2658 #address-cells = <1>;
2659 #size-cells = <0>;
2661 cci0_i2c0: i2c-bus@0 {
2663 clock-frequency = <1000000>;
2664 #address-cells = <1>;
2665 #size-cells = <0>;
2668 cci0_i2c1: i2c-bus@1 {
2670 clock-frequency = <1000000>;
2671 #address-cells = <1>;
2672 #size-cells = <0>;
2676 cci1: cci@ac16000 {
2677 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2680 power-domains = <&camcc TITAN_TOP_GDSC>;
2687 clock-names = "camnoc_axi",
2690 "cci",
2692 pinctrl-0 = <&cci2_default &cci3_default>;
2693 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
2694 pinctrl-names = "default", "sleep";
2697 #address-cells = <1>;
2698 #size-cells = <0>;
2700 cci1_i2c0: i2c-bus@0 {
2702 clock-frequency = <1000000>;
2703 #address-cells = <1>;
2704 #size-cells = <0>;
2707 cci1_i2c1: i2c-bus@1 {
2709 clock-frequency = <1000000>;
2710 #address-cells = <1>;
2711 #size-cells = <0>;
2715 camcc: clock-controller@ade0000 {
2716 compatible = "qcom,sm8450-camcc";
2722 power-domains = <&rpmhpd RPMHPD_MMCX>;
2723 required-opps = <&rpmhpd_opp_low_svs>;
2724 #clock-cells = <1>;
2725 #reset-cells = <1>;
2726 #power-domain-cells = <1>;
2730 mdss: display-subsystem@ae00000 {
2731 compatible = "qcom,sm8450-mdss";
2733 reg-names = "mdss";
2740 interconnect-names = "mdp0-mem",
2741 "mdp1-mem",
2742 "cpu-cfg";
2746 power-domains = <&dispcc MDSS_GDSC>;
2754 interrupt-controller;
2755 #interrupt-cells = <1>;
2759 #address-cells = <2>;
2760 #size-cells = <2>;
2765 mdss_mdp: display-controller@ae01000 {
2766 compatible = "qcom,sm8450-dpu";
2769 reg-names = "mdp", "vbif";
2777 clock-names = "bus",
2784 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2785 assigned-clock-rates = <19200000>;
2787 operating-points-v2 = <&mdp_opp_table>;
2788 power-domains = <&rpmhpd RPMHPD_MMCX>;
2790 interrupt-parent = <&mdss>;
2794 #address-cells = <1>;
2795 #size-cells = <0>;
2800 remote-endpoint = <&mdss_dsi0_in>;
2807 remote-endpoint = <&mdss_dsi1_in>;
2814 remote-endpoint = <&mdss_dp0_in>;
2819 mdp_opp_table: opp-table {
2820 compatible = "operating-points-v2";
2822 opp-172000000 {
2823 opp-hz = /bits/ 64 <172000000>;
2824 required-opps = <&rpmhpd_opp_low_svs_d1>;
2827 opp-200000000 {
2828 opp-hz = /bits/ 64 <200000000>;
2829 required-opps = <&rpmhpd_opp_low_svs>;
2832 opp-325000000 {
2833 opp-hz = /bits/ 64 <325000000>;
2834 required-opps = <&rpmhpd_opp_svs>;
2837 opp-375000000 {
2838 opp-hz = /bits/ 64 <375000000>;
2839 required-opps = <&rpmhpd_opp_svs_l1>;
2842 opp-500000000 {
2843 opp-hz = /bits/ 64 <500000000>;
2844 required-opps = <&rpmhpd_opp_nom>;
2849 mdss_dp0: displayport-controller@ae90000 {
2850 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
2856 interrupt-parent = <&mdss>;
2863 clock-names = "core_iface",
2869 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2871 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2875 phy-names = "dp";
2877 #sound-dai-cells = <0>;
2879 operating-points-v2 = <&dp_opp_table>;
2880 power-domains = <&rpmhpd RPMHPD_MMCX>;
2885 #address-cells = <1>;
2886 #size-cells = <0>;
2891 remote-endpoint = <&dpu_intf0_out>;
2896 dp_opp_table: opp-table {
2897 compatible = "operating-points-v2";
2899 opp-160000000 {
2900 opp-hz = /bits/ 64 <160000000>;
2901 required-opps = <&rpmhpd_opp_low_svs>;
2904 opp-270000000 {
2905 opp-hz = /bits/ 64 <270000000>;
2906 required-opps = <&rpmhpd_opp_svs>;
2909 opp-540000000 {
2910 opp-hz = /bits/ 64 <540000000>;
2911 required-opps = <&rpmhpd_opp_svs_l1>;
2914 opp-810000000 {
2915 opp-hz = /bits/ 64 <810000000>;
2916 required-opps = <&rpmhpd_opp_nom>;
2922 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2924 reg-names = "dsi_ctrl";
2926 interrupt-parent = <&mdss>;
2935 clock-names = "byte",
2942 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2943 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2945 operating-points-v2 = <&mdss_dsi_opp_table>;
2946 power-domains = <&rpmhpd RPMHPD_MMCX>;
2949 phy-names = "dsi";
2951 #address-cells = <1>;
2952 #size-cells = <0>;
2957 #address-cells = <1>;
2958 #size-cells = <0>;
2963 remote-endpoint = <&dpu_intf1_out>;
2974 mdss_dsi_opp_table: opp-table {
2975 compatible = "operating-points-v2";
2977 opp-187500000 {
2978 opp-hz = /bits/ 64 <187500000>;
2979 required-opps = <&rpmhpd_opp_low_svs>;
2982 opp-300000000 {
2983 opp-hz = /bits/ 64 <300000000>;
2984 required-opps = <&rpmhpd_opp_svs>;
2987 opp-358000000 {
2988 opp-hz = /bits/ 64 <358000000>;
2989 required-opps = <&rpmhpd_opp_svs_l1>;
2995 compatible = "qcom,sm8450-dsi-phy-5nm";
2999 reg-names = "dsi_phy",
3003 #clock-cells = <1>;
3004 #phy-cells = <0>;
3008 clock-names = "iface", "ref";
3014 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3016 reg-names = "dsi_ctrl";
3018 interrupt-parent = <&mdss>;
3027 clock-names = "byte",
3034 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3035 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3037 operating-points-v2 = <&mdss_dsi_opp_table>;
3038 power-domains = <&rpmhpd RPMHPD_MMCX>;
3041 phy-names = "dsi";
3043 #address-cells = <1>;
3044 #size-cells = <0>;
3049 #address-cells = <1>;
3050 #size-cells = <0>;
3055 remote-endpoint = <&dpu_intf2_out>;
3068 compatible = "qcom,sm8450-dsi-phy-5nm";
3072 reg-names = "dsi_phy",
3076 #clock-cells = <1>;
3077 #phy-cells = <0>;
3081 clock-names = "iface", "ref";
3087 dispcc: clock-controller@af00000 {
3088 compatible = "qcom,sm8450-dispcc";
3106 power-domains = <&rpmhpd RPMHPD_MMCX>;
3107 required-opps = <&rpmhpd_opp_low_svs>;
3108 #clock-cells = <1>;
3109 #reset-cells = <1>;
3110 #power-domain-cells = <1>;
3114 pdc: interrupt-controller@b220000 {
3115 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3117 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3119 #interrupt-cells = <2>;
3120 interrupt-parent = <&intc>;
3121 interrupt-controller;
3124 tsens0: thermal-sensor@c263000 {
3125 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3131 interrupt-names = "uplow", "critical";
3132 #thermal-sensor-cells = <1>;
3135 tsens1: thermal-sensor@c265000 {
3136 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3142 interrupt-names = "uplow", "critical";
3143 #thermal-sensor-cells = <1>;
3146 aoss_qmp: power-management@c300000 {
3147 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3149 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3153 #clock-cells = <0>;
3157 compatible = "qcom,rpmh-stats";
3162 compatible = "qcom,spmi-pmic-arb";
3168 reg-names = "core",
3173 interrupt-names = "periph_irq";
3174 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3177 interrupt-controller;
3178 #interrupt-cells = <4>;
3179 #address-cells = <2>;
3180 #size-cells = <0>;
3184 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3187 interrupt-controller;
3188 #interrupt-cells = <3>;
3189 #mbox-cells = <2>;
3193 compatible = "qcom,sm8450-tlmm";
3196 gpio-controller;
3197 #gpio-cells = <2>;
3198 interrupt-controller;
3199 #interrupt-cells = <2>;
3200 gpio-ranges = <&tlmm 0 0 211>;
3201 wakeup-parent = <&pdc>;
3203 sdc2_default_state: sdc2-default-state {
3204 clk-pins {
3206 drive-strength = <16>;
3207 bias-disable;
3210 cmd-pins {
3212 drive-strength = <16>;
3213 bias-pull-up;
3216 data-pins {
3218 drive-strength = <16>;
3219 bias-pull-up;
3223 sdc2_sleep_state: sdc2-sleep-state {
3224 clk-pins {
3226 drive-strength = <2>;
3227 bias-disable;
3230 cmd-pins {
3232 drive-strength = <2>;
3233 bias-pull-up;
3236 data-pins {
3238 drive-strength = <2>;
3239 bias-pull-up;
3243 cci0_default: cci0-default-state {
3247 drive-strength = <2>;
3248 bias-pull-up;
3251 cci0_sleep: cci0-sleep-state {
3255 drive-strength = <2>;
3256 bias-pull-down;
3259 cci1_default: cci1-default-state {
3263 drive-strength = <2>;
3264 bias-pull-up;
3267 cci1_sleep: cci1-sleep-state {
3271 drive-strength = <2>;
3272 bias-pull-down;
3275 cci2_default: cci2-default-state {
3279 drive-strength = <2>;
3280 bias-pull-up;
3283 cci2_sleep: cci2-sleep-state {
3287 drive-strength = <2>;
3288 bias-pull-down;
3291 cci3_default: cci3-default-state {
3295 drive-strength = <2>;
3296 bias-pull-up;
3299 cci3_sleep: cci3-sleep-state {
3303 drive-strength = <2>;
3304 bias-pull-down;
3307 pcie0_default_state: pcie0-default-state {
3308 perst-pins {
3311 drive-strength = <2>;
3312 bias-pull-down;
3315 clkreq-pins {
3318 drive-strength = <2>;
3319 bias-pull-up;
3322 wake-pins {
3325 drive-strength = <2>;
3326 bias-pull-up;
3330 pcie1_default_state: pcie1-default-state {
3331 perst-pins {
3334 drive-strength = <2>;
3335 bias-pull-down;
3338 clkreq-pins {
3341 drive-strength = <2>;
3342 bias-pull-up;
3345 wake-pins {
3348 drive-strength = <2>;
3349 bias-pull-up;
3353 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3358 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3363 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3368 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3373 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3378 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3383 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3388 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3393 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3398 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3403 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3408 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3413 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3416 drive-strength = <2>;
3417 bias-pull-up;
3420 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3423 drive-strength = <2>;
3424 bias-pull-up;
3427 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3432 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3437 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3442 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3447 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3452 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3457 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3462 qup_spi0_cs: qup-spi0-cs-state {
3467 qup_spi0_data_clk: qup-spi0-data-clk-state {
3472 qup_spi1_cs: qup-spi1-cs-state {
3477 qup_spi1_data_clk: qup-spi1-data-clk-state {
3482 qup_spi2_cs: qup-spi2-cs-state {
3487 qup_spi2_data_clk: qup-spi2-data-clk-state {
3492 qup_spi3_cs: qup-spi3-cs-state {
3497 qup_spi3_data_clk: qup-spi3-data-clk-state {
3502 qup_spi4_cs: qup-spi4-cs-state {
3505 drive-strength = <6>;
3506 bias-disable;
3509 qup_spi4_data_clk: qup-spi4-data-clk-state {
3514 qup_spi5_cs: qup-spi5-cs-state {
3519 qup_spi5_data_clk: qup-spi5-data-clk-state {
3524 qup_spi6_cs: qup-spi6-cs-state {
3529 qup_spi6_data_clk: qup-spi6-data-clk-state {
3534 qup_spi8_cs: qup-spi8-cs-state {
3539 qup_spi8_data_clk: qup-spi8-data-clk-state {
3544 qup_spi9_cs: qup-spi9-cs-state {
3549 qup_spi9_data_clk: qup-spi9-data-clk-state {
3554 qup_spi10_cs: qup-spi10-cs-state {
3559 qup_spi10_data_clk: qup-spi10-data-clk-state {
3564 qup_spi11_cs: qup-spi11-cs-state {
3569 qup_spi11_data_clk: qup-spi11-data-clk-state {
3574 qup_spi12_cs: qup-spi12-cs-state {
3579 qup_spi12_data_clk: qup-spi12-data-clk-state {
3584 qup_spi13_cs: qup-spi13-cs-state {
3589 qup_spi13_data_clk: qup-spi13-data-clk-state {
3594 qup_spi14_cs: qup-spi14-cs-state {
3599 qup_spi14_data_clk: qup-spi14-data-clk-state {
3604 qup_spi15_cs: qup-spi15-cs-state {
3609 qup_spi15_data_clk: qup-spi15-data-clk-state {
3614 qup_spi16_cs: qup-spi16-cs-state {
3619 qup_spi16_data_clk: qup-spi16-data-clk-state {
3624 qup_spi17_cs: qup-spi17-cs-state {
3629 qup_spi17_data_clk: qup-spi17-data-clk-state {
3634 qup_spi18_cs: qup-spi18-cs-state {
3637 drive-strength = <6>;
3638 bias-disable;
3641 qup_spi18_data_clk: qup-spi18-data-clk-state {
3644 drive-strength = <6>;
3645 bias-disable;
3648 qup_spi19_cs: qup-spi19-cs-state {
3651 drive-strength = <6>;
3652 bias-disable;
3655 qup_spi19_data_clk: qup-spi19-data-clk-state {
3658 drive-strength = <6>;
3659 bias-disable;
3662 qup_spi20_cs: qup-spi20-cs-state {
3667 qup_spi20_data_clk: qup-spi20-data-clk-state {
3672 qup_spi21_cs: qup-spi21-cs-state {
3677 qup_spi21_data_clk: qup-spi21-data-clk-state {
3682 qup_uart7_rx: qup-uart7-rx-state {
3685 drive-strength = <2>;
3686 bias-disable;
3689 qup_uart7_tx: qup-uart7-tx-state {
3692 drive-strength = <2>;
3693 bias-disable;
3696 qup_uart20_default: qup-uart20-default-state {
3703 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
3706 gpio-controller;
3707 #gpio-cells = <2>;
3708 gpio-ranges = <&lpass_tlmm 0 0 23>;
3712 clock-names = "core", "audio";
3714 tx_swr_active: tx-swr-active-state {
3715 clk-pins {
3718 drive-strength = <2>;
3719 slew-rate = <1>;
3720 bias-disable;
3723 data-pins {
3726 drive-strength = <2>;
3727 slew-rate = <1>;
3728 bias-bus-hold;
3732 rx_swr_active: rx-swr-active-state {
3733 clk-pins {
3736 drive-strength = <2>;
3737 slew-rate = <1>;
3738 bias-disable;
3741 data-pins {
3744 drive-strength = <2>;
3745 slew-rate = <1>;
3746 bias-bus-hold;
3750 dmic01_default: dmic01-default-state {
3751 clk-pins {
3754 drive-strength = <8>;
3755 output-high;
3758 data-pins {
3761 drive-strength = <8>;
3765 dmic02_default: dmic02-default-state {
3766 clk-pins {
3769 drive-strength = <8>;
3770 output-high;
3773 data-pins {
3776 drive-strength = <8>;
3780 wsa_swr_active: wsa-swr-active-state {
3781 clk-pins {
3784 drive-strength = <2>;
3785 slew-rate = <1>;
3786 bias-disable;
3789 data-pins {
3792 drive-strength = <2>;
3793 slew-rate = <1>;
3794 bias-bus-hold;
3798 wsa2_swr_active: wsa2-swr-active-state {
3799 clk-pins {
3802 drive-strength = <2>;
3803 slew-rate = <1>;
3804 bias-disable;
3807 data-pins {
3810 drive-strength = <2>;
3811 slew-rate = <1>;
3812 bias-bus-hold;
3818 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
3822 #address-cells = <1>;
3823 #size-cells = <1>;
3825 pil-reloc@94c {
3826 compatible = "qcom,pil-reloc-info";
3832 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
3834 #iommu-cells = <2>;
3835 #global-interrupts = <1>;
3935 intc: interrupt-controller@17100000 {
3936 compatible = "arm,gic-v3";
3937 #interrupt-cells = <3>;
3938 interrupt-controller;
3939 #redistributor-regions = <1>;
3940 redistributor-stride = <0x0 0x40000>;
3944 #address-cells = <2>;
3945 #size-cells = <2>;
3948 gic_its: msi-controller@17140000 {
3949 compatible = "arm,gic-v3-its";
3951 msi-controller;
3952 #msi-cells = <1>;
3957 compatible = "arm,armv7-timer-mem";
3958 #address-cells = <1>;
3959 #size-cells = <1>;
3962 clock-frequency = <19200000>;
3965 frame-number = <0>;
3973 frame-number = <1>;
3980 frame-number = <2>;
3987 frame-number = <3>;
3994 frame-number = <4>;
4001 frame-number = <5>;
4008 frame-number = <6>;
4017 compatible = "qcom,rpmh-rsc";
4022 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4026 qcom,tcs-offset = <0xd00>;
4027 qcom,drv-id = <2>;
4028 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4030 power-domains = <&CLUSTER_PD>;
4032 apps_bcm_voter: bcm-voter {
4033 compatible = "qcom,bcm-voter";
4036 rpmhcc: clock-controller {
4037 compatible = "qcom,sm8450-rpmh-clk";
4038 #clock-cells = <1>;
4039 clock-names = "xo";
4043 rpmhpd: power-controller {
4044 compatible = "qcom,sm8450-rpmhpd";
4045 #power-domain-cells = <1>;
4046 operating-points-v2 = <&rpmhpd_opp_table>;
4048 rpmhpd_opp_table: opp-table {
4049 compatible = "operating-points-v2";
4052 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4056 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4060 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4064 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4068 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4072 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4076 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4080 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4084 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4088 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4092 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4096 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4100 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4104 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4111 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4115 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4117 clock-names = "xo", "alternate";
4121 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4122 #freq-domain-cells = <1>;
4123 #clock-cells = <1>;
4127 compatible = "qcom,sm8450-gem-noc";
4129 #interconnect-cells = <2>;
4130 qcom,bcm-voters = <&apps_bcm_voter>;
4133 system-cache-controller@19200000 {
4134 compatible = "qcom,sm8450-llcc";
4138 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4144 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4145 "jedec,ufs-2.0";
4149 phy-names = "ufsphy";
4150 lanes-per-direction = <2>;
4151 #reset-cells = <1>;
4153 reset-names = "rst";
4155 power-domains = <&gcc UFS_PHY_GDSC>;
4158 dma-coherent;
4162 interconnect-names = "ufs-ddr", "cpu-ufs";
4163 clock-names =
4181 freq-table-hz =
4196 compatible = "qcom,sm8450-qmp-ufs-phy";
4198 #address-cells = <2>;
4199 #size-cells = <2>;
4201 clock-names = "ref", "ref_aux", "qref";
4206 power-domains = <&gcc UFS_PHY_GDSC>;
4209 reset-names = "ufsphy";
4218 #clock-cells = <1>;
4219 #phy-cells = <0>;
4224 compatible = "qcom,sm8450-inline-crypto-engine",
4225 "qcom,inline-crypto-engine";
4230 cryptobam: dma-controller@1dc4000 {
4231 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4234 #dma-cells = <1>;
4236 qcom,controlled-remotely;
4245 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4248 dma-names = "rx", "tx";
4255 interconnect-names = "memory";
4259 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4264 interrupt-names = "hc_irq", "pwr_irq";
4269 clock-names = "iface", "core", "xo";
4273 interconnect-names = "sdhc-ddr","cpu-sdhc";
4275 power-domains = <&rpmhpd RPMHPD_CX>;
4276 operating-points-v2 = <&sdhc2_opp_table>;
4277 bus-width = <4>;
4278 dma-coherent;
4280 /* Forbid SDR104/SDR50 - broken hw! */
4281 sdhci-caps-mask = <0x3 0x0>;
4285 sdhc2_opp_table: opp-table {
4286 compatible = "operating-points-v2";
4288 opp-100000000 {
4289 opp-hz = /bits/ 64 <100000000>;
4290 required-opps = <&rpmhpd_opp_low_svs>;
4293 opp-202000000 {
4294 opp-hz = /bits/ 64 <202000000>;
4295 required-opps = <&rpmhpd_opp_svs_l1>;
4301 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4304 #address-cells = <2>;
4305 #size-cells = <2>;
4314 clock-names = "cfg_noc",
4321 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4323 assigned-clock-rates = <19200000>, <200000000>;
4325 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4329 interrupt-names = "hs_phy_irq",
4334 power-domains = <&gcc USB30_PRIM_GDSC>;
4340 interconnect-names = "usb-ddr", "apps-usb";
4350 phy-names = "usb2-phy", "usb3-phy";
4353 #address-cells = <1>;
4354 #size-cells = <0>;
4374 compatible = "qcom,sm8450-nsp-noc";
4376 #interconnect-cells = <2>;
4377 qcom,bcm-voters = <&apps_bcm_voter>;
4381 compatible = "qcom,sm8450-lpass-ag-noc";
4383 #interconnect-cells = <2>;
4384 qcom,bcm-voters = <&apps_bcm_voter>;
4391 thermal-zones {
4392 aoss0-thermal {
4393 polling-delay-passive = <0>;
4394 polling-delay = <0>;
4395 thermal-sensors = <&tsens0 0>;
4398 thermal-engine-config {
4404 reset-mon-cfg {
4412 cpuss0-thermal {
4413 polling-delay-passive = <0>;
4414 polling-delay = <0>;
4415 thermal-sensors = <&tsens0 1>;
4418 thermal-engine-config {
4424 reset-mon-cfg {
4432 cpuss1-thermal {
4433 polling-delay-passive = <0>;
4434 polling-delay = <0>;
4435 thermal-sensors = <&tsens0 2>;
4438 thermal-engine-config {
4444 reset-mon-cfg {
4452 cpuss3-thermal {
4453 polling-delay-passive = <0>;
4454 polling-delay = <0>;
4455 thermal-sensors = <&tsens0 3>;
4458 thermal-engine-config {
4464 reset-mon-cfg {
4472 cpuss4-thermal {
4473 polling-delay-passive = <0>;
4474 polling-delay = <0>;
4475 thermal-sensors = <&tsens0 4>;
4478 thermal-engine-config {
4484 reset-mon-cfg {
4492 cpu4-top-thermal {
4493 polling-delay-passive = <0>;
4494 polling-delay = <0>;
4495 thermal-sensors = <&tsens0 5>;
4498 cpu4_top_alert0: trip-point0 {
4504 cpu4_top_alert1: trip-point1 {
4510 cpu4_top_crit: cpu-crit {
4518 cpu4-bottom-thermal {
4519 polling-delay-passive = <0>;
4520 polling-delay = <0>;
4521 thermal-sensors = <&tsens0 6>;
4524 cpu4_bottom_alert0: trip-point0 {
4530 cpu4_bottom_alert1: trip-point1 {
4536 cpu4_bottom_crit: cpu-crit {
4544 cpu5-top-thermal {
4545 polling-delay-passive = <0>;
4546 polling-delay = <0>;
4547 thermal-sensors = <&tsens0 7>;
4550 cpu5_top_alert0: trip-point0 {
4556 cpu5_top_alert1: trip-point1 {
4562 cpu5_top_crit: cpu-crit {
4570 cpu5-bottom-thermal {
4571 polling-delay-passive = <0>;
4572 polling-delay = <0>;
4573 thermal-sensors = <&tsens0 8>;
4576 cpu5_bottom_alert0: trip-point0 {
4582 cpu5_bottom_alert1: trip-point1 {
4588 cpu5_bottom_crit: cpu-crit {
4596 cpu6-top-thermal {
4597 polling-delay-passive = <0>;
4598 polling-delay = <0>;
4599 thermal-sensors = <&tsens0 9>;
4602 cpu6_top_alert0: trip-point0 {
4608 cpu6_top_alert1: trip-point1 {
4614 cpu6_top_crit: cpu-crit {
4622 cpu6-bottom-thermal {
4623 polling-delay-passive = <0>;
4624 polling-delay = <0>;
4625 thermal-sensors = <&tsens0 10>;
4628 cpu6_bottom_alert0: trip-point0 {
4634 cpu6_bottom_alert1: trip-point1 {
4640 cpu6_bottom_crit: cpu-crit {
4648 cpu7-top-thermal {
4649 polling-delay-passive = <0>;
4650 polling-delay = <0>;
4651 thermal-sensors = <&tsens0 11>;
4654 cpu7_top_alert0: trip-point0 {
4660 cpu7_top_alert1: trip-point1 {
4666 cpu7_top_crit: cpu-crit {
4674 cpu7-middle-thermal {
4675 polling-delay-passive = <0>;
4676 polling-delay = <0>;
4677 thermal-sensors = <&tsens0 12>;
4680 cpu7_middle_alert0: trip-point0 {
4686 cpu7_middle_alert1: trip-point1 {
4692 cpu7_middle_crit: cpu-crit {
4700 cpu7-bottom-thermal {
4701 polling-delay-passive = <0>;
4702 polling-delay = <0>;
4703 thermal-sensors = <&tsens0 13>;
4706 cpu7_bottom_alert0: trip-point0 {
4712 cpu7_bottom_alert1: trip-point1 {
4718 cpu7_bottom_crit: cpu-crit {
4726 gpu-top-thermal {
4727 polling-delay-passive = <10>;
4728 polling-delay = <0>;
4729 thermal-sensors = <&tsens0 14>;
4732 thermal-engine-config {
4738 thermal-hal-config {
4744 reset-mon-cfg {
4750 gpu0_tj_cfg: tj-cfg {
4758 gpu-bottom-thermal {
4759 polling-delay-passive = <10>;
4760 polling-delay = <0>;
4761 thermal-sensors = <&tsens0 15>;
4764 thermal-engine-config {
4770 thermal-hal-config {
4776 reset-mon-cfg {
4782 gpu1_tj_cfg: tj-cfg {
4790 aoss1-thermal {
4791 polling-delay-passive = <0>;
4792 polling-delay = <0>;
4793 thermal-sensors = <&tsens1 0>;
4796 thermal-engine-config {
4802 reset-mon-cfg {
4810 cpu0-thermal {
4811 polling-delay-passive = <0>;
4812 polling-delay = <0>;
4813 thermal-sensors = <&tsens1 1>;
4816 cpu0_alert0: trip-point0 {
4822 cpu0_alert1: trip-point1 {
4828 cpu0_crit: cpu-crit {
4836 cpu1-thermal {
4837 polling-delay-passive = <0>;
4838 polling-delay = <0>;
4839 thermal-sensors = <&tsens1 2>;
4842 cpu1_alert0: trip-point0 {
4848 cpu1_alert1: trip-point1 {
4854 cpu1_crit: cpu-crit {
4862 cpu2-thermal {
4863 polling-delay-passive = <0>;
4864 polling-delay = <0>;
4865 thermal-sensors = <&tsens1 3>;
4868 cpu2_alert0: trip-point0 {
4874 cpu2_alert1: trip-point1 {
4880 cpu2_crit: cpu-crit {
4888 cpu3-thermal {
4889 polling-delay-passive = <0>;
4890 polling-delay = <0>;
4891 thermal-sensors = <&tsens1 4>;
4894 cpu3_alert0: trip-point0 {
4900 cpu3_alert1: trip-point1 {
4906 cpu3_crit: cpu-crit {
4914 cdsp0-thermal {
4915 polling-delay-passive = <10>;
4916 polling-delay = <0>;
4917 thermal-sensors = <&tsens1 5>;
4920 thermal-engine-config {
4926 thermal-hal-config {
4932 reset-mon-cfg {
4938 cdsp_0_config: junction-config {
4946 cdsp1-thermal {
4947 polling-delay-passive = <10>;
4948 polling-delay = <0>;
4949 thermal-sensors = <&tsens1 6>;
4952 thermal-engine-config {
4958 thermal-hal-config {
4964 reset-mon-cfg {
4970 cdsp_1_config: junction-config {
4978 cdsp2-thermal {
4979 polling-delay-passive = <10>;
4980 polling-delay = <0>;
4981 thermal-sensors = <&tsens1 7>;
4984 thermal-engine-config {
4990 thermal-hal-config {
4996 reset-mon-cfg {
5002 cdsp_2_config: junction-config {
5010 video-thermal {
5011 polling-delay-passive = <0>;
5012 polling-delay = <0>;
5013 thermal-sensors = <&tsens1 8>;
5016 thermal-engine-config {
5022 reset-mon-cfg {
5030 mem-thermal {
5031 polling-delay-passive = <10>;
5032 polling-delay = <0>;
5033 thermal-sensors = <&tsens1 9>;
5036 thermal-engine-config {
5042 ddr_config0: ddr0-config {
5048 reset-mon-cfg {
5056 modem0-thermal {
5057 polling-delay-passive = <0>;
5058 polling-delay = <0>;
5059 thermal-sensors = <&tsens1 10>;
5062 thermal-engine-config {
5068 mdmss0_config0: mdmss0-config0 {
5074 mdmss0_config1: mdmss0-config1 {
5080 reset-mon-cfg {
5088 modem1-thermal {
5089 polling-delay-passive = <0>;
5090 polling-delay = <0>;
5091 thermal-sensors = <&tsens1 11>;
5094 thermal-engine-config {
5100 mdmss1_config0: mdmss1-config0 {
5106 mdmss1_config1: mdmss1-config1 {
5112 reset-mon-cfg {
5120 modem2-thermal {
5121 polling-delay-passive = <0>;
5122 polling-delay = <0>;
5123 thermal-sensors = <&tsens1 12>;
5126 thermal-engine-config {
5132 mdmss2_config0: mdmss2-config0 {
5138 mdmss2_config1: mdmss2-config1 {
5144 reset-mon-cfg {
5152 modem3-thermal {
5153 polling-delay-passive = <0>;
5154 polling-delay = <0>;
5155 thermal-sensors = <&tsens1 13>;
5158 thermal-engine-config {
5164 mdmss3_config0: mdmss3-config0 {
5170 mdmss3_config1: mdmss3-config1 {
5176 reset-mon-cfg {
5184 camera0-thermal {
5185 polling-delay-passive = <0>;
5186 polling-delay = <0>;
5187 thermal-sensors = <&tsens1 14>;
5190 thermal-engine-config {
5196 reset-mon-cfg {
5204 camera1-thermal {
5205 polling-delay-passive = <0>;
5206 polling-delay = <0>;
5207 thermal-sensors = <&tsens1 15>;
5210 thermal-engine-config {
5216 reset-mon-cfg {
5226 compatible = "arm,armv8-timer";
5231 clock-frequency = <19200000>;