Lines Matching +full:0 +full:xae90400
36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
85 clocks = <&cpufreq_hw 0>;
97 reg = <0x0 0x200>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
104 clocks = <&cpufreq_hw 0>;
116 reg = <0x0 0x300>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
123 clocks = <&cpufreq_hw 0>;
135 reg = <0x0 0x400>;
154 reg = <0x0 0x500>;
173 reg = <0x0 0x600>;
192 reg = <0x0 0x700>;
247 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
250 arm,psci-suspend-param = <0x40000004>;
257 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
260 arm,psci-suspend-param = <0x40000004>;
269 CLUSTER_SLEEP_0: cluster-sleep-0 {
271 arm,psci-suspend-param = <0x41000044>;
279 arm,psci-suspend-param = <0x4100c344>;
290 qcom,dload-mode = <&tcsr 0x13000>;
291 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
296 clk_virt: interconnect-0 {
311 reg = <0x0 0xa0000000 0x0 0x0>;
324 #power-domain-cells = <0>;
330 #power-domain-cells = <0>;
336 #power-domain-cells = <0>;
342 #power-domain-cells = <0>;
348 #power-domain-cells = <0>;
354 #power-domain-cells = <0>;
360 #power-domain-cells = <0>;
366 #power-domain-cells = <0>;
372 #power-domain-cells = <0>;
402 reg = <0x0 0x80000000 0x0 0x600000>;
407 reg = <0x0 0x80600000 0x0 0x40000>;
412 reg = <0x0 0x80640000 0x0 0x180000>;
417 reg = <0x0 0x807c0000 0x0 0x40000>;
422 reg = <0x0 0x80800000 0x0 0x60000>;
428 reg = <0x0 0x80860000 0x0 0x20000>;
433 reg = <0x0 0x80880000 0x0 0x20000>;
438 reg = <0x0 0x808a0000 0x0 0x40000>;
443 reg = <0x0 0x808e0000 0x0 0x4000>;
448 reg = <0x0 0x808e4000 0x0 0x10000>;
455 reg = <0x0 0x80900000 0x0 0x200000>;
461 reg = <0x0 0x80b00000 0x0 0x100000>;
466 reg = <0x0 0x80c00000 0x0 0x4600000>;
471 reg = <0x0 0x85700000 0x0 0x700000>;
476 reg = <0x0 0x85e00000 0x0 0x2100000>;
481 reg = <0x0 0x88000000 0x0 0x1900000>;
486 reg = <0x0 0x89900000 0x0 0x2000000>;
491 reg = <0x0 0x8b900000 0x0 0x10000>;
496 reg = <0x0 0x8b910000 0x0 0xa000>;
501 reg = <0x0 0x8b91a000 0x0 0x2000>;
506 reg = <0x0 0x8ba00000 0x0 0x180000>;
512 reg = <0x0 0x8bb80000 0x0 0x60000>;
518 reg = <0x0 0x8bbe0000 0x0 0x20000>;
523 reg = <0x0 0x8bc00000 0x0 0x13200000>;
528 reg = <0x0 0x9ee00000 0x0 0x700000>;
533 reg = <0x0 0x9f500000 0x0 0x800000>;
539 reg = <0x0 0x9fd00000 0x0 0x280000>;
547 reg = <0x0 0xa6e00000 0x0 0x40000>;
552 reg = <0x0 0xa6f00000 0x0 0x100000>;
558 /* Linux kernel image is loaded at 0xa0000000 */
561 reg = <0x0 0xbb000000 0x0 0x5000000>;
566 reg = <0x0 0xc0000000 0x0 0x20000000>;
571 reg = <0x0 0xe0000000 0x0 0x600000>;
576 reg = <0x0 0xe0600000 0x0 0x400000>;
581 reg = <0x0 0xe0a00000 0x0 0x100000>;
586 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
591 reg = <0x0 0xe55f3000 0x0 0x9000>;
596 reg = <0x0 0xe55fc000 0x0 0x4000>;
601 reg = <0x0 0xe5600000 0x0 0x100000>;
606 reg = <0x0 0xe8800000 0x0 0x100000>;
611 reg = <0x0 0xe8900000 0x0 0x1200000>;
616 reg = <0x0 0xe9b00000 0x0 0x500000>;
621 reg = <0x0 0xea000000 0x0 0x3900000>;
626 reg = <0x0 0xed900000 0x0 0x3b00000>;
640 qcom,local-pid = <0>;
664 qcom,local-pid = <0>;
688 qcom,local-pid = <0>;
723 qcom,local-pid = <0>;
738 soc: soc@0 {
741 ranges = <0 0 0 0 0x10 0>;
742 dma-ranges = <0 0 0 0 0x10 0>;
747 reg = <0x0 0x00100000 0x0 0x1f4200>;
755 <0>,
756 <&ufs_mem_phy_lanes 0>,
774 reg = <0 0x00800000 0 0x60000>;
788 dma-channel-mask = <0x7e>;
789 iommus = <&apps_smmu 0x496 0x0>;
795 reg = <0x0 0x008c0000 0x0 0x2000>;
799 iommus = <&apps_smmu 0x483 0x0>;
807 reg = <0x0 0x00880000 0x0 0x4000>;
811 pinctrl-0 = <&qup_i2c15_data_clk>;
814 #size-cells = <0>;
815 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
816 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
817 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
819 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
820 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
827 reg = <0x0 0x00880000 0x0 0x4000>;
832 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
833 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
834 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
836 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
837 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
840 #size-cells = <0>;
846 reg = <0x0 0x00884000 0x0 0x4000>;
850 pinctrl-0 = <&qup_i2c16_data_clk>;
853 #size-cells = <0>;
854 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
855 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
856 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
858 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
866 reg = <0x0 0x00884000 0x0 0x4000>;
871 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
872 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
873 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
875 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 #size-cells = <0>;
885 reg = <0x0 0x00888000 0x0 0x4000>;
889 pinctrl-0 = <&qup_i2c17_data_clk>;
892 #size-cells = <0>;
893 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
894 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
895 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
897 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
905 reg = <0x0 0x00888000 0x0 0x4000>;
910 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
911 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
912 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
914 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 #size-cells = <0>;
924 reg = <0x0 0x0088c000 0x0 0x4000>;
928 pinctrl-0 = <&qup_i2c18_data_clk>;
931 #size-cells = <0>;
932 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
933 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
934 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
936 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
944 reg = <0 0x0088c000 0 0x4000>;
949 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
951 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
953 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 #size-cells = <0>;
963 reg = <0x0 0x00890000 0x0 0x4000>;
967 pinctrl-0 = <&qup_i2c19_data_clk>;
970 #size-cells = <0>;
971 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
972 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
973 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
975 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
983 reg = <0 0x00890000 0 0x4000>;
988 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
989 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
990 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
992 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 #size-cells = <0>;
1002 reg = <0x0 0x00894000 0x0 0x4000>;
1006 pinctrl-0 = <&qup_i2c20_data_clk>;
1009 #size-cells = <0>;
1010 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1011 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1012 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1014 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1022 reg = <0 0x00894000 0 0x4000>;
1026 pinctrl-0 = <&qup_uart20_default>;
1039 reg = <0 0x00894000 0 0x4000>;
1044 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1046 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1048 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 #size-cells = <0>;
1058 reg = <0x0 0x00898000 0x0 0x4000>;
1062 pinctrl-0 = <&qup_i2c21_data_clk>;
1065 #size-cells = <0>;
1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1067 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1068 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1070 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1078 reg = <0 0x00898000 0 0x4000>;
1083 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1084 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1085 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1087 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 #size-cells = <0>;
1099 reg = <0 0x00900000 0 0x60000>;
1113 dma-channel-mask = <0x7e>;
1114 iommus = <&apps_smmu 0x5b6 0x0>;
1120 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 iommus = <&apps_smmu 0x5a3 0x0>;
1125 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1134 reg = <0x0 0x00980000 0x0 0x4000>;
1138 pinctrl-0 = <&qup_i2c0_data_clk>;
1141 #size-cells = <0>;
1142 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1143 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1144 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1146 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1147 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1154 reg = <0x0 0x00980000 0x0 0x4000>;
1159 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1162 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1163 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1164 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1166 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1167 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1170 #size-cells = <0>;
1176 reg = <0x0 0x00984000 0x0 0x4000>;
1180 pinctrl-0 = <&qup_i2c1_data_clk>;
1183 #size-cells = <0>;
1184 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1185 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1186 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1188 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1196 reg = <0x0 0x00984000 0x0 0x4000>;
1201 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1202 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1203 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1204 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1206 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 #size-cells = <0>;
1216 reg = <0x0 0x00988000 0x0 0x4000>;
1220 pinctrl-0 = <&qup_i2c2_data_clk>;
1223 #size-cells = <0>;
1224 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1225 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1226 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1228 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1236 reg = <0x0 0x00988000 0x0 0x4000>;
1241 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1243 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1244 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1246 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 #size-cells = <0>;
1257 reg = <0x0 0x0098c000 0x0 0x4000>;
1261 pinctrl-0 = <&qup_i2c3_data_clk>;
1264 #size-cells = <0>;
1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1266 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1267 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1269 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1277 reg = <0x0 0x0098c000 0x0 0x4000>;
1282 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1284 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1285 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1287 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 #size-cells = <0>;
1297 reg = <0x0 0x00990000 0x0 0x4000>;
1301 pinctrl-0 = <&qup_i2c4_data_clk>;
1304 #size-cells = <0>;
1305 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1306 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1307 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1309 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1317 reg = <0x0 0x00990000 0x0 0x4000>;
1322 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1325 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1326 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1327 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1329 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 #size-cells = <0>;
1339 reg = <0x0 0x00994000 0x0 0x4000>;
1343 pinctrl-0 = <&qup_i2c5_data_clk>;
1346 #size-cells = <0>;
1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1348 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1349 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1351 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1359 reg = <0x0 0x00994000 0x0 0x4000>;
1364 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1365 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1366 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1367 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1369 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 #size-cells = <0>;
1380 reg = <0x0 0x00998000 0x0 0x4000>;
1384 pinctrl-0 = <&qup_i2c6_data_clk>;
1387 #size-cells = <0>;
1388 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1389 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1390 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1392 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1400 reg = <0x0 0x00998000 0x0 0x4000>;
1405 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1406 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1407 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1408 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1410 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 #size-cells = <0>;
1420 reg = <0 0x0099c000 0 0x4000>;
1424 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1439 reg = <0 0x00a00000 0 0x60000>;
1453 dma-channel-mask = <0x7e>;
1454 iommus = <&apps_smmu 0x56 0x0>;
1460 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 iommus = <&apps_smmu 0x43 0x0>;
1465 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1474 reg = <0x0 0x00a80000 0x0 0x4000>;
1478 pinctrl-0 = <&qup_i2c8_data_clk>;
1481 #size-cells = <0>;
1482 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1483 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1484 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1486 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1487 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1494 reg = <0x0 0x00a80000 0x0 0x4000>;
1499 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1500 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1501 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1502 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1504 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1505 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1508 #size-cells = <0>;
1514 reg = <0x0 0x00a84000 0x0 0x4000>;
1518 pinctrl-0 = <&qup_i2c9_data_clk>;
1521 #size-cells = <0>;
1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1523 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1524 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1526 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1534 reg = <0x0 0x00a84000 0x0 0x4000>;
1539 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1540 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1541 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1542 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1544 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 #size-cells = <0>;
1554 reg = <0x0 0x00a88000 0x0 0x4000>;
1558 pinctrl-0 = <&qup_i2c10_data_clk>;
1561 #size-cells = <0>;
1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1563 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1564 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1566 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1574 reg = <0x0 0x00a88000 0x0 0x4000>;
1579 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1580 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1581 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1582 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1584 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 #size-cells = <0>;
1594 reg = <0x0 0x00a8c000 0x0 0x4000>;
1598 pinctrl-0 = <&qup_i2c11_data_clk>;
1601 #size-cells = <0>;
1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1603 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1604 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1606 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1614 reg = <0x0 0x00a8c000 0x0 0x4000>;
1619 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1621 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1622 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1624 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 #size-cells = <0>;
1634 reg = <0x0 0x00a90000 0x0 0x4000>;
1638 pinctrl-0 = <&qup_i2c12_data_clk>;
1641 #size-cells = <0>;
1642 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1643 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1644 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1646 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1654 reg = <0x0 0x00a90000 0x0 0x4000>;
1659 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1661 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1662 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1664 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 #size-cells = <0>;
1674 reg = <0 0x00a94000 0 0x4000>;
1678 pinctrl-0 = <&qup_i2c13_data_clk>;
1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1681 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1682 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1684 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 #size-cells = <0>;
1694 reg = <0x0 0x00a94000 0x0 0x4000>;
1699 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1700 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1701 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1702 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1704 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 #size-cells = <0>;
1714 reg = <0 0x00a98000 0 0x4000>;
1718 pinctrl-0 = <&qup_i2c14_data_clk>;
1720 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1721 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1722 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1724 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 #size-cells = <0>;
1734 reg = <0x0 0x00a98000 0x0 0x4000>;
1739 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1740 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1741 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1742 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1744 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 #size-cells = <0>;
1755 reg = <0 0x010c3000 0 0x1000>;
1760 reg = <0 0x01c00000 0 0x3000>,
1761 <0 0x60000000 0 0xf1d>,
1762 <0 0x60000f20 0 0xa8>,
1763 <0 0x60001000 0 0x1000>,
1764 <0 0x60100000 0 0x100000>;
1767 linux,pci-domain = <0>;
1768 bus-range = <0x00 0xff>;
1774 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1775 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1777 msi-map = <0x0 &gic_its 0x5980 0x1>,
1778 <0x100 &gic_its 0x5981 0x1>;
1779 msi-map-mask = <0xff00>;
1783 interrupt-map-mask = <0 0 0 0x7>;
1784 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1785 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1786 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1787 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1814 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1815 <0x100 &apps_smmu 0x1c01 0x1>;
1829 pinctrl-0 = <&pcie0_default_state>;
1836 reg = <0 0x01c06000 0 0x200>;
1855 reg = <0 0x01c06e00 0 0x200>, /* tx */
1856 <0 0x01c07000 0 0x200>, /* rx */
1857 <0 0x01c06200 0 0x200>, /* pcs */
1858 <0 0x01c06600 0 0x200>; /* pcs_pcie */
1862 #clock-cells = <0>;
1863 #phy-cells = <0>;
1870 reg = <0 0x01c08000 0 0x3000>,
1871 <0 0x40000000 0 0xf1d>,
1872 <0 0x40000f20 0 0xa8>,
1873 <0 0x40001000 0 0x1000>,
1874 <0 0x40100000 0 0x100000>;
1878 bus-range = <0x00 0xff>;
1884 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1885 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1887 msi-map = <0x0 &gic_its 0x5a00 0x1>,
1888 <0x100 &gic_its 0x5a01 0x1>;
1889 msi-map-mask = <0xff00>;
1893 interrupt-map-mask = <0 0 0 0x7>;
1894 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1895 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1896 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1897 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1922 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1923 <0x100 &apps_smmu 0x1c81 0x1>;
1937 pinctrl-0 = <&pcie1_default_state>;
1944 reg = <0 0x01c0f000 0 0x200>;
1963 reg = <0 0x01c0e000 0 0x200>, /* tx */
1964 <0 0x01c0e200 0 0x300>, /* rx */
1965 <0 0x01c0f200 0 0x200>, /* pcs */
1966 <0 0x01c0e800 0 0x200>, /* tx */
1967 <0 0x01c0ea00 0 0x300>, /* rx */
1968 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */
1972 #clock-cells = <0>;
1973 #phy-cells = <0>;
1980 reg = <0 0x01500000 0 0x1c000>;
1987 reg = <0 0x01680000 0 0x1e200>;
1994 reg = <0 0x016c0000 0 0xe280>;
2001 reg = <0 0x016e0000 0 0x1c080>;
2010 reg = <0 0x01700000 0 0x31080>;
2021 reg = <0 0x01740000 0 0x1f080>;
2028 reg = <0x0 0x01f40000 0x0 0x40000>;
2034 reg = <0x0 0x1fc0000 0x0 0x30000>;
2040 reg = <0 0x088e3000 0 0x400>;
2042 #phy-cells = <0>;
2052 reg = <0 0x088e8000 0 0x3000>;
2071 #size-cells = <0>;
2073 port@0 {
2074 reg = <0>;
2098 reg = <0 0x02400000 0 0x4000>;
2101 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2119 qcom,smem-states = <&smp2p_slpi_out 0>;
2139 #size-cells = <0>;
2144 iommus = <&apps_smmu 0x0541 0x0>;
2150 iommus = <&apps_smmu 0x0542 0x0>;
2156 iommus = <&apps_smmu 0x0543 0x0>;
2165 reg = <0 0x031e0000 0 0x1000>;
2176 #clock-cells = <0>;
2179 pinctrl-0 = <&wsa2_swr_active>;
2185 reg = <0 0x031f0000 0 0x2000>;
2194 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2195 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2196 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2197 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2198 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2199 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2200 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2201 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2202 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2205 #size-cells = <0>;
2212 reg = <0 0x03200000 0 0x1000>;
2224 #clock-cells = <0>;
2227 pinctrl-0 = <&rx_swr_active>;
2233 reg = <0 0x03210000 0 0x2000>;
2238 qcom,din-ports = <0>;
2241 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2242 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2243 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2244 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2245 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2246 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2247 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2248 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2249 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2252 #size-cells = <0>;
2259 reg = <0 0x03220000 0 0x1000>;
2270 #clock-cells = <0>;
2273 pinctrl-0 = <&tx_swr_active>;
2279 reg = <0 0x03240000 0 0x1000>;
2291 #clock-cells = <0>;
2294 pinctrl-0 = <&wsa_swr_active>;
2300 reg = <0 0x03250000 0 0x2000>;
2309 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2310 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2311 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2312 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2313 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2314 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2315 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2316 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2317 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2320 #size-cells = <0>;
2327 reg = <0 0x033b0000 0 0x2000>;
2337 qcom,dout-ports = <0>;
2338 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2339 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2340 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2341 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2342 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2343 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2344 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2345 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2346 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2349 #size-cells = <0>;
2356 reg = <0 0x033f0000 0 0x1000>;
2365 #clock-cells = <0>;
2373 reg = <0 0x30000000 0 0x100>;
2376 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2394 qcom,smem-states = <&smp2p_adsp_out 0>;
2415 #size-cells = <0>;
2420 #sound-dai-cells = <0>;
2426 iommus = <&apps_smmu 0x1801 0x0>;
2453 #size-cells = <0>;
2458 iommus = <&apps_smmu 0x1803 0x0>;
2464 iommus = <&apps_smmu 0x1804 0x0>;
2470 iommus = <&apps_smmu 0x1805 0x0>;
2478 reg = <0 0x32300000 0 0x1400000>;
2481 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2499 qcom,smem-states = <&smp2p_cdsp_out 0>;
2519 #size-cells = <0>;
2524 iommus = <&apps_smmu 0x2161 0x0400>,
2525 <&apps_smmu 0x1021 0x1420>;
2531 iommus = <&apps_smmu 0x2162 0x0400>,
2532 <&apps_smmu 0x1022 0x1420>;
2538 iommus = <&apps_smmu 0x2163 0x0400>,
2539 <&apps_smmu 0x1023 0x1420>;
2545 iommus = <&apps_smmu 0x2164 0x0400>,
2546 <&apps_smmu 0x1024 0x1420>;
2552 iommus = <&apps_smmu 0x2165 0x0400>,
2553 <&apps_smmu 0x1025 0x1420>;
2559 iommus = <&apps_smmu 0x2166 0x0400>,
2560 <&apps_smmu 0x1026 0x1420>;
2566 iommus = <&apps_smmu 0x2167 0x0400>,
2567 <&apps_smmu 0x1027 0x1420>;
2573 iommus = <&apps_smmu 0x2168 0x0400>,
2574 <&apps_smmu 0x1028 0x1420>;
2584 reg = <0x0 0x04080000 0x0 0x4040>;
2587 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2606 qcom,smem-states = <&smp2p_modem_out 0>;
2624 reg = <0 0x0aaf0000 0 0x10000>;
2636 reg = <0 0x0ac15000 0 0x1000>;
2650 pinctrl-0 = <&cci0_default &cci1_default>;
2656 #size-cells = <0>;
2658 cci0_i2c0: i2c-bus@0 {
2659 reg = <0>;
2662 #size-cells = <0>;
2669 #size-cells = <0>;
2675 reg = <0 0x0ac16000 0 0x1000>;
2689 pinctrl-0 = <&cci2_default &cci3_default>;
2695 #size-cells = <0>;
2697 cci1_i2c0: i2c-bus@0 {
2698 reg = <0>;
2701 #size-cells = <0>;
2708 #size-cells = <0>;
2714 reg = <0 0x0ade0000 0 0x20000>;
2729 reg = <0 0x0ae00000 0 0x1000>;
2733 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2734 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2754 iommus = <&apps_smmu 0x2800 0x402>;
2764 reg = <0 0x0ae01000 0 0x8f000>,
2765 <0 0x0aeb0000 0 0x2008>;
2788 interrupts = <0>;
2792 #size-cells = <0>;
2794 port@0 {
2795 reg = <0>;
2848 reg = <0 0xae90000 0 0x200>,
2849 <0 0xae90200 0 0x200>,
2850 <0 0xae90400 0 0xc00>,
2851 <0 0xae91000 0 0x400>,
2852 <0 0xae91400 0 0x400>;
2874 #sound-dai-cells = <0>;
2883 #size-cells = <0>;
2885 port@0 {
2886 reg = <0>;
2920 reg = <0 0x0ae94000 0 0x400>;
2940 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2949 #size-cells = <0>;
2955 #size-cells = <0>;
2957 port@0 {
2958 reg = <0>;
2993 reg = <0 0x0ae94400 0 0x200>,
2994 <0 0x0ae94600 0 0x280>,
2995 <0 0x0ae94900 0 0x260>;
3001 #phy-cells = <0>;
3012 reg = <0 0x0ae96000 0 0x400>;
3032 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3041 #size-cells = <0>;
3047 #size-cells = <0>;
3049 port@0 {
3050 reg = <0>;
3066 reg = <0 0x0ae96400 0 0x200>,
3067 <0 0x0ae96600 0 0x280>,
3068 <0 0x0ae96900 0 0x260>;
3074 #phy-cells = <0>;
3086 reg = <0 0x0af00000 0 0x20000>;
3091 <&mdss_dsi0_phy 0>,
3093 <&mdss_dsi1_phy 0>,
3097 <0>, /* dp1 */
3098 <0>,
3099 <0>, /* dp2 */
3100 <0>,
3101 <0>, /* dp3 */
3102 <0>;
3113 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3114 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3123 reg = <0 0x0c263000 0 0x1000>, /* TM */
3124 <0 0x0c222000 0 0x1000>; /* SROT */
3134 reg = <0 0x0c265000 0 0x1000>, /* TM */
3135 <0 0x0c223000 0 0x1000>; /* SROT */
3145 reg = <0 0x0c300000 0 0x400>;
3150 #clock-cells = <0>;
3155 reg = <0 0x0c3f0000 0 0x400>;
3160 reg = <0 0x0c400000 0 0x00003000>,
3161 <0 0x0c500000 0 0x00400000>,
3162 <0 0x0c440000 0 0x00080000>,
3163 <0 0x0c4c0000 0 0x00010000>,
3164 <0 0x0c42d000 0 0x00010000>;
3172 qcom,ee = <0>;
3173 qcom,channel = <0>;
3177 #size-cells = <0>;
3182 reg = <0 0x0ed18000 0 0x1000>;
3191 reg = <0 0x0f100000 0 0x300000>;
3197 gpio-ranges = <&tlmm 0 0 211>;
3701 reg = <0 0x03440000 0x0 0x20000>,
3702 <0 0x034d0000 0x0 0x10000>;
3705 gpio-ranges = <&lpass_tlmm 0 0 23>;
3816 reg = <0 0x146aa000 0 0x1000>;
3817 ranges = <0 0 0x146aa000 0x1000>;
3824 reg = <0x94c 0xc8>;
3830 reg = <0 0x15000000 0 0x100000>;
3937 redistributor-stride = <0x0 0x40000>;
3938 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
3939 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
3947 reg = <0x0 0x17140000 0x0 0x20000>;
3957 ranges = <0 0 0 0x20000000>;
3958 reg = <0x0 0x17420000 0x0 0x1000>;
3962 frame-number = <0>;
3965 reg = <0x17421000 0x1000>,
3966 <0x17422000 0x1000>;
3972 reg = <0x17423000 0x1000>;
3979 reg = <0x17425000 0x1000>;
3986 reg = <0x17427000 0x1000>;
3993 reg = <0x17429000 0x1000>;
4000 reg = <0x1742b000 0x1000>;
4007 reg = <0x1742d000 0x1000>;
4015 reg = <0x0 0x17a00000 0x0 0x10000>,
4016 <0x0 0x17a10000 0x0 0x10000>,
4017 <0x0 0x17a20000 0x0 0x10000>,
4018 <0x0 0x17a30000 0x0 0x10000>;
4019 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4023 qcom,tcs-offset = <0xd00>;
4026 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4109 reg = <0 0x17d91000 0 0x1000>,
4110 <0 0x17d92000 0 0x1000>,
4111 <0 0x17d93000 0 0x1000>;
4118 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4125 reg = <0 0x19100000 0 0xbb800>;
4132 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4133 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4134 <0 0x19a00000 0 0x80000>;
4143 reg = <0 0x01d84000 0 0x3000>;
4154 iommus = <&apps_smmu 0xe0 0x0>;
4157 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4158 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4180 <0 0>,
4181 <0 0>,
4184 <0 0>,
4185 <0 0>,
4186 <0 0>;
4194 reg = <0 0x01d87000 0 0x1c4>;
4205 resets = <&ufs_mem_hc 0>;
4210 reg = <0 0x01d87400 0 0x188>,
4211 <0 0x01d87600 0 0x200>,
4212 <0 0x01d87c00 0 0x200>,
4213 <0 0x01d87800 0 0x188>,
4214 <0 0x01d87a00 0 0x200>;
4216 #phy-cells = <0>;
4223 reg = <0 0x01d88000 0 0x8000>;
4229 reg = <0 0x01dc4000 0 0x28000>;
4232 qcom,ee = <0>;
4234 iommus = <&apps_smmu 0x584 0x11>,
4235 <&apps_smmu 0x588 0x0>,
4236 <&apps_smmu 0x598 0x5>,
4237 <&apps_smmu 0x59a 0x0>,
4238 <&apps_smmu 0x59f 0x0>;
4243 reg = <0 0x01dfa000 0 0x6000>;
4246 iommus = <&apps_smmu 0x584 0x11>,
4247 <&apps_smmu 0x588 0x0>,
4248 <&apps_smmu 0x598 0x5>,
4249 <&apps_smmu 0x59a 0x0>,
4250 <&apps_smmu 0x59f 0x0>;
4251 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4257 reg = <0 0x08804000 0 0x1000>;
4268 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4269 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4271 iommus = <&apps_smmu 0x4a0 0x0>;
4278 sdhci-caps-mask = <0x3 0x0>;
4299 reg = <0 0x0a6f8800 0 0x400>;
4335 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4336 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4341 reg = <0 0x0a600000 0 0xcd00>;
4343 iommus = <&apps_smmu 0x0 0x0>;
4351 #size-cells = <0>;
4353 port@0 {
4354 reg = <0>;
4372 reg = <0 0x320c0000 0 0x10000>;
4379 reg = <0 0x03c40000 0 0x17200>;
4390 polling-delay-passive = <0>;
4391 polling-delay = <0>;
4392 thermal-sensors = <&tsens0 0>;
4410 polling-delay-passive = <0>;
4411 polling-delay = <0>;
4430 polling-delay-passive = <0>;
4431 polling-delay = <0>;
4450 polling-delay-passive = <0>;
4451 polling-delay = <0>;
4470 polling-delay-passive = <0>;
4471 polling-delay = <0>;
4490 polling-delay-passive = <0>;
4491 polling-delay = <0>;
4516 polling-delay-passive = <0>;
4517 polling-delay = <0>;
4542 polling-delay-passive = <0>;
4543 polling-delay = <0>;
4568 polling-delay-passive = <0>;
4569 polling-delay = <0>;
4594 polling-delay-passive = <0>;
4595 polling-delay = <0>;
4620 polling-delay-passive = <0>;
4621 polling-delay = <0>;
4646 polling-delay-passive = <0>;
4647 polling-delay = <0>;
4672 polling-delay-passive = <0>;
4673 polling-delay = <0>;
4698 polling-delay-passive = <0>;
4699 polling-delay = <0>;
4725 polling-delay = <0>;
4757 polling-delay = <0>;
4788 polling-delay-passive = <0>;
4789 polling-delay = <0>;
4790 thermal-sensors = <&tsens1 0>;
4808 polling-delay-passive = <0>;
4809 polling-delay = <0>;
4834 polling-delay-passive = <0>;
4835 polling-delay = <0>;
4860 polling-delay-passive = <0>;
4861 polling-delay = <0>;
4886 polling-delay-passive = <0>;
4887 polling-delay = <0>;
4913 polling-delay = <0>;
4945 polling-delay = <0>;
4977 polling-delay = <0>;
5008 polling-delay-passive = <0>;
5009 polling-delay = <0>;
5029 polling-delay = <0>;
5054 polling-delay-passive = <0>;
5055 polling-delay = <0>;
5086 polling-delay-passive = <0>;
5087 polling-delay = <0>;
5118 polling-delay-passive = <0>;
5119 polling-delay = <0>;
5150 polling-delay-passive = <0>;
5151 polling-delay = <0>;
5182 polling-delay-passive = <0>;
5183 polling-delay = <0>;
5202 polling-delay-passive = <0>;
5203 polling-delay = <0>;