Lines Matching +full:gpucc +full:- +full:sm8350
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,sm8350.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
9 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,sm8350.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/interconnect/qcom,sm8350.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <38400000>;
38 clock-output-names = "xo_board";
41 sleep_clk: sleep-clk {
42 compatible = "fixed-clock";
43 clock-frequency = <32000>;
44 #clock-cells = <0>;
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a55";
57 enable-method = "psci";
58 next-level-cache = <&L2_0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
60 power-domains = <&CPU_PD0>;
61 power-domain-names = "psci";
62 #cooling-cells = <2>;
63 L2_0: l2-cache {
65 cache-level = <2>;
66 cache-unified;
67 next-level-cache = <&L3_0>;
68 L3_0: l3-cache {
70 cache-level = <3>;
71 cache-unified;
78 compatible = "arm,cortex-a55";
81 enable-method = "psci";
82 next-level-cache = <&L2_100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
84 power-domains = <&CPU_PD1>;
85 power-domain-names = "psci";
86 #cooling-cells = <2>;
87 L2_100: l2-cache {
89 cache-level = <2>;
90 cache-unified;
91 next-level-cache = <&L3_0>;
97 compatible = "arm,cortex-a55";
100 enable-method = "psci";
101 next-level-cache = <&L2_200>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 power-domains = <&CPU_PD2>;
104 power-domain-names = "psci";
105 #cooling-cells = <2>;
106 L2_200: l2-cache {
108 cache-level = <2>;
109 cache-unified;
110 next-level-cache = <&L3_0>;
116 compatible = "arm,cortex-a55";
119 enable-method = "psci";
120 next-level-cache = <&L2_300>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 power-domains = <&CPU_PD3>;
123 power-domain-names = "psci";
124 #cooling-cells = <2>;
125 L2_300: l2-cache {
127 cache-level = <2>;
128 cache-unified;
129 next-level-cache = <&L3_0>;
135 compatible = "arm,cortex-a78";
138 enable-method = "psci";
139 next-level-cache = <&L2_400>;
140 qcom,freq-domain = <&cpufreq_hw 1>;
141 power-domains = <&CPU_PD4>;
142 power-domain-names = "psci";
143 #cooling-cells = <2>;
144 L2_400: l2-cache {
146 cache-level = <2>;
147 cache-unified;
148 next-level-cache = <&L3_0>;
154 compatible = "arm,cortex-a78";
157 enable-method = "psci";
158 next-level-cache = <&L2_500>;
159 qcom,freq-domain = <&cpufreq_hw 1>;
160 power-domains = <&CPU_PD5>;
161 power-domain-names = "psci";
162 #cooling-cells = <2>;
163 L2_500: l2-cache {
165 cache-level = <2>;
166 cache-unified;
167 next-level-cache = <&L3_0>;
173 compatible = "arm,cortex-a78";
176 enable-method = "psci";
177 next-level-cache = <&L2_600>;
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 power-domains = <&CPU_PD6>;
180 power-domain-names = "psci";
181 #cooling-cells = <2>;
182 L2_600: l2-cache {
184 cache-level = <2>;
185 cache-unified;
186 next-level-cache = <&L3_0>;
192 compatible = "arm,cortex-x1";
195 enable-method = "psci";
196 next-level-cache = <&L2_700>;
197 qcom,freq-domain = <&cpufreq_hw 2>;
198 power-domains = <&CPU_PD7>;
199 power-domain-names = "psci";
200 #cooling-cells = <2>;
201 L2_700: l2-cache {
203 cache-level = <2>;
204 cache-unified;
205 next-level-cache = <&L3_0>;
209 cpu-map {
245 idle-states {
246 entry-method = "psci";
248 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
249 compatible = "arm,idle-state";
250 idle-state-name = "silver-rail-power-collapse";
251 arm,psci-suspend-param = <0x40000004>;
252 entry-latency-us = <360>;
253 exit-latency-us = <531>;
254 min-residency-us = <3934>;
255 local-timer-stop;
258 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
259 compatible = "arm,idle-state";
260 idle-state-name = "gold-rail-power-collapse";
261 arm,psci-suspend-param = <0x40000004>;
262 entry-latency-us = <702>;
263 exit-latency-us = <1061>;
264 min-residency-us = <4488>;
265 local-timer-stop;
269 domain-idle-states {
270 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
271 compatible = "domain-idle-state";
272 arm,psci-suspend-param = <0x41000044>;
273 entry-latency-us = <2752>;
274 exit-latency-us = <3048>;
275 min-residency-us = <6118>;
278 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
279 compatible = "domain-idle-state";
280 arm,psci-suspend-param = <0x4100c344>;
281 entry-latency-us = <3263>;
282 exit-latency-us = <6562>;
283 min-residency-us = <9987>;
290 compatible = "qcom,scm-sm8350", "qcom,scm";
291 #reset-cells = <1>;
302 compatible = "arm,armv8-pmuv3";
307 compatible = "arm,psci-1.0";
310 CPU_PD0: power-domain-cpu0 {
311 #power-domain-cells = <0>;
312 power-domains = <&CLUSTER_PD>;
313 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
316 CPU_PD1: power-domain-cpu1 {
317 #power-domain-cells = <0>;
318 power-domains = <&CLUSTER_PD>;
319 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
322 CPU_PD2: power-domain-cpu2 {
323 #power-domain-cells = <0>;
324 power-domains = <&CLUSTER_PD>;
325 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
328 CPU_PD3: power-domain-cpu3 {
329 #power-domain-cells = <0>;
330 power-domains = <&CLUSTER_PD>;
331 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
334 CPU_PD4: power-domain-cpu4 {
335 #power-domain-cells = <0>;
336 power-domains = <&CLUSTER_PD>;
337 domain-idle-states = <&BIG_CPU_SLEEP_0>;
340 CPU_PD5: power-domain-cpu5 {
341 #power-domain-cells = <0>;
342 power-domains = <&CLUSTER_PD>;
343 domain-idle-states = <&BIG_CPU_SLEEP_0>;
346 CPU_PD6: power-domain-cpu6 {
347 #power-domain-cells = <0>;
348 power-domains = <&CLUSTER_PD>;
349 domain-idle-states = <&BIG_CPU_SLEEP_0>;
352 CPU_PD7: power-domain-cpu7 {
353 #power-domain-cells = <0>;
354 power-domains = <&CLUSTER_PD>;
355 domain-idle-states = <&BIG_CPU_SLEEP_0>;
358 CLUSTER_PD: power-domain-cpu-cluster0 {
359 #power-domain-cells = <0>;
360 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
364 qup_opp_table_100mhz: opp-table-qup100mhz {
365 compatible = "operating-points-v2";
367 opp-50000000 {
368 opp-hz = /bits/ 64 <50000000>;
369 required-opps = <&rpmhpd_opp_min_svs>;
372 opp-75000000 {
373 opp-hz = /bits/ 64 <75000000>;
374 required-opps = <&rpmhpd_opp_low_svs>;
377 opp-100000000 {
378 opp-hz = /bits/ 64 <100000000>;
379 required-opps = <&rpmhpd_opp_svs>;
383 qup_opp_table_120mhz: opp-table-qup120mhz {
384 compatible = "operating-points-v2";
386 opp-50000000 {
387 opp-hz = /bits/ 64 <50000000>;
388 required-opps = <&rpmhpd_opp_min_svs>;
391 opp-75000000 {
392 opp-hz = /bits/ 64 <75000000>;
393 required-opps = <&rpmhpd_opp_low_svs>;
396 opp-120000000 {
397 opp-hz = /bits/ 64 <120000000>;
398 required-opps = <&rpmhpd_opp_svs>;
402 reserved_memory: reserved-memory {
403 #address-cells = <2>;
404 #size-cells = <2>;
409 no-map;
413 no-map;
418 compatible = "qcom,cmd-db";
420 no-map;
425 no-map;
432 no-map;
437 no-map;
442 no-map;
447 no-map;
452 no-map;
457 no-map;
462 no-map;
467 no-map;
472 no-map;
477 no-map;
482 no-map;
487 no-map;
492 no-map;
497 no-map;
501 compatible = "qcom,rmtfs-mem";
503 no-map;
505 qcom,client-id = <1>;
511 no-map;
516 no-map;
521 no-map;
526 no-map;
531 no-map;
536 no-map;
540 smp2p-adsp {
543 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
549 qcom,local-pid = <0>;
550 qcom,remote-pid = <2>;
552 smp2p_adsp_out: master-kernel {
553 qcom,entry-name = "master-kernel";
554 #qcom,smem-state-cells = <1>;
557 smp2p_adsp_in: slave-kernel {
558 qcom,entry-name = "slave-kernel";
559 interrupt-controller;
560 #interrupt-cells = <2>;
564 smp2p-cdsp {
567 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
573 qcom,local-pid = <0>;
574 qcom,remote-pid = <5>;
576 smp2p_cdsp_out: master-kernel {
577 qcom,entry-name = "master-kernel";
578 #qcom,smem-state-cells = <1>;
581 smp2p_cdsp_in: slave-kernel {
582 qcom,entry-name = "slave-kernel";
583 interrupt-controller;
584 #interrupt-cells = <2>;
588 smp2p-modem {
591 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
597 qcom,local-pid = <0>;
598 qcom,remote-pid = <1>;
600 smp2p_modem_out: master-kernel {
601 qcom,entry-name = "master-kernel";
602 #qcom,smem-state-cells = <1>;
605 smp2p_modem_in: slave-kernel {
606 qcom,entry-name = "slave-kernel";
607 interrupt-controller;
608 #interrupt-cells = <2>;
611 ipa_smp2p_out: ipa-ap-to-modem {
612 qcom,entry-name = "ipa";
613 #qcom,smem-state-cells = <1>;
616 ipa_smp2p_in: ipa-modem-to-ap {
617 qcom,entry-name = "ipa";
618 interrupt-controller;
619 #interrupt-cells = <2>;
623 smp2p-slpi {
626 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
632 qcom,local-pid = <0>;
633 qcom,remote-pid = <3>;
635 smp2p_slpi_out: master-kernel {
636 qcom,entry-name = "master-kernel";
637 #qcom,smem-state-cells = <1>;
640 smp2p_slpi_in: slave-kernel {
641 qcom,entry-name = "slave-kernel";
642 interrupt-controller;
643 #interrupt-cells = <2>;
648 #address-cells = <2>;
649 #size-cells = <2>;
651 dma-ranges = <0 0 0 0 0x10 0>;
652 compatible = "simple-bus";
654 gcc: clock-controller@100000 {
655 compatible = "qcom,gcc-sm8350";
657 #clock-cells = <1>;
658 #reset-cells = <1>;
659 #power-domain-cells = <1>;
660 clock-names = "bi_tcxo",
687 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
690 interrupt-controller;
691 #interrupt-cells = <3>;
692 #mbox-cells = <2>;
695 gpi_dma2: dma-controller@800000 {
696 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
710 dma-channels = <12>;
711 dma-channel-mask = <0xff>;
713 #dma-cells = <3>;
718 compatible = "qcom,geni-se-qup";
720 clock-names = "m-ahb", "s-ahb";
724 #address-cells = <2>;
725 #size-cells = <2>;
730 compatible = "qcom,geni-i2c";
732 clock-names = "se";
734 pinctrl-names = "default";
735 pinctrl-0 = <&qup_i2c14_default>;
739 dma-names = "tx", "rx";
740 #address-cells = <1>;
741 #size-cells = <0>;
746 compatible = "qcom,geni-spi";
748 clock-names = "se";
751 power-domains = <&rpmhpd RPMHPD_CX>;
752 operating-points-v2 = <&qup_opp_table_120mhz>;
755 dma-names = "tx", "rx";
756 #address-cells = <1>;
757 #size-cells = <0>;
762 compatible = "qcom,geni-i2c";
764 clock-names = "se";
766 pinctrl-names = "default";
767 pinctrl-0 = <&qup_i2c15_default>;
771 dma-names = "tx", "rx";
772 #address-cells = <1>;
773 #size-cells = <0>;
778 compatible = "qcom,geni-spi";
780 clock-names = "se";
783 power-domains = <&rpmhpd RPMHPD_CX>;
784 operating-points-v2 = <&qup_opp_table_120mhz>;
787 dma-names = "tx", "rx";
788 #address-cells = <1>;
789 #size-cells = <0>;
794 compatible = "qcom,geni-i2c";
796 clock-names = "se";
798 pinctrl-names = "default";
799 pinctrl-0 = <&qup_i2c16_default>;
803 dma-names = "tx", "rx";
804 #address-cells = <1>;
805 #size-cells = <0>;
810 compatible = "qcom,geni-spi";
812 clock-names = "se";
815 power-domains = <&rpmhpd RPMHPD_CX>;
816 operating-points-v2 = <&qup_opp_table_100mhz>;
819 dma-names = "tx", "rx";
820 #address-cells = <1>;
821 #size-cells = <0>;
826 compatible = "qcom,geni-i2c";
828 clock-names = "se";
830 pinctrl-names = "default";
831 pinctrl-0 = <&qup_i2c17_default>;
835 dma-names = "tx", "rx";
836 #address-cells = <1>;
837 #size-cells = <0>;
842 compatible = "qcom,geni-spi";
844 clock-names = "se";
847 power-domains = <&rpmhpd RPMHPD_CX>;
848 operating-points-v2 = <&qup_opp_table_100mhz>;
851 dma-names = "tx", "rx";
852 #address-cells = <1>;
853 #size-cells = <0>;
857 /* QUP no. 18 seems to be strictly SPI/UART-only */
860 compatible = "qcom,geni-spi";
862 clock-names = "se";
865 power-domains = <&rpmhpd RPMHPD_CX>;
866 operating-points-v2 = <&qup_opp_table_100mhz>;
869 dma-names = "tx", "rx";
870 #address-cells = <1>;
871 #size-cells = <0>;
876 compatible = "qcom,geni-uart";
878 clock-names = "se";
880 pinctrl-names = "default";
881 pinctrl-0 = <&qup_uart18_default>;
883 power-domains = <&rpmhpd RPMHPD_CX>;
884 operating-points-v2 = <&qup_opp_table_100mhz>;
889 compatible = "qcom,geni-i2c";
891 clock-names = "se";
893 pinctrl-names = "default";
894 pinctrl-0 = <&qup_i2c19_default>;
898 dma-names = "tx", "rx";
899 #address-cells = <1>;
900 #size-cells = <0>;
905 compatible = "qcom,geni-spi";
907 clock-names = "se";
910 power-domains = <&rpmhpd RPMHPD_CX>;
911 operating-points-v2 = <&qup_opp_table_100mhz>;
914 dma-names = "tx", "rx";
915 #address-cells = <1>;
916 #size-cells = <0>;
921 gpi_dma0: dma-controller@900000 {
922 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
936 dma-channels = <12>;
937 dma-channel-mask = <0x7e>;
939 #dma-cells = <3>;
944 compatible = "qcom,geni-se-qup";
946 clock-names = "m-ahb", "s-ahb";
950 #address-cells = <2>;
951 #size-cells = <2>;
956 compatible = "qcom,geni-i2c";
958 clock-names = "se";
960 pinctrl-names = "default";
961 pinctrl-0 = <&qup_i2c0_default>;
965 dma-names = "tx", "rx";
966 #address-cells = <1>;
967 #size-cells = <0>;
972 compatible = "qcom,geni-spi";
974 clock-names = "se";
977 power-domains = <&rpmhpd RPMHPD_CX>;
978 operating-points-v2 = <&qup_opp_table_100mhz>;
981 dma-names = "tx", "rx";
982 #address-cells = <1>;
983 #size-cells = <0>;
988 compatible = "qcom,geni-i2c";
990 clock-names = "se";
992 pinctrl-names = "default";
993 pinctrl-0 = <&qup_i2c1_default>;
997 dma-names = "tx", "rx";
998 #address-cells = <1>;
999 #size-cells = <0>;
1004 compatible = "qcom,geni-spi";
1006 clock-names = "se";
1009 power-domains = <&rpmhpd RPMHPD_CX>;
1010 operating-points-v2 = <&qup_opp_table_100mhz>;
1013 dma-names = "tx", "rx";
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1020 compatible = "qcom,geni-i2c";
1022 clock-names = "se";
1024 pinctrl-names = "default";
1025 pinctrl-0 = <&qup_i2c2_default>;
1029 dma-names = "tx", "rx";
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1036 compatible = "qcom,geni-spi";
1038 clock-names = "se";
1041 power-domains = <&rpmhpd RPMHPD_CX>;
1042 operating-points-v2 = <&qup_opp_table_100mhz>;
1045 dma-names = "tx", "rx";
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1052 compatible = "qcom,geni-debug-uart";
1054 clock-names = "se";
1056 pinctrl-names = "default";
1057 pinctrl-0 = <&qup_uart3_default_state>;
1059 power-domains = <&rpmhpd RPMHPD_CX>;
1060 operating-points-v2 = <&qup_opp_table_100mhz>;
1064 /* QUP no. 3 seems to be strictly SPI-only */
1067 compatible = "qcom,geni-spi";
1069 clock-names = "se";
1072 power-domains = <&rpmhpd RPMHPD_CX>;
1073 operating-points-v2 = <&qup_opp_table_100mhz>;
1076 dma-names = "tx", "rx";
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1083 compatible = "qcom,geni-i2c";
1085 clock-names = "se";
1087 pinctrl-names = "default";
1088 pinctrl-0 = <&qup_i2c4_default>;
1092 dma-names = "tx", "rx";
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1099 compatible = "qcom,geni-spi";
1101 clock-names = "se";
1104 power-domains = <&rpmhpd RPMHPD_CX>;
1105 operating-points-v2 = <&qup_opp_table_100mhz>;
1108 dma-names = "tx", "rx";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1115 compatible = "qcom,geni-i2c";
1117 clock-names = "se";
1119 pinctrl-names = "default";
1120 pinctrl-0 = <&qup_i2c5_default>;
1124 dma-names = "tx", "rx";
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1131 compatible = "qcom,geni-spi";
1133 clock-names = "se";
1136 power-domains = <&rpmhpd RPMHPD_CX>;
1137 operating-points-v2 = <&qup_opp_table_100mhz>;
1140 dma-names = "tx", "rx";
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1147 compatible = "qcom,geni-i2c";
1149 clock-names = "se";
1151 pinctrl-names = "default";
1152 pinctrl-0 = <&qup_i2c6_default>;
1156 dma-names = "tx", "rx";
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1163 compatible = "qcom,geni-spi";
1165 clock-names = "se";
1168 power-domains = <&rpmhpd RPMHPD_CX>;
1169 operating-points-v2 = <&qup_opp_table_100mhz>;
1172 dma-names = "tx", "rx";
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1179 compatible = "qcom,geni-uart";
1181 clock-names = "se";
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&qup_uart6_default>;
1186 power-domains = <&rpmhpd RPMHPD_CX>;
1187 operating-points-v2 = <&qup_opp_table_100mhz>;
1192 compatible = "qcom,geni-i2c";
1194 clock-names = "se";
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&qup_i2c7_default>;
1201 dma-names = "tx", "rx";
1202 #address-cells = <1>;
1203 #size-cells = <0>;
1208 compatible = "qcom,geni-spi";
1210 clock-names = "se";
1213 power-domains = <&rpmhpd RPMHPD_CX>;
1214 operating-points-v2 = <&qup_opp_table_100mhz>;
1217 dma-names = "tx", "rx";
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1224 gpi_dma1: dma-controller@a00000 {
1225 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
1239 dma-channels = <12>;
1240 dma-channel-mask = <0xff>;
1242 #dma-cells = <3>;
1247 compatible = "qcom,geni-se-qup";
1249 clock-names = "m-ahb", "s-ahb";
1253 #address-cells = <2>;
1254 #size-cells = <2>;
1259 compatible = "qcom,geni-i2c";
1261 clock-names = "se";
1263 pinctrl-names = "default";
1264 pinctrl-0 = <&qup_i2c8_default>;
1268 dma-names = "tx", "rx";
1269 #address-cells = <1>;
1270 #size-cells = <0>;
1275 compatible = "qcom,geni-spi";
1277 clock-names = "se";
1280 power-domains = <&rpmhpd RPMHPD_CX>;
1281 operating-points-v2 = <&qup_opp_table_120mhz>;
1284 dma-names = "tx", "rx";
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1291 compatible = "qcom,geni-i2c";
1293 clock-names = "se";
1295 pinctrl-names = "default";
1296 pinctrl-0 = <&qup_i2c9_default>;
1300 dma-names = "tx", "rx";
1301 #address-cells = <1>;
1302 #size-cells = <0>;
1307 compatible = "qcom,geni-spi";
1309 clock-names = "se";
1312 power-domains = <&rpmhpd RPMHPD_CX>;
1313 operating-points-v2 = <&qup_opp_table_100mhz>;
1316 dma-names = "tx", "rx";
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1323 compatible = "qcom,geni-i2c";
1325 clock-names = "se";
1327 pinctrl-names = "default";
1328 pinctrl-0 = <&qup_i2c10_default>;
1332 dma-names = "tx", "rx";
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1339 compatible = "qcom,geni-spi";
1341 clock-names = "se";
1344 power-domains = <&rpmhpd RPMHPD_CX>;
1345 operating-points-v2 = <&qup_opp_table_100mhz>;
1348 dma-names = "tx", "rx";
1349 #address-cells = <1>;
1350 #size-cells = <0>;
1355 compatible = "qcom,geni-i2c";
1357 clock-names = "se";
1359 pinctrl-names = "default";
1360 pinctrl-0 = <&qup_i2c11_default>;
1364 dma-names = "tx", "rx";
1365 #address-cells = <1>;
1366 #size-cells = <0>;
1371 compatible = "qcom,geni-spi";
1373 clock-names = "se";
1376 power-domains = <&rpmhpd RPMHPD_CX>;
1377 operating-points-v2 = <&qup_opp_table_100mhz>;
1380 dma-names = "tx", "rx";
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1387 compatible = "qcom,geni-i2c";
1389 clock-names = "se";
1391 pinctrl-names = "default";
1392 pinctrl-0 = <&qup_i2c12_default>;
1396 dma-names = "tx", "rx";
1397 #address-cells = <1>;
1398 #size-cells = <0>;
1403 compatible = "qcom,geni-spi";
1405 clock-names = "se";
1408 power-domains = <&rpmhpd RPMHPD_CX>;
1409 operating-points-v2 = <&qup_opp_table_100mhz>;
1412 dma-names = "tx", "rx";
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1419 compatible = "qcom,geni-i2c";
1421 clock-names = "se";
1423 pinctrl-names = "default";
1424 pinctrl-0 = <&qup_i2c13_default>;
1428 dma-names = "tx", "rx";
1429 #address-cells = <1>;
1430 #size-cells = <0>;
1435 compatible = "qcom,geni-spi";
1437 clock-names = "se";
1440 power-domains = <&rpmhpd RPMHPD_CX>;
1441 operating-points-v2 = <&qup_opp_table_100mhz>;
1444 dma-names = "tx", "rx";
1445 #address-cells = <1>;
1446 #size-cells = <0>;
1452 compatible = "qcom,prng-ee";
1455 clock-names = "core";
1459 compatible = "qcom,sm8350-config-noc";
1461 #interconnect-cells = <2>;
1462 qcom,bcm-voters = <&apps_bcm_voter>;
1466 compatible = "qcom,sm8350-mc-virt";
1468 #interconnect-cells = <2>;
1469 qcom,bcm-voters = <&apps_bcm_voter>;
1473 compatible = "qcom,sm8350-system-noc";
1475 #interconnect-cells = <2>;
1476 qcom,bcm-voters = <&apps_bcm_voter>;
1480 compatible = "qcom,sm8350-aggre1-noc";
1482 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&apps_bcm_voter>;
1487 compatible = "qcom,sm8350-aggre2-noc";
1489 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&apps_bcm_voter>;
1494 compatible = "qcom,sm8350-mmss-noc";
1496 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&apps_bcm_voter>;
1501 compatible = "qcom,pcie-sm8350";
1507 reg-names = "parf", "dbi", "elbi", "atu", "config";
1509 linux,pci-domain = <0>;
1510 bus-range = <0x00 0xff>;
1511 num-lanes = <1>;
1513 #address-cells = <3>;
1514 #size-cells = <2>;
1527 interrupt-names = "msi0", "msi1", "msi2", "msi3",
1529 #interrupt-cells = <1>;
1530 interrupt-map-mask = <0 0 0 0x7>;
1531 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1545 clock-names = "aux",
1555 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1559 reset-names = "pci";
1561 power-domains = <&gcc PCIE_0_GDSC>;
1564 phy-names = "pciephy";
1570 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1577 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1580 reset-names = "phy";
1582 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1583 assigned-clock-rates = <100000000>;
1585 #clock-cells = <0>;
1586 clock-output-names = "pcie_0_pipe_clk";
1588 #phy-cells = <0>;
1594 compatible = "qcom,pcie-sm8350";
1600 reg-names = "parf", "dbi", "elbi", "atu", "config";
1602 linux,pci-domain = <1>;
1603 bus-range = <0x00 0xff>;
1604 num-lanes = <2>;
1606 #address-cells = <3>;
1607 #size-cells = <2>;
1613 interrupt-names = "msi";
1614 #interrupt-cells = <1>;
1615 interrupt-map-mask = <0 0 0 0x7>;
1616 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1629 clock-names = "aux",
1638 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1642 reset-names = "pci";
1644 power-domains = <&gcc PCIE_1_GDSC>;
1647 phy-names = "pciephy";
1653 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1660 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1663 reset-names = "phy";
1665 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1666 assigned-clock-rates = <100000000>;
1668 #clock-cells = <0>;
1669 clock-output-names = "pcie_1_pipe_clk";
1671 #phy-cells = <0>;
1677 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1678 "jedec,ufs-2.0";
1682 phy-names = "ufsphy";
1683 lanes-per-direction = <2>;
1684 #reset-cells = <1>;
1686 reset-names = "rst";
1688 power-domains = <&gcc UFS_PHY_GDSC>;
1691 dma-coherent;
1693 clock-names =
1711 freq-table-hz =
1724 compatible = "qcom,sm8350-qmp-ufs-phy";
1726 #address-cells = <2>;
1727 #size-cells = <2>;
1729 clock-names = "ref",
1734 power-domains = <&gcc UFS_PHY_GDSC>;
1737 reset-names = "ufsphy";
1746 #clock-cells = <1>;
1747 #phy-cells = <0>;
1751 cryptobam: dma-controller@1dc4000 {
1752 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1755 #dma-cells = <1>;
1757 qcom,controlled-remotely;
1765 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce";
1768 dma-names = "rx", "tx";
1772 interconnect-names = "memory";
1778 compatible = "qcom,sm8350-ipa";
1785 reg-names = "ipa-reg",
1786 "ipa-shared",
1789 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1793 interrupt-names = "ipa",
1795 "ipa-clock-query",
1796 "ipa-setup-ready";
1799 clock-names = "core";
1803 interconnect-names = "memory",
1808 qcom,smem-states = <&ipa_smp2p_out 0>,
1810 qcom,smem-state-names = "ipa-clock-enabled-valid",
1811 "ipa-clock-enabled";
1817 compatible = "qcom,tcsr-mutex";
1819 #hwlock-cells = <1>;
1823 compatible = "qcom,sm8350-lpass-lpi-pinctrl";
1829 clock-names = "core", "audio";
1831 gpio-controller;
1832 #gpio-cells = <2>;
1833 gpio-ranges = <&lpass_tlmm 0 0 15>;
1837 compatible = "qcom,adreno-660.1", "qcom,adreno";
1842 reg-names = "kgsl_3d0_reg_memory",
1850 operating-points-v2 = <&gpu_opp_table>;
1856 zap-shader {
1857 memory-region = <&pil_gpu_mem>;
1861 gpu_opp_table: opp-table {
1862 compatible = "operating-points-v2";
1864 opp-840000000 {
1865 opp-hz = /bits/ 64 <840000000>;
1866 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1869 opp-778000000 {
1870 opp-hz = /bits/ 64 <778000000>;
1871 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1874 opp-738000000 {
1875 opp-hz = /bits/ 64 <738000000>;
1876 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1879 opp-676000000 {
1880 opp-hz = /bits/ 64 <676000000>;
1881 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1884 opp-608000000 {
1885 opp-hz = /bits/ 64 <608000000>;
1886 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1889 opp-540000000 {
1890 opp-hz = /bits/ 64 <540000000>;
1891 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1894 opp-491000000 {
1895 opp-hz = /bits/ 64 <491000000>;
1896 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1899 opp-443000000 {
1900 opp-hz = /bits/ 64 <443000000>;
1901 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1904 opp-379000000 {
1905 opp-hz = /bits/ 64 <379000000>;
1906 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
1909 opp-315000000 {
1910 opp-hz = /bits/ 64 <315000000>;
1911 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1917 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1922 reg-names = "gmu", "rscc", "gmu_pdc";
1926 interrupt-names = "hfi", "gmu";
1928 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
1929 <&gpucc GPU_CC_CXO_CLK>,
1932 <&gpucc GPU_CC_AHB_CLK>,
1933 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1934 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
1935 clock-names = "gmu",
1943 power-domains = <&gpucc GPU_CX_GDSC>,
1944 <&gpucc GPU_GX_GDSC>;
1945 power-domain-names = "cx",
1950 operating-points-v2 = <&gmu_opp_table>;
1952 gmu_opp_table: opp-table {
1953 compatible = "operating-points-v2";
1955 opp-200000000 {
1956 opp-hz = /bits/ 64 <200000000>;
1957 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1962 gpucc: clock-controller@3d90000 { label
1963 compatible = "qcom,sm8350-gpucc";
1968 clock-names = "bi_tcxo",
1971 #clock-cells = <1>;
1972 #reset-cells = <1>;
1973 #power-domain-cells = <1>;
1977 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
1978 "qcom,smmu-500", "arm,mmu-500";
1980 #iommu-cells = <2>;
1981 #global-interrupts = <2>;
1997 <&gpucc GPU_CC_AHB_CLK>,
1998 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1999 <&gpucc GPU_CC_CX_GMU_CLK>,
2000 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2001 <&gpucc GPU_CC_HUB_AON_CLK>;
2002 clock-names = "bus",
2010 power-domains = <&gpucc GPU_CX_GDSC>;
2011 dma-coherent;
2015 compatible = "qcom,sm8350-lpass-ag-noc";
2017 #interconnect-cells = <2>;
2018 qcom,bcm-voters = <&apps_bcm_voter>;
2022 compatible = "qcom,sm8350-mpss-pas";
2025 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2031 interrupt-names = "wdog", "fatal", "ready", "handover",
2032 "stop-ack", "shutdown-ack";
2035 clock-names = "xo";
2037 power-domains = <&rpmhpd RPMHPD_CX>,
2039 power-domain-names = "cx", "mss";
2043 memory-region = <&pil_modem_mem>;
2047 qcom,smem-states = <&smp2p_modem_out 0>;
2048 qcom,smem-state-names = "stop";
2052 glink-edge {
2053 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2059 qcom,remote-pid = <1>;
2064 compatible = "qcom,sm8350-slpi-pas";
2067 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2072 interrupt-names = "wdog", "fatal", "ready",
2073 "handover", "stop-ack";
2076 clock-names = "xo";
2078 power-domains = <&rpmhpd RPMHPD_LCX>,
2080 power-domain-names = "lcx", "lmx";
2082 memory-region = <&pil_slpi_mem>;
2086 qcom,smem-states = <&smp2p_slpi_out 0>;
2087 qcom,smem-state-names = "stop";
2091 glink-edge {
2092 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2099 qcom,remote-pid = <3>;
2103 qcom,glink-channels = "fastrpcglink-apps-dsp";
2105 qcom,non-secure-domain;
2106 #address-cells = <1>;
2107 #size-cells = <0>;
2109 compute-cb@1 {
2110 compatible = "qcom,fastrpc-compute-cb";
2115 compute-cb@2 {
2116 compatible = "qcom,fastrpc-compute-cb";
2121 compute-cb@3 {
2122 compatible = "qcom,fastrpc-compute-cb";
2125 /* note: shared-cb = <4> in downstream */
2132 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2137 interrupt-names = "hc_irq", "pwr_irq";
2142 clock-names = "iface", "core", "xo";
2146 interconnect-names = "sdhc-ddr","cpu-sdhc";
2148 power-domains = <&rpmhpd RPMHPD_CX>;
2149 operating-points-v2 = <&sdhc2_opp_table>;
2150 bus-width = <4>;
2151 dma-coherent;
2155 sdhc2_opp_table: opp-table {
2156 compatible = "operating-points-v2";
2158 opp-100000000 {
2159 opp-hz = /bits/ 64 <100000000>;
2160 required-opps = <&rpmhpd_opp_low_svs>;
2163 opp-202000000 {
2164 opp-hz = /bits/ 64 <202000000>;
2165 required-opps = <&rpmhpd_opp_svs_l1>;
2171 compatible = "qcom,sm8350-usb-hs-phy",
2172 "qcom,usb-snps-hs-7nm-phy";
2175 #phy-cells = <0>;
2178 clock-names = "ref";
2184 compatible = "qcom,sm8250-usb-hs-phy",
2185 "qcom,usb-snps-hs-7nm-phy";
2188 #phy-cells = <0>;
2191 clock-names = "ref";
2197 compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2204 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2208 reset-names = "phy", "common";
2210 #clock-cells = <1>;
2211 #phy-cells = <1>;
2216 #address-cells = <1>;
2217 #size-cells = <0>;
2242 usb_2_qmpphy: phy-wrapper@88eb000 {
2243 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2246 #address-cells = <2>;
2247 #size-cells = <2>;
2254 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2258 reset-names = "phy", "common";
2264 #phy-cells = <0>;
2265 #clock-cells = <0>;
2267 clock-names = "pipe0";
2268 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2273 compatible = "qcom,sm8350-dc-noc";
2275 #interconnect-cells = <2>;
2276 qcom,bcm-voters = <&apps_bcm_voter>;
2280 compatible = "qcom,sm8350-gem-noc";
2282 #interconnect-cells = <2>;
2283 qcom,bcm-voters = <&apps_bcm_voter>;
2286 system-cache-controller@9200000 {
2287 compatible = "qcom,sm8350-llcc";
2291 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2296 compatible = "qcom,sm8350-compute-noc";
2298 #interconnect-cells = <2>;
2299 qcom,bcm-voters = <&apps_bcm_voter>;
2303 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2306 #address-cells = <2>;
2307 #size-cells = <2>;
2315 clock-names = "cfg_noc",
2321 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2323 assigned-clock-rates = <19200000>, <200000000>;
2325 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2329 interrupt-names = "hs_phy_irq",
2334 power-domains = <&gcc USB30_PRIM_GDSC>;
2340 interconnect-names = "usb-ddr", "apps-usb";
2350 phy-names = "usb2-phy", "usb3-phy";
2353 #address-cells = <1>;
2354 #size-cells = <0>;
2374 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2377 #address-cells = <2>;
2378 #size-cells = <2>;
2387 clock-names = "cfg_noc",
2394 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2396 assigned-clock-rates = <19200000>, <200000000>;
2398 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2402 interrupt-names = "hs_phy_irq",
2407 power-domains = <&gcc USB30_SEC_GDSC>;
2413 interconnect-names = "usb-ddr", "apps-usb";
2423 phy-names = "usb2-phy", "usb3-phy";
2427 mdss: display-subsystem@ae00000 {
2428 compatible = "qcom,sm8350-mdss";
2430 reg-names = "mdss";
2434 interconnect-names = "mdp0-mem", "mdp1-mem";
2436 power-domains = <&dispcc MDSS_GDSC>;
2443 clock-names = "iface", "bus", "nrt_bus", "core";
2446 interrupt-controller;
2447 #interrupt-cells = <1>;
2453 #address-cells = <2>;
2454 #size-cells = <2>;
2457 dpu_opp_table: opp-table {
2458 compatible = "operating-points-v2";
2460 /* TODO: opp-200000000 should work with
2465 opp-200000000 {
2466 opp-hz = /bits/ 64 <200000000>;
2467 required-opps = <&rpmhpd_opp_svs>;
2470 opp-300000000 {
2471 opp-hz = /bits/ 64 <300000000>;
2472 required-opps = <&rpmhpd_opp_svs>;
2475 opp-345000000 {
2476 opp-hz = /bits/ 64 <345000000>;
2477 required-opps = <&rpmhpd_opp_svs_l1>;
2480 opp-460000000 {
2481 opp-hz = /bits/ 64 <460000000>;
2482 required-opps = <&rpmhpd_opp_nom>;
2486 mdss_mdp: display-controller@ae01000 {
2487 compatible = "qcom,sm8350-dpu";
2490 reg-names = "mdp", "vbif";
2498 clock-names = "bus",
2505 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2506 assigned-clock-rates = <19200000>;
2508 operating-points-v2 = <&dpu_opp_table>;
2509 power-domains = <&rpmhpd RPMHPD_MMCX>;
2511 interrupt-parent = <&mdss>;
2515 #address-cells = <1>;
2516 #size-cells = <0>;
2521 remote-endpoint = <&mdss_dsi0_in>;
2528 remote-endpoint = <&mdss_dsi1_in>;
2535 remote-endpoint = <&mdss_dp_in>;
2541 mdss_dp: displayport-controller@ae90000 {
2542 compatible = "qcom,sm8350-dp";
2548 interrupt-parent = <&mdss>;
2555 clock-names = "core_iface",
2561 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2563 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2567 phy-names = "dp";
2569 #sound-dai-cells = <0>;
2571 operating-points-v2 = <&dp_opp_table>;
2572 power-domains = <&rpmhpd RPMHPD_MMCX>;
2577 #address-cells = <1>;
2578 #size-cells = <0>;
2583 remote-endpoint = <&dpu_intf0_out>;
2588 dp_opp_table: opp-table {
2589 compatible = "operating-points-v2";
2591 opp-160000000 {
2592 opp-hz = /bits/ 64 <160000000>;
2593 required-opps = <&rpmhpd_opp_low_svs>;
2596 opp-270000000 {
2597 opp-hz = /bits/ 64 <270000000>;
2598 required-opps = <&rpmhpd_opp_svs>;
2601 opp-540000000 {
2602 opp-hz = /bits/ 64 <540000000>;
2603 required-opps = <&rpmhpd_opp_svs_l1>;
2606 opp-810000000 {
2607 opp-hz = /bits/ 64 <810000000>;
2608 required-opps = <&rpmhpd_opp_nom>;
2614 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2616 reg-names = "dsi_ctrl";
2618 interrupt-parent = <&mdss>;
2627 clock-names = "byte",
2634 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2636 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2639 operating-points-v2 = <&dsi0_opp_table>;
2640 power-domains = <&rpmhpd RPMHPD_MMCX>;
2644 #address-cells = <1>;
2645 #size-cells = <0>;
2649 dsi0_opp_table: opp-table {
2650 compatible = "operating-points-v2";
2652 /* TODO: opp-187500000 should work with
2657 opp-187500000 {
2658 opp-hz = /bits/ 64 <187500000>;
2659 required-opps = <&rpmhpd_opp_svs>;
2662 opp-300000000 {
2663 opp-hz = /bits/ 64 <300000000>;
2664 required-opps = <&rpmhpd_opp_svs>;
2667 opp-358000000 {
2668 opp-hz = /bits/ 64 <358000000>;
2669 required-opps = <&rpmhpd_opp_svs_l1>;
2674 #address-cells = <1>;
2675 #size-cells = <0>;
2680 remote-endpoint = <&dpu_intf1_out>;
2693 compatible = "qcom,sm8350-dsi-phy-5nm";
2697 reg-names = "dsi_phy",
2701 #clock-cells = <1>;
2702 #phy-cells = <0>;
2706 clock-names = "iface", "ref";
2712 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2714 reg-names = "dsi_ctrl";
2716 interrupt-parent = <&mdss>;
2725 clock-names = "byte",
2732 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2734 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2737 operating-points-v2 = <&dsi1_opp_table>;
2738 power-domains = <&rpmhpd RPMHPD_MMCX>;
2742 #address-cells = <1>;
2743 #size-cells = <0>;
2747 dsi1_opp_table: opp-table {
2748 compatible = "operating-points-v2";
2750 /* TODO: opp-187500000 should work with
2755 opp-187500000 {
2756 opp-hz = /bits/ 64 <187500000>;
2757 required-opps = <&rpmhpd_opp_svs>;
2760 opp-300000000 {
2761 opp-hz = /bits/ 64 <300000000>;
2762 required-opps = <&rpmhpd_opp_svs>;
2765 opp-358000000 {
2766 opp-hz = /bits/ 64 <358000000>;
2767 required-opps = <&rpmhpd_opp_svs_l1>;
2772 #address-cells = <1>;
2773 #size-cells = <0>;
2778 remote-endpoint = <&dpu_intf2_out>;
2791 compatible = "qcom,sm8350-dsi-phy-5nm";
2795 reg-names = "dsi_phy",
2799 #clock-cells = <1>;
2800 #phy-cells = <0>;
2804 clock-names = "iface", "ref";
2810 dispcc: clock-controller@af00000 {
2811 compatible = "qcom,sm8350-dispcc";
2818 clock-names = "bi_tcxo",
2825 #clock-cells = <1>;
2826 #reset-cells = <1>;
2827 #power-domain-cells = <1>;
2829 power-domains = <&rpmhpd RPMHPD_MMCX>;
2832 pdc: interrupt-controller@b220000 {
2833 compatible = "qcom,sm8350-pdc", "qcom,pdc";
2835 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2839 #interrupt-cells = <2>;
2840 interrupt-parent = <&intc>;
2841 interrupt-controller;
2844 tsens0: thermal-sensor@c263000 {
2845 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2849 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2851 interrupt-names = "uplow", "critical";
2852 #thermal-sensor-cells = <1>;
2855 tsens1: thermal-sensor@c265000 {
2856 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2860 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2862 interrupt-names = "uplow", "critical";
2863 #thermal-sensor-cells = <1>;
2866 aoss_qmp: power-management@c300000 {
2867 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
2869 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2873 #clock-cells = <0>;
2877 compatible = "qcom,rpmh-stats";
2882 compatible = "qcom,spmi-pmic-arb";
2888 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2889 interrupt-names = "periph_irq";
2890 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2893 #address-cells = <2>;
2894 #size-cells = <0>;
2895 interrupt-controller;
2896 #interrupt-cells = <4>;
2900 compatible = "qcom,sm8350-tlmm";
2903 gpio-controller;
2904 #gpio-cells = <2>;
2905 interrupt-controller;
2906 #interrupt-cells = <2>;
2907 gpio-ranges = <&tlmm 0 0 204>;
2908 wakeup-parent = <&pdc>;
2910 sdc2_default_state: sdc2-default-state {
2911 clk-pins {
2913 drive-strength = <16>;
2914 bias-disable;
2917 cmd-pins {
2919 drive-strength = <16>;
2920 bias-pull-up;
2923 data-pins {
2925 drive-strength = <16>;
2926 bias-pull-up;
2930 sdc2_sleep_state: sdc2-sleep-state {
2931 clk-pins {
2933 drive-strength = <2>;
2934 bias-disable;
2937 cmd-pins {
2939 drive-strength = <2>;
2940 bias-pull-up;
2943 data-pins {
2945 drive-strength = <2>;
2946 bias-pull-up;
2950 qup_uart3_default_state: qup-uart3-default-state {
2951 rx-pins {
2955 tx-pins {
2961 qup_uart6_default: qup-uart6-default-state {
2964 drive-strength = <2>;
2965 bias-disable;
2968 qup_uart18_default: qup-uart18-default-state {
2971 drive-strength = <2>;
2972 bias-disable;
2975 qup_i2c0_default: qup-i2c0-default-state {
2978 drive-strength = <2>;
2979 bias-pull-up;
2982 qup_i2c1_default: qup-i2c1-default-state {
2985 drive-strength = <2>;
2986 bias-pull-up;
2989 qup_i2c2_default: qup-i2c2-default-state {
2992 drive-strength = <2>;
2993 bias-pull-up;
2996 qup_i2c4_default: qup-i2c4-default-state {
2999 drive-strength = <2>;
3000 bias-pull-up;
3003 qup_i2c5_default: qup-i2c5-default-state {
3006 drive-strength = <2>;
3007 bias-pull-up;
3010 qup_i2c6_default: qup-i2c6-default-state {
3013 drive-strength = <2>;
3014 bias-pull-up;
3017 qup_i2c7_default: qup-i2c7-default-state {
3020 drive-strength = <2>;
3021 bias-disable;
3024 qup_i2c8_default: qup-i2c8-default-state {
3027 drive-strength = <2>;
3028 bias-pull-up;
3031 qup_i2c9_default: qup-i2c9-default-state {
3034 drive-strength = <2>;
3035 bias-pull-up;
3038 qup_i2c10_default: qup-i2c10-default-state {
3041 drive-strength = <2>;
3042 bias-pull-up;
3045 qup_i2c11_default: qup-i2c11-default-state {
3048 drive-strength = <2>;
3049 bias-pull-up;
3052 qup_i2c12_default: qup-i2c12-default-state {
3055 drive-strength = <2>;
3056 bias-pull-up;
3059 qup_i2c13_default: qup-i2c13-default-state {
3062 drive-strength = <2>;
3063 bias-pull-up;
3066 qup_i2c14_default: qup-i2c14-default-state {
3069 drive-strength = <2>;
3070 bias-disable;
3073 qup_i2c15_default: qup-i2c15-default-state {
3076 drive-strength = <2>;
3077 bias-disable;
3080 qup_i2c16_default: qup-i2c16-default-state {
3083 drive-strength = <2>;
3084 bias-disable;
3087 qup_i2c17_default: qup-i2c17-default-state {
3090 drive-strength = <2>;
3091 bias-disable;
3094 qup_i2c19_default: qup-i2c19-default-state {
3097 drive-strength = <2>;
3098 bias-disable;
3103 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
3105 #iommu-cells = <2>;
3106 #global-interrupts = <2>;
3208 compatible = "qcom,sm8350-adsp-pas";
3211 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3216 interrupt-names = "wdog", "fatal", "ready",
3217 "handover", "stop-ack";
3220 clock-names = "xo";
3222 power-domains = <&rpmhpd RPMHPD_LCX>,
3224 power-domain-names = "lcx", "lmx";
3226 memory-region = <&pil_adsp_mem>;
3230 qcom,smem-states = <&smp2p_adsp_out 0>;
3231 qcom,smem-state-names = "stop";
3235 glink-edge {
3236 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3243 qcom,remote-pid = <2>;
3246 compatible = "qcom,apr-v2";
3247 qcom,glink-channels = "apr_audio_svc";
3249 #address-cells = <1>;
3250 #size-cells = <0>;
3255 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3261 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3264 compatible = "qcom,q6afe-dais";
3265 #address-cells = <1>;
3266 #size-cells = <0>;
3267 #sound-dai-cells = <1>;
3270 q6afecc: clock-controller {
3271 compatible = "qcom,q6afe-clocks";
3272 #clock-cells = <2>;
3279 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3282 compatible = "qcom,q6asm-dais";
3283 #address-cells = <1>;
3284 #size-cells = <0>;
3285 #sound-dai-cells = <1>;
3305 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3308 compatible = "qcom,q6adm-routing";
3309 #sound-dai-cells = <0>;
3316 qcom,glink-channels = "fastrpcglink-apps-dsp";
3318 qcom,non-secure-domain;
3319 #address-cells = <1>;
3320 #size-cells = <0>;
3322 compute-cb@3 {
3323 compatible = "qcom,fastrpc-compute-cb";
3328 compute-cb@4 {
3329 compatible = "qcom,fastrpc-compute-cb";
3334 compute-cb@5 {
3335 compatible = "qcom,fastrpc-compute-cb";
3343 intc: interrupt-controller@17a00000 {
3344 compatible = "arm,gic-v3";
3345 #interrupt-cells = <3>;
3346 interrupt-controller;
3347 #redistributor-regions = <1>;
3348 redistributor-stride = <0 0x20000>;
3355 compatible = "arm,armv7-timer-mem";
3356 #address-cells = <1>;
3357 #size-cells = <1>;
3360 clock-frequency = <19200000>;
3363 frame-number = <0>;
3371 frame-number = <1>;
3378 frame-number = <2>;
3385 frame-number = <3>;
3392 frame-number = <4>;
3399 frame-number = <5>;
3406 frame-number = <6>;
3415 compatible = "qcom,rpmh-rsc";
3419 reg-names = "drv-0", "drv-1", "drv-2";
3423 qcom,tcs-offset = <0xd00>;
3424 qcom,drv-id = <2>;
3425 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3427 power-domains = <&CLUSTER_PD>;
3429 rpmhcc: clock-controller {
3430 compatible = "qcom,sm8350-rpmh-clk";
3431 #clock-cells = <1>;
3432 clock-names = "xo";
3436 rpmhpd: power-controller {
3437 compatible = "qcom,sm8350-rpmhpd";
3438 #power-domain-cells = <1>;
3439 operating-points-v2 = <&rpmhpd_opp_table>;
3441 rpmhpd_opp_table: opp-table {
3442 compatible = "operating-points-v2";
3445 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3449 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3453 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3457 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3461 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3465 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3469 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3473 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3477 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3481 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3486 apps_bcm_voter: bcm-voter {
3487 compatible = "qcom,bcm-voter";
3492 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3496 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3501 interrupt-names = "dcvsh-irq-0",
3502 "dcvsh-irq-1",
3503 "dcvsh-irq-2";
3506 clock-names = "xo", "alternate";
3508 #freq-domain-cells = <1>;
3509 #clock-cells = <1>;
3513 compatible = "qcom,sm8350-cdsp-pas";
3516 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3521 interrupt-names = "wdog", "fatal", "ready",
3522 "handover", "stop-ack";
3525 clock-names = "xo";
3527 power-domains = <&rpmhpd RPMHPD_CX>,
3529 power-domain-names = "cx", "mxc";
3533 memory-region = <&pil_cdsp_mem>;
3537 qcom,smem-states = <&smp2p_cdsp_out 0>;
3538 qcom,smem-state-names = "stop";
3542 glink-edge {
3543 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3550 qcom,remote-pid = <5>;
3554 qcom,glink-channels = "fastrpcglink-apps-dsp";
3556 qcom,non-secure-domain;
3557 #address-cells = <1>;
3558 #size-cells = <0>;
3560 compute-cb@1 {
3561 compatible = "qcom,fastrpc-compute-cb";
3567 compute-cb@2 {
3568 compatible = "qcom,fastrpc-compute-cb";
3574 compute-cb@3 {
3575 compatible = "qcom,fastrpc-compute-cb";
3581 compute-cb@4 {
3582 compatible = "qcom,fastrpc-compute-cb";
3588 compute-cb@5 {
3589 compatible = "qcom,fastrpc-compute-cb";
3595 compute-cb@6 {
3596 compatible = "qcom,fastrpc-compute-cb";
3602 compute-cb@7 {
3603 compatible = "qcom,fastrpc-compute-cb";
3609 compute-cb@8 {
3610 compatible = "qcom,fastrpc-compute-cb";
3622 thermal_zones: thermal-zones {
3623 cpu0-thermal {
3624 polling-delay-passive = <250>;
3625 polling-delay = <1000>;
3627 thermal-sensors = <&tsens0 1>;
3630 cpu0_alert0: trip-point0 {
3636 cpu0_alert1: trip-point1 {
3642 cpu0_crit: cpu-crit {
3649 cooling-maps {
3652 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3659 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3667 cpu1-thermal {
3668 polling-delay-passive = <250>;
3669 polling-delay = <1000>;
3671 thermal-sensors = <&tsens0 2>;
3674 cpu1_alert0: trip-point0 {
3680 cpu1_alert1: trip-point1 {
3686 cpu1_crit: cpu-crit {
3693 cooling-maps {
3696 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3703 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3711 cpu2-thermal {
3712 polling-delay-passive = <250>;
3713 polling-delay = <1000>;
3715 thermal-sensors = <&tsens0 3>;
3718 cpu2_alert0: trip-point0 {
3724 cpu2_alert1: trip-point1 {
3730 cpu2_crit: cpu-crit {
3737 cooling-maps {
3740 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3747 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3755 cpu3-thermal {
3756 polling-delay-passive = <250>;
3757 polling-delay = <1000>;
3759 thermal-sensors = <&tsens0 4>;
3762 cpu3_alert0: trip-point0 {
3768 cpu3_alert1: trip-point1 {
3774 cpu3_crit: cpu-crit {
3781 cooling-maps {
3784 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3791 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3799 cpu4-top-thermal {
3800 polling-delay-passive = <250>;
3801 polling-delay = <1000>;
3803 thermal-sensors = <&tsens0 7>;
3806 cpu4_top_alert0: trip-point0 {
3812 cpu4_top_alert1: trip-point1 {
3818 cpu4_top_crit: cpu-crit {
3825 cooling-maps {
3828 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3835 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3843 cpu5-top-thermal {
3844 polling-delay-passive = <250>;
3845 polling-delay = <1000>;
3847 thermal-sensors = <&tsens0 8>;
3850 cpu5_top_alert0: trip-point0 {
3856 cpu5_top_alert1: trip-point1 {
3862 cpu5_top_crit: cpu-crit {
3869 cooling-maps {
3872 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3879 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3887 cpu6-top-thermal {
3888 polling-delay-passive = <250>;
3889 polling-delay = <1000>;
3891 thermal-sensors = <&tsens0 9>;
3894 cpu6_top_alert0: trip-point0 {
3900 cpu6_top_alert1: trip-point1 {
3906 cpu6_top_crit: cpu-crit {
3913 cooling-maps {
3916 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3923 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3931 cpu7-top-thermal {
3932 polling-delay-passive = <250>;
3933 polling-delay = <1000>;
3935 thermal-sensors = <&tsens0 10>;
3938 cpu7_top_alert0: trip-point0 {
3944 cpu7_top_alert1: trip-point1 {
3950 cpu7_top_crit: cpu-crit {
3957 cooling-maps {
3960 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3967 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3975 cpu4-bottom-thermal {
3976 polling-delay-passive = <250>;
3977 polling-delay = <1000>;
3979 thermal-sensors = <&tsens0 11>;
3982 cpu4_bottom_alert0: trip-point0 {
3988 cpu4_bottom_alert1: trip-point1 {
3994 cpu4_bottom_crit: cpu-crit {
4001 cooling-maps {
4004 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4011 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4019 cpu5-bottom-thermal {
4020 polling-delay-passive = <250>;
4021 polling-delay = <1000>;
4023 thermal-sensors = <&tsens0 12>;
4026 cpu5_bottom_alert0: trip-point0 {
4032 cpu5_bottom_alert1: trip-point1 {
4038 cpu5_bottom_crit: cpu-crit {
4045 cooling-maps {
4048 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4055 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4063 cpu6-bottom-thermal {
4064 polling-delay-passive = <250>;
4065 polling-delay = <1000>;
4067 thermal-sensors = <&tsens0 13>;
4070 cpu6_bottom_alert0: trip-point0 {
4076 cpu6_bottom_alert1: trip-point1 {
4082 cpu6_bottom_crit: cpu-crit {
4089 cooling-maps {
4092 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4099 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4107 cpu7-bottom-thermal {
4108 polling-delay-passive = <250>;
4109 polling-delay = <1000>;
4111 thermal-sensors = <&tsens0 14>;
4114 cpu7_bottom_alert0: trip-point0 {
4120 cpu7_bottom_alert1: trip-point1 {
4126 cpu7_bottom_crit: cpu-crit {
4133 cooling-maps {
4136 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4143 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4151 aoss0-thermal {
4152 polling-delay-passive = <250>;
4153 polling-delay = <1000>;
4155 thermal-sensors = <&tsens0 0>;
4158 aoss0_alert0: trip-point0 {
4166 cluster0-thermal {
4167 polling-delay-passive = <250>;
4168 polling-delay = <1000>;
4170 thermal-sensors = <&tsens0 5>;
4173 cluster0_alert0: trip-point0 {
4186 cluster1-thermal {
4187 polling-delay-passive = <250>;
4188 polling-delay = <1000>;
4190 thermal-sensors = <&tsens0 6>;
4193 cluster1_alert0: trip-point0 {
4206 aoss1-thermal {
4207 polling-delay-passive = <250>;
4208 polling-delay = <1000>;
4210 thermal-sensors = <&tsens1 0>;
4213 aoss1_alert0: trip-point0 {
4221 gpu-top-thermal {
4222 polling-delay-passive = <250>;
4223 polling-delay = <1000>;
4225 thermal-sensors = <&tsens1 1>;
4228 gpu1_alert0: trip-point0 {
4236 gpu-bottom-thermal {
4237 polling-delay-passive = <250>;
4238 polling-delay = <1000>;
4240 thermal-sensors = <&tsens1 2>;
4243 gpu2_alert0: trip-point0 {
4251 nspss1-thermal {
4252 polling-delay-passive = <250>;
4253 polling-delay = <1000>;
4255 thermal-sensors = <&tsens1 3>;
4258 nspss1_alert0: trip-point0 {
4266 nspss2-thermal {
4267 polling-delay-passive = <250>;
4268 polling-delay = <1000>;
4270 thermal-sensors = <&tsens1 4>;
4273 nspss2_alert0: trip-point0 {
4281 nspss3-thermal {
4282 polling-delay-passive = <250>;
4283 polling-delay = <1000>;
4285 thermal-sensors = <&tsens1 5>;
4288 nspss3_alert0: trip-point0 {
4296 video-thermal {
4297 polling-delay-passive = <250>;
4298 polling-delay = <1000>;
4300 thermal-sensors = <&tsens1 6>;
4303 video_alert0: trip-point0 {
4311 mem-thermal {
4312 polling-delay-passive = <250>;
4313 polling-delay = <1000>;
4315 thermal-sensors = <&tsens1 7>;
4318 mem_alert0: trip-point0 {
4326 modem1-top-thermal {
4327 polling-delay-passive = <250>;
4328 polling-delay = <1000>;
4330 thermal-sensors = <&tsens1 8>;
4333 modem1_alert0: trip-point0 {
4341 modem2-top-thermal {
4342 polling-delay-passive = <250>;
4343 polling-delay = <1000>;
4345 thermal-sensors = <&tsens1 9>;
4348 modem2_alert0: trip-point0 {
4356 modem3-top-thermal {
4357 polling-delay-passive = <250>;
4358 polling-delay = <1000>;
4360 thermal-sensors = <&tsens1 10>;
4363 modem3_alert0: trip-point0 {
4371 modem4-top-thermal {
4372 polling-delay-passive = <250>;
4373 polling-delay = <1000>;
4375 thermal-sensors = <&tsens1 11>;
4378 modem4_alert0: trip-point0 {
4386 camera-top-thermal {
4387 polling-delay-passive = <250>;
4388 polling-delay = <1000>;
4390 thermal-sensors = <&tsens1 12>;
4393 camera1_alert0: trip-point0 {
4401 cam-bottom-thermal {
4402 polling-delay-passive = <250>;
4403 polling-delay = <1000>;
4405 thermal-sensors = <&tsens1 13>;
4408 camera2_alert0: trip-point0 {
4418 compatible = "arm,armv8-timer";