Lines Matching +full:pdc +full:- +full:global
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,sm8350.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
9 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,sm8350.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/interconnect/qcom,sm8350.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <38400000>;
38 clock-output-names = "xo_board";
41 sleep_clk: sleep-clk {
42 compatible = "fixed-clock";
43 clock-frequency = <32764>;
44 #clock-cells = <0>;
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a55";
57 enable-method = "psci";
58 next-level-cache = <&L2_0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
60 power-domains = <&CPU_PD0>;
61 power-domain-names = "psci";
62 #cooling-cells = <2>;
63 L2_0: l2-cache {
65 cache-level = <2>;
66 cache-unified;
67 next-level-cache = <&L3_0>;
68 L3_0: l3-cache {
70 cache-level = <3>;
71 cache-unified;
78 compatible = "arm,cortex-a55";
81 enable-method = "psci";
82 next-level-cache = <&L2_100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
84 power-domains = <&CPU_PD1>;
85 power-domain-names = "psci";
86 #cooling-cells = <2>;
87 L2_100: l2-cache {
89 cache-level = <2>;
90 cache-unified;
91 next-level-cache = <&L3_0>;
97 compatible = "arm,cortex-a55";
100 enable-method = "psci";
101 next-level-cache = <&L2_200>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 power-domains = <&CPU_PD2>;
104 power-domain-names = "psci";
105 #cooling-cells = <2>;
106 L2_200: l2-cache {
108 cache-level = <2>;
109 cache-unified;
110 next-level-cache = <&L3_0>;
116 compatible = "arm,cortex-a55";
119 enable-method = "psci";
120 next-level-cache = <&L2_300>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 power-domains = <&CPU_PD3>;
123 power-domain-names = "psci";
124 #cooling-cells = <2>;
125 L2_300: l2-cache {
127 cache-level = <2>;
128 cache-unified;
129 next-level-cache = <&L3_0>;
135 compatible = "arm,cortex-a78";
138 enable-method = "psci";
139 next-level-cache = <&L2_400>;
140 qcom,freq-domain = <&cpufreq_hw 1>;
141 power-domains = <&CPU_PD4>;
142 power-domain-names = "psci";
143 #cooling-cells = <2>;
144 L2_400: l2-cache {
146 cache-level = <2>;
147 cache-unified;
148 next-level-cache = <&L3_0>;
154 compatible = "arm,cortex-a78";
157 enable-method = "psci";
158 next-level-cache = <&L2_500>;
159 qcom,freq-domain = <&cpufreq_hw 1>;
160 power-domains = <&CPU_PD5>;
161 power-domain-names = "psci";
162 #cooling-cells = <2>;
163 L2_500: l2-cache {
165 cache-level = <2>;
166 cache-unified;
167 next-level-cache = <&L3_0>;
173 compatible = "arm,cortex-a78";
176 enable-method = "psci";
177 next-level-cache = <&L2_600>;
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 power-domains = <&CPU_PD6>;
180 power-domain-names = "psci";
181 #cooling-cells = <2>;
182 L2_600: l2-cache {
184 cache-level = <2>;
185 cache-unified;
186 next-level-cache = <&L3_0>;
192 compatible = "arm,cortex-x1";
195 enable-method = "psci";
196 next-level-cache = <&L2_700>;
197 qcom,freq-domain = <&cpufreq_hw 2>;
198 power-domains = <&CPU_PD7>;
199 power-domain-names = "psci";
200 #cooling-cells = <2>;
201 L2_700: l2-cache {
203 cache-level = <2>;
204 cache-unified;
205 next-level-cache = <&L3_0>;
209 cpu-map {
245 idle-states {
246 entry-method = "psci";
248 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
249 compatible = "arm,idle-state";
250 idle-state-name = "silver-rail-power-collapse";
251 arm,psci-suspend-param = <0x40000004>;
252 entry-latency-us = <360>;
253 exit-latency-us = <531>;
254 min-residency-us = <3934>;
255 local-timer-stop;
258 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
259 compatible = "arm,idle-state";
260 idle-state-name = "gold-rail-power-collapse";
261 arm,psci-suspend-param = <0x40000004>;
262 entry-latency-us = <702>;
263 exit-latency-us = <1061>;
264 min-residency-us = <4488>;
265 local-timer-stop;
269 domain-idle-states {
270 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
271 compatible = "domain-idle-state";
272 arm,psci-suspend-param = <0x41000044>;
273 entry-latency-us = <2752>;
274 exit-latency-us = <3048>;
275 min-residency-us = <6118>;
278 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
279 compatible = "domain-idle-state";
280 arm,psci-suspend-param = <0x4100c344>;
281 entry-latency-us = <3263>;
282 exit-latency-us = <6562>;
283 min-residency-us = <9987>;
290 compatible = "qcom,scm-sm8350", "qcom,scm";
291 #reset-cells = <1>;
302 compatible = "arm,armv8-pmuv3";
307 compatible = "arm,psci-1.0";
310 CPU_PD0: power-domain-cpu0 {
311 #power-domain-cells = <0>;
312 power-domains = <&CLUSTER_PD>;
313 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
316 CPU_PD1: power-domain-cpu1 {
317 #power-domain-cells = <0>;
318 power-domains = <&CLUSTER_PD>;
319 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
322 CPU_PD2: power-domain-cpu2 {
323 #power-domain-cells = <0>;
324 power-domains = <&CLUSTER_PD>;
325 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
328 CPU_PD3: power-domain-cpu3 {
329 #power-domain-cells = <0>;
330 power-domains = <&CLUSTER_PD>;
331 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
334 CPU_PD4: power-domain-cpu4 {
335 #power-domain-cells = <0>;
336 power-domains = <&CLUSTER_PD>;
337 domain-idle-states = <&BIG_CPU_SLEEP_0>;
340 CPU_PD5: power-domain-cpu5 {
341 #power-domain-cells = <0>;
342 power-domains = <&CLUSTER_PD>;
343 domain-idle-states = <&BIG_CPU_SLEEP_0>;
346 CPU_PD6: power-domain-cpu6 {
347 #power-domain-cells = <0>;
348 power-domains = <&CLUSTER_PD>;
349 domain-idle-states = <&BIG_CPU_SLEEP_0>;
352 CPU_PD7: power-domain-cpu7 {
353 #power-domain-cells = <0>;
354 power-domains = <&CLUSTER_PD>;
355 domain-idle-states = <&BIG_CPU_SLEEP_0>;
358 CLUSTER_PD: power-domain-cpu-cluster0 {
359 #power-domain-cells = <0>;
360 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
364 qup_opp_table_100mhz: opp-table-qup100mhz {
365 compatible = "operating-points-v2";
367 opp-50000000 {
368 opp-hz = /bits/ 64 <50000000>;
369 required-opps = <&rpmhpd_opp_min_svs>;
372 opp-75000000 {
373 opp-hz = /bits/ 64 <75000000>;
374 required-opps = <&rpmhpd_opp_low_svs>;
377 opp-100000000 {
378 opp-hz = /bits/ 64 <100000000>;
379 required-opps = <&rpmhpd_opp_svs>;
383 qup_opp_table_120mhz: opp-table-qup120mhz {
384 compatible = "operating-points-v2";
386 opp-50000000 {
387 opp-hz = /bits/ 64 <50000000>;
388 required-opps = <&rpmhpd_opp_min_svs>;
391 opp-75000000 {
392 opp-hz = /bits/ 64 <75000000>;
393 required-opps = <&rpmhpd_opp_low_svs>;
396 opp-120000000 {
397 opp-hz = /bits/ 64 <120000000>;
398 required-opps = <&rpmhpd_opp_svs>;
402 reserved_memory: reserved-memory {
403 #address-cells = <2>;
404 #size-cells = <2>;
409 no-map;
413 no-map;
418 compatible = "qcom,cmd-db";
420 no-map;
425 no-map;
432 no-map;
437 no-map;
442 no-map;
447 no-map;
452 no-map;
457 no-map;
462 no-map;
467 no-map;
472 no-map;
477 no-map;
482 no-map;
487 no-map;
492 no-map;
497 no-map;
501 compatible = "qcom,rmtfs-mem";
503 no-map;
505 qcom,client-id = <1>;
511 no-map;
516 no-map;
521 no-map;
526 no-map;
531 no-map;
536 no-map;
540 smp2p-adsp {
543 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
549 qcom,local-pid = <0>;
550 qcom,remote-pid = <2>;
552 smp2p_adsp_out: master-kernel {
553 qcom,entry-name = "master-kernel";
554 #qcom,smem-state-cells = <1>;
557 smp2p_adsp_in: slave-kernel {
558 qcom,entry-name = "slave-kernel";
559 interrupt-controller;
560 #interrupt-cells = <2>;
564 smp2p-cdsp {
567 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
573 qcom,local-pid = <0>;
574 qcom,remote-pid = <5>;
576 smp2p_cdsp_out: master-kernel {
577 qcom,entry-name = "master-kernel";
578 #qcom,smem-state-cells = <1>;
581 smp2p_cdsp_in: slave-kernel {
582 qcom,entry-name = "slave-kernel";
583 interrupt-controller;
584 #interrupt-cells = <2>;
588 smp2p-modem {
591 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
597 qcom,local-pid = <0>;
598 qcom,remote-pid = <1>;
600 smp2p_modem_out: master-kernel {
601 qcom,entry-name = "master-kernel";
602 #qcom,smem-state-cells = <1>;
605 smp2p_modem_in: slave-kernel {
606 qcom,entry-name = "slave-kernel";
607 interrupt-controller;
608 #interrupt-cells = <2>;
611 ipa_smp2p_out: ipa-ap-to-modem {
612 qcom,entry-name = "ipa";
613 #qcom,smem-state-cells = <1>;
616 ipa_smp2p_in: ipa-modem-to-ap {
617 qcom,entry-name = "ipa";
618 interrupt-controller;
619 #interrupt-cells = <2>;
623 smp2p-slpi {
626 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
632 qcom,local-pid = <0>;
633 qcom,remote-pid = <3>;
635 smp2p_slpi_out: master-kernel {
636 qcom,entry-name = "master-kernel";
637 #qcom,smem-state-cells = <1>;
640 smp2p_slpi_in: slave-kernel {
641 qcom,entry-name = "slave-kernel";
642 interrupt-controller;
643 #interrupt-cells = <2>;
648 #address-cells = <2>;
649 #size-cells = <2>;
651 dma-ranges = <0 0 0 0 0x10 0>;
652 compatible = "simple-bus";
654 gcc: clock-controller@100000 {
655 compatible = "qcom,gcc-sm8350";
657 #clock-cells = <1>;
658 #reset-cells = <1>;
659 #power-domain-cells = <1>;
660 clock-names = "bi_tcxo",
687 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
690 interrupt-controller;
691 #interrupt-cells = <3>;
692 #mbox-cells = <2>;
695 gpi_dma2: dma-controller@800000 {
696 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
710 dma-channels = <12>;
711 dma-channel-mask = <0xff>;
713 #dma-cells = <3>;
718 compatible = "qcom,geni-se-qup";
720 clock-names = "m-ahb", "s-ahb";
724 #address-cells = <2>;
725 #size-cells = <2>;
730 compatible = "qcom,geni-i2c";
732 clock-names = "se";
734 pinctrl-names = "default";
735 pinctrl-0 = <&qup_i2c14_default>;
739 dma-names = "tx", "rx";
740 #address-cells = <1>;
741 #size-cells = <0>;
746 compatible = "qcom,geni-spi";
748 clock-names = "se";
751 power-domains = <&rpmhpd RPMHPD_CX>;
752 operating-points-v2 = <&qup_opp_table_120mhz>;
755 dma-names = "tx", "rx";
756 #address-cells = <1>;
757 #size-cells = <0>;
762 compatible = "qcom,geni-i2c";
764 clock-names = "se";
766 pinctrl-names = "default";
767 pinctrl-0 = <&qup_i2c15_default>;
771 dma-names = "tx", "rx";
772 #address-cells = <1>;
773 #size-cells = <0>;
778 compatible = "qcom,geni-spi";
780 clock-names = "se";
783 power-domains = <&rpmhpd RPMHPD_CX>;
784 operating-points-v2 = <&qup_opp_table_120mhz>;
787 dma-names = "tx", "rx";
788 #address-cells = <1>;
789 #size-cells = <0>;
794 compatible = "qcom,geni-i2c";
796 clock-names = "se";
798 pinctrl-names = "default";
799 pinctrl-0 = <&qup_i2c16_default>;
803 dma-names = "tx", "rx";
804 #address-cells = <1>;
805 #size-cells = <0>;
810 compatible = "qcom,geni-spi";
812 clock-names = "se";
815 power-domains = <&rpmhpd RPMHPD_CX>;
816 operating-points-v2 = <&qup_opp_table_100mhz>;
819 dma-names = "tx", "rx";
820 #address-cells = <1>;
821 #size-cells = <0>;
826 compatible = "qcom,geni-i2c";
828 clock-names = "se";
830 pinctrl-names = "default";
831 pinctrl-0 = <&qup_i2c17_default>;
835 dma-names = "tx", "rx";
836 #address-cells = <1>;
837 #size-cells = <0>;
842 compatible = "qcom,geni-spi";
844 clock-names = "se";
847 power-domains = <&rpmhpd RPMHPD_CX>;
848 operating-points-v2 = <&qup_opp_table_100mhz>;
851 dma-names = "tx", "rx";
852 #address-cells = <1>;
853 #size-cells = <0>;
857 /* QUP no. 18 seems to be strictly SPI/UART-only */
860 compatible = "qcom,geni-spi";
862 clock-names = "se";
865 power-domains = <&rpmhpd RPMHPD_CX>;
866 operating-points-v2 = <&qup_opp_table_100mhz>;
869 dma-names = "tx", "rx";
870 #address-cells = <1>;
871 #size-cells = <0>;
876 compatible = "qcom,geni-uart";
878 clock-names = "se";
880 pinctrl-names = "default";
881 pinctrl-0 = <&qup_uart18_default>;
883 power-domains = <&rpmhpd RPMHPD_CX>;
884 operating-points-v2 = <&qup_opp_table_100mhz>;
889 compatible = "qcom,geni-i2c";
891 clock-names = "se";
893 pinctrl-names = "default";
894 pinctrl-0 = <&qup_i2c19_default>;
898 dma-names = "tx", "rx";
899 #address-cells = <1>;
900 #size-cells = <0>;
905 compatible = "qcom,geni-spi";
907 clock-names = "se";
910 power-domains = <&rpmhpd RPMHPD_CX>;
911 operating-points-v2 = <&qup_opp_table_100mhz>;
914 dma-names = "tx", "rx";
915 #address-cells = <1>;
916 #size-cells = <0>;
921 gpi_dma0: dma-controller@900000 {
922 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
936 dma-channels = <12>;
937 dma-channel-mask = <0x7e>;
939 #dma-cells = <3>;
944 compatible = "qcom,geni-se-qup";
946 clock-names = "m-ahb", "s-ahb";
950 #address-cells = <2>;
951 #size-cells = <2>;
956 compatible = "qcom,geni-i2c";
958 clock-names = "se";
960 pinctrl-names = "default";
961 pinctrl-0 = <&qup_i2c0_default>;
965 dma-names = "tx", "rx";
966 #address-cells = <1>;
967 #size-cells = <0>;
972 compatible = "qcom,geni-spi";
974 clock-names = "se";
977 power-domains = <&rpmhpd RPMHPD_CX>;
978 operating-points-v2 = <&qup_opp_table_100mhz>;
981 dma-names = "tx", "rx";
982 #address-cells = <1>;
983 #size-cells = <0>;
988 compatible = "qcom,geni-i2c";
990 clock-names = "se";
992 pinctrl-names = "default";
993 pinctrl-0 = <&qup_i2c1_default>;
997 dma-names = "tx", "rx";
998 #address-cells = <1>;
999 #size-cells = <0>;
1004 compatible = "qcom,geni-spi";
1006 clock-names = "se";
1009 power-domains = <&rpmhpd RPMHPD_CX>;
1010 operating-points-v2 = <&qup_opp_table_100mhz>;
1013 dma-names = "tx", "rx";
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1020 compatible = "qcom,geni-i2c";
1022 clock-names = "se";
1024 pinctrl-names = "default";
1025 pinctrl-0 = <&qup_i2c2_default>;
1029 dma-names = "tx", "rx";
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1036 compatible = "qcom,geni-spi";
1038 clock-names = "se";
1041 power-domains = <&rpmhpd RPMHPD_CX>;
1042 operating-points-v2 = <&qup_opp_table_100mhz>;
1045 dma-names = "tx", "rx";
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1052 compatible = "qcom,geni-debug-uart";
1054 clock-names = "se";
1056 pinctrl-names = "default";
1057 pinctrl-0 = <&qup_uart3_default_state>;
1059 power-domains = <&rpmhpd RPMHPD_CX>;
1060 operating-points-v2 = <&qup_opp_table_100mhz>;
1064 /* QUP no. 3 seems to be strictly SPI-only */
1067 compatible = "qcom,geni-spi";
1069 clock-names = "se";
1072 power-domains = <&rpmhpd RPMHPD_CX>;
1073 operating-points-v2 = <&qup_opp_table_100mhz>;
1076 dma-names = "tx", "rx";
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1083 compatible = "qcom,geni-i2c";
1085 clock-names = "se";
1087 pinctrl-names = "default";
1088 pinctrl-0 = <&qup_i2c4_default>;
1092 dma-names = "tx", "rx";
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1099 compatible = "qcom,geni-spi";
1101 clock-names = "se";
1104 power-domains = <&rpmhpd RPMHPD_CX>;
1105 operating-points-v2 = <&qup_opp_table_100mhz>;
1108 dma-names = "tx", "rx";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1115 compatible = "qcom,geni-i2c";
1117 clock-names = "se";
1119 pinctrl-names = "default";
1120 pinctrl-0 = <&qup_i2c5_default>;
1124 dma-names = "tx", "rx";
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1131 compatible = "qcom,geni-spi";
1133 clock-names = "se";
1136 power-domains = <&rpmhpd RPMHPD_CX>;
1137 operating-points-v2 = <&qup_opp_table_100mhz>;
1140 dma-names = "tx", "rx";
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1147 compatible = "qcom,geni-i2c";
1149 clock-names = "se";
1151 pinctrl-names = "default";
1152 pinctrl-0 = <&qup_i2c6_default>;
1156 dma-names = "tx", "rx";
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1163 compatible = "qcom,geni-spi";
1165 clock-names = "se";
1168 power-domains = <&rpmhpd RPMHPD_CX>;
1169 operating-points-v2 = <&qup_opp_table_100mhz>;
1172 dma-names = "tx", "rx";
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1179 compatible = "qcom,geni-uart";
1181 clock-names = "se";
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&qup_uart6_default>;
1186 power-domains = <&rpmhpd RPMHPD_CX>;
1187 operating-points-v2 = <&qup_opp_table_100mhz>;
1192 compatible = "qcom,geni-i2c";
1194 clock-names = "se";
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&qup_i2c7_default>;
1201 dma-names = "tx", "rx";
1202 #address-cells = <1>;
1203 #size-cells = <0>;
1208 compatible = "qcom,geni-spi";
1210 clock-names = "se";
1213 power-domains = <&rpmhpd RPMHPD_CX>;
1214 operating-points-v2 = <&qup_opp_table_100mhz>;
1217 dma-names = "tx", "rx";
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1224 gpi_dma1: dma-controller@a00000 {
1225 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
1239 dma-channels = <12>;
1240 dma-channel-mask = <0xff>;
1242 #dma-cells = <3>;
1247 compatible = "qcom,geni-se-qup";
1249 clock-names = "m-ahb", "s-ahb";
1253 #address-cells = <2>;
1254 #size-cells = <2>;
1259 compatible = "qcom,geni-i2c";
1261 clock-names = "se";
1263 pinctrl-names = "default";
1264 pinctrl-0 = <&qup_i2c8_default>;
1268 dma-names = "tx", "rx";
1269 #address-cells = <1>;
1270 #size-cells = <0>;
1275 compatible = "qcom,geni-spi";
1277 clock-names = "se";
1280 power-domains = <&rpmhpd RPMHPD_CX>;
1281 operating-points-v2 = <&qup_opp_table_120mhz>;
1284 dma-names = "tx", "rx";
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1291 compatible = "qcom,geni-i2c";
1293 clock-names = "se";
1295 pinctrl-names = "default";
1296 pinctrl-0 = <&qup_i2c9_default>;
1300 dma-names = "tx", "rx";
1301 #address-cells = <1>;
1302 #size-cells = <0>;
1307 compatible = "qcom,geni-spi";
1309 clock-names = "se";
1312 power-domains = <&rpmhpd RPMHPD_CX>;
1313 operating-points-v2 = <&qup_opp_table_100mhz>;
1316 dma-names = "tx", "rx";
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1323 compatible = "qcom,geni-i2c";
1325 clock-names = "se";
1327 pinctrl-names = "default";
1328 pinctrl-0 = <&qup_i2c10_default>;
1332 dma-names = "tx", "rx";
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1339 compatible = "qcom,geni-spi";
1341 clock-names = "se";
1344 power-domains = <&rpmhpd RPMHPD_CX>;
1345 operating-points-v2 = <&qup_opp_table_100mhz>;
1348 dma-names = "tx", "rx";
1349 #address-cells = <1>;
1350 #size-cells = <0>;
1355 compatible = "qcom,geni-i2c";
1357 clock-names = "se";
1359 pinctrl-names = "default";
1360 pinctrl-0 = <&qup_i2c11_default>;
1364 dma-names = "tx", "rx";
1365 #address-cells = <1>;
1366 #size-cells = <0>;
1371 compatible = "qcom,geni-spi";
1373 clock-names = "se";
1376 power-domains = <&rpmhpd RPMHPD_CX>;
1377 operating-points-v2 = <&qup_opp_table_100mhz>;
1380 dma-names = "tx", "rx";
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1387 compatible = "qcom,geni-i2c";
1389 clock-names = "se";
1391 pinctrl-names = "default";
1392 pinctrl-0 = <&qup_i2c12_default>;
1396 dma-names = "tx", "rx";
1397 #address-cells = <1>;
1398 #size-cells = <0>;
1403 compatible = "qcom,geni-spi";
1405 clock-names = "se";
1408 power-domains = <&rpmhpd RPMHPD_CX>;
1409 operating-points-v2 = <&qup_opp_table_100mhz>;
1412 dma-names = "tx", "rx";
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1419 compatible = "qcom,geni-i2c";
1421 clock-names = "se";
1423 pinctrl-names = "default";
1424 pinctrl-0 = <&qup_i2c13_default>;
1428 dma-names = "tx", "rx";
1429 #address-cells = <1>;
1430 #size-cells = <0>;
1435 compatible = "qcom,geni-spi";
1437 clock-names = "se";
1440 power-domains = <&rpmhpd RPMHPD_CX>;
1441 operating-points-v2 = <&qup_opp_table_100mhz>;
1444 dma-names = "tx", "rx";
1445 #address-cells = <1>;
1446 #size-cells = <0>;
1452 compatible = "qcom,prng-ee";
1455 clock-names = "core";
1459 compatible = "qcom,sm8350-config-noc";
1461 #interconnect-cells = <2>;
1462 qcom,bcm-voters = <&apps_bcm_voter>;
1466 compatible = "qcom,sm8350-mc-virt";
1468 #interconnect-cells = <2>;
1469 qcom,bcm-voters = <&apps_bcm_voter>;
1473 compatible = "qcom,sm8350-system-noc";
1475 #interconnect-cells = <2>;
1476 qcom,bcm-voters = <&apps_bcm_voter>;
1480 compatible = "qcom,sm8350-aggre1-noc";
1482 #interconnect-cells = <2>;
1483 qcom,bcm-voters = <&apps_bcm_voter>;
1487 compatible = "qcom,sm8350-aggre2-noc";
1489 #interconnect-cells = <2>;
1490 qcom,bcm-voters = <&apps_bcm_voter>;
1494 compatible = "qcom,sm8350-mmss-noc";
1496 #interconnect-cells = <2>;
1497 qcom,bcm-voters = <&apps_bcm_voter>;
1501 compatible = "qcom,pcie-sm8350";
1507 reg-names = "parf", "dbi", "elbi", "atu", "config";
1509 linux,pci-domain = <0>;
1510 bus-range = <0x00 0xff>;
1511 num-lanes = <1>;
1513 #address-cells = <3>;
1514 #size-cells = <2>;
1527 interrupt-names = "msi0", "msi1", "msi2", "msi3",
1529 #interrupt-cells = <1>;
1530 interrupt-map-mask = <0 0 0 0x7>;
1531 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1545 clock-names = "aux",
1555 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1559 reset-names = "pci";
1561 power-domains = <&gcc PCIE_0_GDSC>;
1564 phy-names = "pciephy";
1570 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1577 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1580 reset-names = "phy";
1582 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1583 assigned-clock-rates = <100000000>;
1585 #clock-cells = <0>;
1586 clock-output-names = "pcie_0_pipe_clk";
1588 #phy-cells = <0>;
1594 compatible = "qcom,pcie-sm8350";
1600 reg-names = "parf", "dbi", "elbi", "atu", "config";
1602 linux,pci-domain = <1>;
1603 bus-range = <0x00 0xff>;
1604 num-lanes = <2>;
1606 #address-cells = <3>;
1607 #size-cells = <2>;
1613 interrupt-names = "msi";
1614 #interrupt-cells = <1>;
1615 interrupt-map-mask = <0 0 0 0x7>;
1616 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1629 clock-names = "aux",
1638 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1642 reset-names = "pci";
1644 power-domains = <&gcc PCIE_1_GDSC>;
1647 phy-names = "pciephy";
1653 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1660 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1663 reset-names = "phy";
1665 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1666 assigned-clock-rates = <100000000>;
1668 #clock-cells = <0>;
1669 clock-output-names = "pcie_1_pipe_clk";
1671 #phy-cells = <0>;
1677 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1678 "jedec,ufs-2.0";
1682 phy-names = "ufsphy";
1683 lanes-per-direction = <2>;
1684 #reset-cells = <1>;
1686 reset-names = "rst";
1688 power-domains = <&gcc UFS_PHY_GDSC>;
1691 dma-coherent;
1693 clock-names =
1711 freq-table-hz =
1724 compatible = "qcom,sm8350-qmp-ufs-phy";
1726 #address-cells = <2>;
1727 #size-cells = <2>;
1729 clock-names = "ref",
1734 power-domains = <&gcc UFS_PHY_GDSC>;
1737 reset-names = "ufsphy";
1746 #clock-cells = <1>;
1747 #phy-cells = <0>;
1751 cryptobam: dma-controller@1dc4000 {
1752 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1755 #dma-cells = <1>;
1757 qcom,num-ees = <4>;
1758 num-channels = <16>;
1759 qcom,controlled-remotely;
1765 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce";
1768 dma-names = "rx", "tx";
1772 interconnect-names = "memory";
1776 compatible = "qcom,sm8350-ipa";
1783 reg-names = "ipa-reg",
1784 "ipa-shared",
1787 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1791 interrupt-names = "ipa",
1793 "ipa-clock-query",
1794 "ipa-setup-ready";
1797 clock-names = "core";
1801 interconnect-names = "memory",
1806 qcom,smem-states = <&ipa_smp2p_out 0>,
1808 qcom,smem-state-names = "ipa-clock-enabled-valid",
1809 "ipa-clock-enabled";
1815 compatible = "qcom,tcsr-mutex";
1817 #hwlock-cells = <1>;
1821 compatible = "qcom,sm8350-adsp-pas";
1824 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
1829 interrupt-names = "wdog", "fatal", "ready",
1830 "handover", "stop-ack";
1833 clock-names = "xo";
1835 power-domains = <&rpmhpd RPMHPD_LCX>,
1837 power-domain-names = "lcx", "lmx";
1839 memory-region = <&pil_adsp_mem>;
1843 qcom,smem-states = <&smp2p_adsp_out 0>;
1844 qcom,smem-state-names = "stop";
1848 glink-edge {
1849 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1856 qcom,remote-pid = <2>;
1859 compatible = "qcom,apr-v2";
1860 qcom,glink-channels = "apr_audio_svc";
1862 #address-cells = <1>;
1863 #size-cells = <0>;
1868 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1874 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1877 compatible = "qcom,q6afe-dais";
1878 #address-cells = <1>;
1879 #size-cells = <0>;
1880 #sound-dai-cells = <1>;
1883 q6afecc: clock-controller {
1884 compatible = "qcom,q6afe-clocks";
1885 #clock-cells = <2>;
1892 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1895 compatible = "qcom,q6asm-dais";
1896 #address-cells = <1>;
1897 #size-cells = <0>;
1898 #sound-dai-cells = <1>;
1918 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
1921 compatible = "qcom,q6adm-routing";
1922 #sound-dai-cells = <0>;
1929 qcom,glink-channels = "fastrpcglink-apps-dsp";
1931 qcom,non-secure-domain;
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1935 compute-cb@3 {
1936 compatible = "qcom,fastrpc-compute-cb";
1941 compute-cb@4 {
1942 compatible = "qcom,fastrpc-compute-cb";
1947 compute-cb@5 {
1948 compatible = "qcom,fastrpc-compute-cb";
1957 compatible = "qcom,sm8350-lpass-lpi-pinctrl";
1963 clock-names = "core", "audio";
1965 gpio-controller;
1966 #gpio-cells = <2>;
1967 gpio-ranges = <&lpass_tlmm 0 0 15>;
1971 compatible = "qcom,adreno-660.1", "qcom,adreno";
1976 reg-names = "kgsl_3d0_reg_memory",
1984 operating-points-v2 = <&gpu_opp_table>;
1990 zap-shader {
1991 memory-region = <&pil_gpu_mem>;
1995 gpu_opp_table: opp-table {
1996 compatible = "operating-points-v2";
1998 opp-840000000 {
1999 opp-hz = /bits/ 64 <840000000>;
2000 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2003 opp-778000000 {
2004 opp-hz = /bits/ 64 <778000000>;
2005 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2008 opp-738000000 {
2009 opp-hz = /bits/ 64 <738000000>;
2010 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2013 opp-676000000 {
2014 opp-hz = /bits/ 64 <676000000>;
2015 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2018 opp-608000000 {
2019 opp-hz = /bits/ 64 <608000000>;
2020 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2023 opp-540000000 {
2024 opp-hz = /bits/ 64 <540000000>;
2025 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2028 opp-491000000 {
2029 opp-hz = /bits/ 64 <491000000>;
2030 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2033 opp-443000000 {
2034 opp-hz = /bits/ 64 <443000000>;
2035 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2038 opp-379000000 {
2039 opp-hz = /bits/ 64 <379000000>;
2040 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
2043 opp-315000000 {
2044 opp-hz = /bits/ 64 <315000000>;
2045 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2051 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
2056 reg-names = "gmu", "rscc", "gmu_pdc";
2060 interrupt-names = "hfi", "gmu";
2069 clock-names = "gmu",
2077 power-domains = <&gpucc GPU_CX_GDSC>,
2079 power-domain-names = "cx",
2084 operating-points-v2 = <&gmu_opp_table>;
2086 gmu_opp_table: opp-table {
2087 compatible = "operating-points-v2";
2089 opp-200000000 {
2090 opp-hz = /bits/ 64 <200000000>;
2091 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2096 gpucc: clock-controller@3d90000 {
2097 compatible = "qcom,sm8350-gpucc";
2102 clock-names = "bi_tcxo",
2105 #clock-cells = <1>;
2106 #reset-cells = <1>;
2107 #power-domain-cells = <1>;
2111 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
2112 "qcom,smmu-500", "arm,mmu-500";
2114 #iommu-cells = <2>;
2115 #global-interrupts = <2>;
2136 clock-names = "bus",
2144 power-domains = <&gpucc GPU_CX_GDSC>;
2145 dma-coherent;
2149 compatible = "qcom,sm8350-lpass-ag-noc";
2151 #interconnect-cells = <2>;
2152 qcom,bcm-voters = <&apps_bcm_voter>;
2156 compatible = "qcom,sm8350-mpss-pas";
2159 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2165 interrupt-names = "wdog", "fatal", "ready", "handover",
2166 "stop-ack", "shutdown-ack";
2169 clock-names = "xo";
2171 power-domains = <&rpmhpd RPMHPD_CX>,
2173 power-domain-names = "cx", "mss";
2177 memory-region = <&pil_modem_mem>;
2181 qcom,smem-states = <&smp2p_modem_out 0>;
2182 qcom,smem-state-names = "stop";
2186 glink-edge {
2187 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2193 qcom,remote-pid = <1>;
2198 compatible = "qcom,sm8350-slpi-pas";
2201 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2206 interrupt-names = "wdog", "fatal", "ready",
2207 "handover", "stop-ack";
2210 clock-names = "xo";
2212 power-domains = <&rpmhpd RPMHPD_LCX>,
2214 power-domain-names = "lcx", "lmx";
2216 memory-region = <&pil_slpi_mem>;
2220 qcom,smem-states = <&smp2p_slpi_out 0>;
2221 qcom,smem-state-names = "stop";
2225 glink-edge {
2226 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2233 qcom,remote-pid = <3>;
2237 qcom,glink-channels = "fastrpcglink-apps-dsp";
2239 qcom,non-secure-domain;
2240 #address-cells = <1>;
2241 #size-cells = <0>;
2243 compute-cb@1 {
2244 compatible = "qcom,fastrpc-compute-cb";
2249 compute-cb@2 {
2250 compatible = "qcom,fastrpc-compute-cb";
2255 compute-cb@3 {
2256 compatible = "qcom,fastrpc-compute-cb";
2259 /* note: shared-cb = <4> in downstream */
2266 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2271 interrupt-names = "hc_irq", "pwr_irq";
2276 clock-names = "iface", "core", "xo";
2280 interconnect-names = "sdhc-ddr","cpu-sdhc";
2282 power-domains = <&rpmhpd RPMHPD_CX>;
2283 operating-points-v2 = <&sdhc2_opp_table>;
2284 bus-width = <4>;
2285 dma-coherent;
2289 sdhc2_opp_table: opp-table {
2290 compatible = "operating-points-v2";
2292 opp-100000000 {
2293 opp-hz = /bits/ 64 <100000000>;
2294 required-opps = <&rpmhpd_opp_low_svs>;
2297 opp-202000000 {
2298 opp-hz = /bits/ 64 <202000000>;
2299 required-opps = <&rpmhpd_opp_svs_l1>;
2305 compatible = "qcom,sm8350-usb-hs-phy",
2306 "qcom,usb-snps-hs-7nm-phy";
2309 #phy-cells = <0>;
2312 clock-names = "ref";
2318 compatible = "qcom,sm8250-usb-hs-phy",
2319 "qcom,usb-snps-hs-7nm-phy";
2322 #phy-cells = <0>;
2325 clock-names = "ref";
2331 compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2338 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2342 reset-names = "phy", "common";
2344 #clock-cells = <1>;
2345 #phy-cells = <1>;
2350 #address-cells = <1>;
2351 #size-cells = <0>;
2376 usb_2_qmpphy: phy-wrapper@88eb000 {
2377 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2380 #address-cells = <2>;
2381 #size-cells = <2>;
2388 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2392 reset-names = "phy", "common";
2398 #phy-cells = <0>;
2399 #clock-cells = <0>;
2401 clock-names = "pipe0";
2402 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2407 compatible = "qcom,sm8350-dc-noc";
2409 #interconnect-cells = <2>;
2410 qcom,bcm-voters = <&apps_bcm_voter>;
2414 compatible = "qcom,sm8350-gem-noc";
2416 #interconnect-cells = <2>;
2417 qcom,bcm-voters = <&apps_bcm_voter>;
2420 system-cache-controller@9200000 {
2421 compatible = "qcom,sm8350-llcc";
2425 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2430 compatible = "qcom,sm8350-compute-noc";
2432 #interconnect-cells = <2>;
2433 qcom,bcm-voters = <&apps_bcm_voter>;
2437 compatible = "qcom,sm8350-cdsp-pas";
2440 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2445 interrupt-names = "wdog", "fatal", "ready",
2446 "handover", "stop-ack";
2449 clock-names = "xo";
2451 power-domains = <&rpmhpd RPMHPD_CX>,
2453 power-domain-names = "cx", "mxc";
2457 memory-region = <&pil_cdsp_mem>;
2461 qcom,smem-states = <&smp2p_cdsp_out 0>;
2462 qcom,smem-state-names = "stop";
2466 glink-edge {
2467 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2474 qcom,remote-pid = <5>;
2478 qcom,glink-channels = "fastrpcglink-apps-dsp";
2480 qcom,non-secure-domain;
2481 #address-cells = <1>;
2482 #size-cells = <0>;
2484 compute-cb@1 {
2485 compatible = "qcom,fastrpc-compute-cb";
2491 compute-cb@2 {
2492 compatible = "qcom,fastrpc-compute-cb";
2498 compute-cb@3 {
2499 compatible = "qcom,fastrpc-compute-cb";
2505 compute-cb@4 {
2506 compatible = "qcom,fastrpc-compute-cb";
2512 compute-cb@5 {
2513 compatible = "qcom,fastrpc-compute-cb";
2519 compute-cb@6 {
2520 compatible = "qcom,fastrpc-compute-cb";
2526 compute-cb@7 {
2527 compatible = "qcom,fastrpc-compute-cb";
2533 compute-cb@8 {
2534 compatible = "qcom,fastrpc-compute-cb";
2546 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2549 #address-cells = <2>;
2550 #size-cells = <2>;
2558 clock-names = "cfg_noc",
2564 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2566 assigned-clock-rates = <19200000>, <200000000>;
2568 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2569 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
2570 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2571 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
2572 interrupt-names = "hs_phy_irq",
2577 power-domains = <&gcc USB30_PRIM_GDSC>;
2583 interconnect-names = "usb-ddr", "apps-usb";
2593 phy-names = "usb2-phy", "usb3-phy";
2596 #address-cells = <1>;
2597 #size-cells = <0>;
2617 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2620 #address-cells = <2>;
2621 #size-cells = <2>;
2630 clock-names = "cfg_noc",
2637 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2639 assigned-clock-rates = <19200000>, <200000000>;
2641 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2642 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
2643 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2644 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
2645 interrupt-names = "hs_phy_irq",
2650 power-domains = <&gcc USB30_SEC_GDSC>;
2656 interconnect-names = "usb-ddr", "apps-usb";
2666 phy-names = "usb2-phy", "usb3-phy";
2670 mdss: display-subsystem@ae00000 {
2671 compatible = "qcom,sm8350-mdss";
2673 reg-names = "mdss";
2677 interconnect-names = "mdp0-mem", "mdp1-mem";
2679 power-domains = <&dispcc MDSS_GDSC>;
2686 clock-names = "iface", "bus", "nrt_bus", "core";
2689 interrupt-controller;
2690 #interrupt-cells = <1>;
2696 #address-cells = <2>;
2697 #size-cells = <2>;
2700 dpu_opp_table: opp-table {
2701 compatible = "operating-points-v2";
2703 /* TODO: opp-200000000 should work with
2708 opp-200000000 {
2709 opp-hz = /bits/ 64 <200000000>;
2710 required-opps = <&rpmhpd_opp_svs>;
2713 opp-300000000 {
2714 opp-hz = /bits/ 64 <300000000>;
2715 required-opps = <&rpmhpd_opp_svs>;
2718 opp-345000000 {
2719 opp-hz = /bits/ 64 <345000000>;
2720 required-opps = <&rpmhpd_opp_svs_l1>;
2723 opp-460000000 {
2724 opp-hz = /bits/ 64 <460000000>;
2725 required-opps = <&rpmhpd_opp_nom>;
2729 mdss_mdp: display-controller@ae01000 {
2730 compatible = "qcom,sm8350-dpu";
2733 reg-names = "mdp", "vbif";
2741 clock-names = "bus",
2748 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2749 assigned-clock-rates = <19200000>;
2751 operating-points-v2 = <&dpu_opp_table>;
2752 power-domains = <&rpmhpd RPMHPD_MMCX>;
2754 interrupt-parent = <&mdss>;
2758 #address-cells = <1>;
2759 #size-cells = <0>;
2764 remote-endpoint = <&mdss_dsi0_in>;
2771 remote-endpoint = <&mdss_dsi1_in>;
2778 remote-endpoint = <&mdss_dp_in>;
2784 mdss_dp: displayport-controller@ae90000 {
2785 compatible = "qcom,sm8350-dp";
2791 interrupt-parent = <&mdss>;
2798 clock-names = "core_iface",
2804 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2806 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2810 phy-names = "dp";
2812 #sound-dai-cells = <0>;
2814 operating-points-v2 = <&dp_opp_table>;
2815 power-domains = <&rpmhpd RPMHPD_MMCX>;
2820 #address-cells = <1>;
2821 #size-cells = <0>;
2826 remote-endpoint = <&dpu_intf0_out>;
2831 dp_opp_table: opp-table {
2832 compatible = "operating-points-v2";
2834 opp-160000000 {
2835 opp-hz = /bits/ 64 <160000000>;
2836 required-opps = <&rpmhpd_opp_low_svs>;
2839 opp-270000000 {
2840 opp-hz = /bits/ 64 <270000000>;
2841 required-opps = <&rpmhpd_opp_svs>;
2844 opp-540000000 {
2845 opp-hz = /bits/ 64 <540000000>;
2846 required-opps = <&rpmhpd_opp_svs_l1>;
2849 opp-810000000 {
2850 opp-hz = /bits/ 64 <810000000>;
2851 required-opps = <&rpmhpd_opp_nom>;
2857 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2859 reg-names = "dsi_ctrl";
2861 interrupt-parent = <&mdss>;
2870 clock-names = "byte",
2877 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2879 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2882 operating-points-v2 = <&dsi0_opp_table>;
2883 power-domains = <&rpmhpd RPMHPD_MMCX>;
2887 #address-cells = <1>;
2888 #size-cells = <0>;
2892 dsi0_opp_table: opp-table {
2893 compatible = "operating-points-v2";
2895 /* TODO: opp-187500000 should work with
2900 opp-187500000 {
2901 opp-hz = /bits/ 64 <187500000>;
2902 required-opps = <&rpmhpd_opp_svs>;
2905 opp-300000000 {
2906 opp-hz = /bits/ 64 <300000000>;
2907 required-opps = <&rpmhpd_opp_svs>;
2910 opp-358000000 {
2911 opp-hz = /bits/ 64 <358000000>;
2912 required-opps = <&rpmhpd_opp_svs_l1>;
2917 #address-cells = <1>;
2918 #size-cells = <0>;
2923 remote-endpoint = <&dpu_intf1_out>;
2936 compatible = "qcom,sm8350-dsi-phy-5nm";
2940 reg-names = "dsi_phy",
2944 #clock-cells = <1>;
2945 #phy-cells = <0>;
2949 clock-names = "iface", "ref";
2955 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2957 reg-names = "dsi_ctrl";
2959 interrupt-parent = <&mdss>;
2968 clock-names = "byte",
2975 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2977 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2980 operating-points-v2 = <&dsi1_opp_table>;
2981 power-domains = <&rpmhpd RPMHPD_MMCX>;
2985 #address-cells = <1>;
2986 #size-cells = <0>;
2990 dsi1_opp_table: opp-table {
2991 compatible = "operating-points-v2";
2993 /* TODO: opp-187500000 should work with
2998 opp-187500000 {
2999 opp-hz = /bits/ 64 <187500000>;
3000 required-opps = <&rpmhpd_opp_svs>;
3003 opp-300000000 {
3004 opp-hz = /bits/ 64 <300000000>;
3005 required-opps = <&rpmhpd_opp_svs>;
3008 opp-358000000 {
3009 opp-hz = /bits/ 64 <358000000>;
3010 required-opps = <&rpmhpd_opp_svs_l1>;
3015 #address-cells = <1>;
3016 #size-cells = <0>;
3021 remote-endpoint = <&dpu_intf2_out>;
3034 compatible = "qcom,sm8350-dsi-phy-5nm";
3038 reg-names = "dsi_phy",
3042 #clock-cells = <1>;
3043 #phy-cells = <0>;
3047 clock-names = "iface", "ref";
3053 dispcc: clock-controller@af00000 {
3054 compatible = "qcom,sm8350-dispcc";
3061 clock-names = "bi_tcxo",
3068 #clock-cells = <1>;
3069 #reset-cells = <1>;
3070 #power-domain-cells = <1>;
3072 power-domains = <&rpmhpd RPMHPD_MMCX>;
3075 pdc: interrupt-controller@b220000 { label
3076 compatible = "qcom,sm8350-pdc", "qcom,pdc";
3078 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
3082 #interrupt-cells = <2>;
3083 interrupt-parent = <&intc>;
3084 interrupt-controller;
3087 tsens0: thermal-sensor@c263000 {
3088 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
3092 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
3093 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
3094 interrupt-names = "uplow", "critical";
3095 #thermal-sensor-cells = <1>;
3098 tsens1: thermal-sensor@c265000 {
3099 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
3103 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
3104 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
3105 interrupt-names = "uplow", "critical";
3106 #thermal-sensor-cells = <1>;
3109 aoss_qmp: power-management@c300000 {
3110 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
3112 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3116 #clock-cells = <0>;
3120 compatible = "qcom,rpmh-stats";
3125 compatible = "qcom,spmi-pmic-arb";
3131 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3132 interrupt-names = "periph_irq";
3133 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3136 #address-cells = <2>;
3137 #size-cells = <0>;
3138 interrupt-controller;
3139 #interrupt-cells = <4>;
3143 compatible = "qcom,sm8350-tlmm";
3146 gpio-controller;
3147 #gpio-cells = <2>;
3148 interrupt-controller;
3149 #interrupt-cells = <2>;
3150 gpio-ranges = <&tlmm 0 0 204>;
3151 wakeup-parent = <&pdc>;
3153 sdc2_default_state: sdc2-default-state {
3154 clk-pins {
3156 drive-strength = <16>;
3157 bias-disable;
3160 cmd-pins {
3162 drive-strength = <16>;
3163 bias-pull-up;
3166 data-pins {
3168 drive-strength = <16>;
3169 bias-pull-up;
3173 sdc2_sleep_state: sdc2-sleep-state {
3174 clk-pins {
3176 drive-strength = <2>;
3177 bias-disable;
3180 cmd-pins {
3182 drive-strength = <2>;
3183 bias-pull-up;
3186 data-pins {
3188 drive-strength = <2>;
3189 bias-pull-up;
3193 qup_uart3_default_state: qup-uart3-default-state {
3194 rx-pins {
3198 tx-pins {
3204 qup_uart6_default: qup-uart6-default-state {
3207 drive-strength = <2>;
3208 bias-disable;
3211 qup_uart18_default: qup-uart18-default-state {
3214 drive-strength = <2>;
3215 bias-disable;
3218 qup_i2c0_default: qup-i2c0-default-state {
3221 drive-strength = <2>;
3222 bias-pull-up;
3225 qup_i2c1_default: qup-i2c1-default-state {
3228 drive-strength = <2>;
3229 bias-pull-up;
3232 qup_i2c2_default: qup-i2c2-default-state {
3235 drive-strength = <2>;
3236 bias-pull-up;
3239 qup_i2c4_default: qup-i2c4-default-state {
3242 drive-strength = <2>;
3243 bias-pull-up;
3246 qup_i2c5_default: qup-i2c5-default-state {
3249 drive-strength = <2>;
3250 bias-pull-up;
3253 qup_i2c6_default: qup-i2c6-default-state {
3256 drive-strength = <2>;
3257 bias-pull-up;
3260 qup_i2c7_default: qup-i2c7-default-state {
3263 drive-strength = <2>;
3264 bias-disable;
3267 qup_i2c8_default: qup-i2c8-default-state {
3270 drive-strength = <2>;
3271 bias-pull-up;
3274 qup_i2c9_default: qup-i2c9-default-state {
3277 drive-strength = <2>;
3278 bias-pull-up;
3281 qup_i2c10_default: qup-i2c10-default-state {
3284 drive-strength = <2>;
3285 bias-pull-up;
3288 qup_i2c11_default: qup-i2c11-default-state {
3291 drive-strength = <2>;
3292 bias-pull-up;
3295 qup_i2c12_default: qup-i2c12-default-state {
3298 drive-strength = <2>;
3299 bias-pull-up;
3302 qup_i2c13_default: qup-i2c13-default-state {
3305 drive-strength = <2>;
3306 bias-pull-up;
3309 qup_i2c14_default: qup-i2c14-default-state {
3312 drive-strength = <2>;
3313 bias-disable;
3316 qup_i2c15_default: qup-i2c15-default-state {
3319 drive-strength = <2>;
3320 bias-disable;
3323 qup_i2c16_default: qup-i2c16-default-state {
3326 drive-strength = <2>;
3327 bias-disable;
3330 qup_i2c17_default: qup-i2c17-default-state {
3333 drive-strength = <2>;
3334 bias-disable;
3337 qup_i2c19_default: qup-i2c19-default-state {
3340 drive-strength = <2>;
3341 bias-disable;
3346 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
3348 #iommu-cells = <2>;
3349 #global-interrupts = <2>;
3450 intc: interrupt-controller@17a00000 {
3451 compatible = "arm,gic-v3";
3452 #interrupt-cells = <3>;
3453 interrupt-controller;
3454 #redistributor-regions = <1>;
3455 redistributor-stride = <0 0x20000>;
3462 compatible = "arm,armv7-timer-mem";
3463 #address-cells = <1>;
3464 #size-cells = <1>;
3467 clock-frequency = <19200000>;
3470 frame-number = <0>;
3478 frame-number = <1>;
3485 frame-number = <2>;
3492 frame-number = <3>;
3499 frame-number = <4>;
3506 frame-number = <5>;
3513 frame-number = <6>;
3522 compatible = "qcom,rpmh-rsc";
3526 reg-names = "drv-0", "drv-1", "drv-2";
3530 qcom,tcs-offset = <0xd00>;
3531 qcom,drv-id = <2>;
3532 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3534 power-domains = <&CLUSTER_PD>;
3536 rpmhcc: clock-controller {
3537 compatible = "qcom,sm8350-rpmh-clk";
3538 #clock-cells = <1>;
3539 clock-names = "xo";
3543 rpmhpd: power-controller {
3544 compatible = "qcom,sm8350-rpmhpd";
3545 #power-domain-cells = <1>;
3546 operating-points-v2 = <&rpmhpd_opp_table>;
3548 rpmhpd_opp_table: opp-table {
3549 compatible = "operating-points-v2";
3552 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3556 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3560 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3564 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3568 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3572 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3576 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3580 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3584 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3588 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3593 apps_bcm_voter: bcm-voter {
3594 compatible = "qcom,bcm-voter";
3599 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3603 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3608 interrupt-names = "dcvsh-irq-0",
3609 "dcvsh-irq-1",
3610 "dcvsh-irq-2";
3613 clock-names = "xo", "alternate";
3615 #freq-domain-cells = <1>;
3616 #clock-cells = <1>;
3620 thermal_zones: thermal-zones {
3621 cpu0-thermal {
3622 polling-delay-passive = <250>;
3623 polling-delay = <1000>;
3625 thermal-sensors = <&tsens0 1>;
3628 cpu0_alert0: trip-point0 {
3634 cpu0_alert1: trip-point1 {
3640 cpu0_crit: cpu-crit {
3647 cooling-maps {
3650 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3657 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3665 cpu1-thermal {
3666 polling-delay-passive = <250>;
3667 polling-delay = <1000>;
3669 thermal-sensors = <&tsens0 2>;
3672 cpu1_alert0: trip-point0 {
3678 cpu1_alert1: trip-point1 {
3684 cpu1_crit: cpu-crit {
3691 cooling-maps {
3694 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3701 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3709 cpu2-thermal {
3710 polling-delay-passive = <250>;
3711 polling-delay = <1000>;
3713 thermal-sensors = <&tsens0 3>;
3716 cpu2_alert0: trip-point0 {
3722 cpu2_alert1: trip-point1 {
3728 cpu2_crit: cpu-crit {
3735 cooling-maps {
3738 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3745 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3753 cpu3-thermal {
3754 polling-delay-passive = <250>;
3755 polling-delay = <1000>;
3757 thermal-sensors = <&tsens0 4>;
3760 cpu3_alert0: trip-point0 {
3766 cpu3_alert1: trip-point1 {
3772 cpu3_crit: cpu-crit {
3779 cooling-maps {
3782 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3789 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3797 cpu4-top-thermal {
3798 polling-delay-passive = <250>;
3799 polling-delay = <1000>;
3801 thermal-sensors = <&tsens0 7>;
3804 cpu4_top_alert0: trip-point0 {
3810 cpu4_top_alert1: trip-point1 {
3816 cpu4_top_crit: cpu-crit {
3823 cooling-maps {
3826 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3833 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3841 cpu5-top-thermal {
3842 polling-delay-passive = <250>;
3843 polling-delay = <1000>;
3845 thermal-sensors = <&tsens0 8>;
3848 cpu5_top_alert0: trip-point0 {
3854 cpu5_top_alert1: trip-point1 {
3860 cpu5_top_crit: cpu-crit {
3867 cooling-maps {
3870 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3877 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3885 cpu6-top-thermal {
3886 polling-delay-passive = <250>;
3887 polling-delay = <1000>;
3889 thermal-sensors = <&tsens0 9>;
3892 cpu6_top_alert0: trip-point0 {
3898 cpu6_top_alert1: trip-point1 {
3904 cpu6_top_crit: cpu-crit {
3911 cooling-maps {
3914 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3921 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3929 cpu7-top-thermal {
3930 polling-delay-passive = <250>;
3931 polling-delay = <1000>;
3933 thermal-sensors = <&tsens0 10>;
3936 cpu7_top_alert0: trip-point0 {
3942 cpu7_top_alert1: trip-point1 {
3948 cpu7_top_crit: cpu-crit {
3955 cooling-maps {
3958 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3965 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3973 cpu4-bottom-thermal {
3974 polling-delay-passive = <250>;
3975 polling-delay = <1000>;
3977 thermal-sensors = <&tsens0 11>;
3980 cpu4_bottom_alert0: trip-point0 {
3986 cpu4_bottom_alert1: trip-point1 {
3992 cpu4_bottom_crit: cpu-crit {
3999 cooling-maps {
4002 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4009 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4017 cpu5-bottom-thermal {
4018 polling-delay-passive = <250>;
4019 polling-delay = <1000>;
4021 thermal-sensors = <&tsens0 12>;
4024 cpu5_bottom_alert0: trip-point0 {
4030 cpu5_bottom_alert1: trip-point1 {
4036 cpu5_bottom_crit: cpu-crit {
4043 cooling-maps {
4046 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4053 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4061 cpu6-bottom-thermal {
4062 polling-delay-passive = <250>;
4063 polling-delay = <1000>;
4065 thermal-sensors = <&tsens0 13>;
4068 cpu6_bottom_alert0: trip-point0 {
4074 cpu6_bottom_alert1: trip-point1 {
4080 cpu6_bottom_crit: cpu-crit {
4087 cooling-maps {
4090 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4097 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4105 cpu7-bottom-thermal {
4106 polling-delay-passive = <250>;
4107 polling-delay = <1000>;
4109 thermal-sensors = <&tsens0 14>;
4112 cpu7_bottom_alert0: trip-point0 {
4118 cpu7_bottom_alert1: trip-point1 {
4124 cpu7_bottom_crit: cpu-crit {
4131 cooling-maps {
4134 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4141 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4149 aoss0-thermal {
4150 polling-delay-passive = <250>;
4151 polling-delay = <1000>;
4153 thermal-sensors = <&tsens0 0>;
4156 aoss0_alert0: trip-point0 {
4164 cluster0-thermal {
4165 polling-delay-passive = <250>;
4166 polling-delay = <1000>;
4168 thermal-sensors = <&tsens0 5>;
4171 cluster0_alert0: trip-point0 {
4184 cluster1-thermal {
4185 polling-delay-passive = <250>;
4186 polling-delay = <1000>;
4188 thermal-sensors = <&tsens0 6>;
4191 cluster1_alert0: trip-point0 {
4204 aoss1-thermal {
4205 polling-delay-passive = <250>;
4206 polling-delay = <1000>;
4208 thermal-sensors = <&tsens1 0>;
4211 aoss1_alert0: trip-point0 {
4219 gpu-top-thermal {
4220 polling-delay-passive = <250>;
4221 polling-delay = <1000>;
4223 thermal-sensors = <&tsens1 1>;
4226 gpu1_alert0: trip-point0 {
4234 gpu-bottom-thermal {
4235 polling-delay-passive = <250>;
4236 polling-delay = <1000>;
4238 thermal-sensors = <&tsens1 2>;
4241 gpu2_alert0: trip-point0 {
4249 nspss1-thermal {
4250 polling-delay-passive = <250>;
4251 polling-delay = <1000>;
4253 thermal-sensors = <&tsens1 3>;
4256 nspss1_alert0: trip-point0 {
4264 nspss2-thermal {
4265 polling-delay-passive = <250>;
4266 polling-delay = <1000>;
4268 thermal-sensors = <&tsens1 4>;
4271 nspss2_alert0: trip-point0 {
4279 nspss3-thermal {
4280 polling-delay-passive = <250>;
4281 polling-delay = <1000>;
4283 thermal-sensors = <&tsens1 5>;
4286 nspss3_alert0: trip-point0 {
4294 video-thermal {
4295 polling-delay-passive = <250>;
4296 polling-delay = <1000>;
4298 thermal-sensors = <&tsens1 6>;
4301 video_alert0: trip-point0 {
4309 mem-thermal {
4310 polling-delay-passive = <250>;
4311 polling-delay = <1000>;
4313 thermal-sensors = <&tsens1 7>;
4316 mem_alert0: trip-point0 {
4324 modem1-top-thermal {
4325 polling-delay-passive = <250>;
4326 polling-delay = <1000>;
4328 thermal-sensors = <&tsens1 8>;
4331 modem1_alert0: trip-point0 {
4339 modem2-top-thermal {
4340 polling-delay-passive = <250>;
4341 polling-delay = <1000>;
4343 thermal-sensors = <&tsens1 9>;
4346 modem2_alert0: trip-point0 {
4354 modem3-top-thermal {
4355 polling-delay-passive = <250>;
4356 polling-delay = <1000>;
4358 thermal-sensors = <&tsens1 10>;
4361 modem3_alert0: trip-point0 {
4369 modem4-top-thermal {
4370 polling-delay-passive = <250>;
4371 polling-delay = <1000>;
4373 thermal-sensors = <&tsens1 11>;
4376 modem4_alert0: trip-point0 {
4384 camera-top-thermal {
4385 polling-delay-passive = <250>;
4386 polling-delay = <1000>;
4388 thermal-sensors = <&tsens1 12>;
4391 camera1_alert0: trip-point0 {
4399 cam-bottom-thermal {
4400 polling-delay-passive = <250>;
4401 polling-delay = <1000>;
4403 thermal-sensors = <&tsens1 13>;
4406 camera2_alert0: trip-point0 {
4416 compatible = "arm,armv8-timer";