dts/qcom/sm8350.dtsi

1 // SPDX-License-Identifier: BSD-3-Clause
70 					cache-level = <3>;
431 			hwlocks = <&tcsr_mutex 3>;
633 		qcom,remote-pid = <3>;
691 			#interrupt-cells = <3>;
713 			#dma-cells = <3>;
833 				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
834 				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
849 				dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
850 				       <&gpi_dma2 1 3 QCOM_GPI_SPI>;
939 			#dma-cells = <3>;
1064 			/* QUP no. 3 seems to be strictly SPI-only */
1074 				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1075 				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1242 			#dma-cells = <3>;
1362 				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1363 				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1378 				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1379 				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1513 			#address-cells = <3>;
1533 					<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1606 			#address-cells = <3>;
1618 					<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1836 		gpu: gpu@3d00000 {
1916 		gmu: gmu@3d6a000 {
1962 		gpucc: clock-controller@3d90000 {
1976 		adreno_smmu: iommu@3da0000 {
2014 		lpass_ag_noc: interconnect@3c40000 {
2029 					      <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2071 					      <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2099 				qcom,remote-pid = <3>;
2121 					compute-cb@3 {
2123 						reg = <3>;
2836 					  <59 312 3>, <62 374 2>,  <64 434 2>,   <66 438 3>,
3215 					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3252 					service@3 {
3322 					compute-cb@3 {
3324 						reg = <3>;
3345 			#interrupt-cells = <3>;
3385 				frame-number = <3>;
3420 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3425 			qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
3426 					  <WAKE_TCS    3>, <CONTROL_TCS 0>;
3520 					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3574 					compute-cb@3 {
3576 						reg = <3>;
3715 			thermal-sensors = <&tsens0 3>;
4255 			thermal-sensors = <&tsens1 3>;