Lines Matching +full:0 +full:x01740000
36 #clock-cells = <0>;
44 #clock-cells = <0>;
50 #size-cells = <0>;
52 CPU0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0x0 0x200>;
99 clocks = <&cpufreq_hw 0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
117 reg = <0x0 0x300>;
118 clocks = <&cpufreq_hw 0>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
136 reg = <0x0 0x400>;
155 reg = <0x0 0x500>;
174 reg = <0x0 0x600>;
193 reg = <0x0 0x700>;
248 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 arm,psci-suspend-param = <0x40000004>;
258 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 arm,psci-suspend-param = <0x40000004>;
270 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
272 arm,psci-suspend-param = <0x41000044>;
280 arm,psci-suspend-param = <0x4100c344>;
298 reg = <0x0 0x80000000 0x0 0x0>;
311 #power-domain-cells = <0>;
317 #power-domain-cells = <0>;
323 #power-domain-cells = <0>;
329 #power-domain-cells = <0>;
335 #power-domain-cells = <0>;
341 #power-domain-cells = <0>;
347 #power-domain-cells = <0>;
353 #power-domain-cells = <0>;
359 #power-domain-cells = <0>;
408 reg = <0x0 0x80000000 0x0 0x600000>;
414 reg = <0x0 0x80700000 0x0 0x160000>;
419 reg = <0x0 0x80860000 0x0 0x20000>;
424 reg = <0x0 0x80880000 0x0 0x14000>;
430 reg = <0x0 0x80900000 0x0 0x200000>;
436 reg = <0x0 0x80b00000 0x0 0x100000>;
441 reg = <0x0 0x80c00000 0x0 0x4600000>;
446 reg = <0x0 0x85200000 0x0 0x500000>;
451 reg = <0x0 0x85700000 0x0 0x500000>;
456 reg = <0x0 0x85c00000 0x0 0x500000>;
461 reg = <0x0 0x86100000 0x0 0x2100000>;
466 reg = <0x0 0x88200000 0x0 0x1500000>;
471 reg = <0x0 0x89700000 0x0 0x1e00000>;
476 reg = <0x0 0x8b500000 0x0 0x10000>;
481 reg = <0x0 0x8b510000 0x0 0xa000>;
486 reg = <0x0 0x8b51a000 0x0 0x2000>;
491 reg = <0x0 0x8b600000 0x0 0x100000>;
496 reg = <0x0 0x8b800000 0x0 0x10000000>;
502 reg = <0x0 0x9b800000 0x0 0x280000>;
510 reg = <0x0 0xd0000000 0x0 0x800000>;
515 reg = <0x0 0xd0800000 0x0 0x76f7000>;
520 reg = <0x0 0xd7ef7000 0x0 0x9000>;
525 reg = <0x0 0xd7f00000 0x0 0x80000>;
530 reg = <0x0 0xd7f80000 0x0 0x80000>;
535 reg = <0x0 0xd8800000 0x0 0x6800000>;
549 qcom,local-pid = <0>;
573 qcom,local-pid = <0>;
597 qcom,local-pid = <0>;
632 qcom,local-pid = <0>;
647 soc: soc@0 {
650 ranges = <0 0 0 0 0x10 0>;
651 dma-ranges = <0 0 0 0 0x10 0>;
656 reg = <0x0 0x00100000 0x0 0x1f0000>;
676 <0>,
677 <0>,
678 <0>,
679 <&ufs_mem_phy_lanes 0>,
683 <0>;
688 reg = <0 0x00408000 0 0x1000>;
697 reg = <0 0x00800000 0 0x60000>;
711 dma-channel-mask = <0xff>;
712 iommus = <&apps_smmu 0x5f6 0x0>;
719 reg = <0x0 0x008c0000 0x0 0x6000>;
723 iommus = <&apps_smmu 0x5e3 0x0>;
731 reg = <0 0x00880000 0 0x4000>;
735 pinctrl-0 = <&qup_i2c14_default>;
737 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
738 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
741 #size-cells = <0>;
747 reg = <0 0x00880000 0 0x4000>;
753 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
754 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
757 #size-cells = <0>;
763 reg = <0 0x00884000 0 0x4000>;
767 pinctrl-0 = <&qup_i2c15_default>;
769 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
773 #size-cells = <0>;
779 reg = <0 0x00884000 0 0x4000>;
785 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
789 #size-cells = <0>;
795 reg = <0 0x00888000 0 0x4000>;
799 pinctrl-0 = <&qup_i2c16_default>;
801 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
805 #size-cells = <0>;
811 reg = <0 0x00888000 0 0x4000>;
817 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
821 #size-cells = <0>;
827 reg = <0 0x0088c000 0 0x4000>;
831 pinctrl-0 = <&qup_i2c17_default>;
833 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
837 #size-cells = <0>;
843 reg = <0 0x0088c000 0 0x4000>;
849 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
853 #size-cells = <0>;
861 reg = <0 0x00890000 0 0x4000>;
867 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
871 #size-cells = <0>;
877 reg = <0 0x00890000 0 0x4000>;
881 pinctrl-0 = <&qup_uart18_default>;
890 reg = <0 0x00894000 0 0x4000>;
894 pinctrl-0 = <&qup_i2c19_default>;
896 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
900 #size-cells = <0>;
906 reg = <0 0x00894000 0 0x4000>;
912 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
916 #size-cells = <0>;
923 reg = <0 0x00900000 0 0x60000>;
937 dma-channel-mask = <0x7e>;
938 iommus = <&apps_smmu 0x5b6 0x0>;
945 reg = <0x0 0x009c0000 0x0 0x6000>;
949 iommus = <&apps_smmu 0x5a3 0>;
957 reg = <0 0x00980000 0 0x4000>;
961 pinctrl-0 = <&qup_i2c0_default>;
963 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
964 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
967 #size-cells = <0>;
973 reg = <0 0x00980000 0 0x4000>;
979 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
980 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
983 #size-cells = <0>;
989 reg = <0 0x00984000 0 0x4000>;
993 pinctrl-0 = <&qup_i2c1_default>;
995 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
999 #size-cells = <0>;
1005 reg = <0 0x00984000 0 0x4000>;
1011 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1015 #size-cells = <0>;
1021 reg = <0 0x00988000 0 0x4000>;
1025 pinctrl-0 = <&qup_i2c2_default>;
1027 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1031 #size-cells = <0>;
1037 reg = <0 0x00988000 0 0x4000>;
1043 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1047 #size-cells = <0>;
1053 reg = <0 0x0098c000 0 0x4000>;
1057 pinctrl-0 = <&qup_uart3_default_state>;
1068 reg = <0 0x0098c000 0 0x4000>;
1074 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1078 #size-cells = <0>;
1084 reg = <0 0x00990000 0 0x4000>;
1088 pinctrl-0 = <&qup_i2c4_default>;
1090 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1094 #size-cells = <0>;
1100 reg = <0 0x00990000 0 0x4000>;
1106 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1110 #size-cells = <0>;
1116 reg = <0 0x00994000 0 0x4000>;
1120 pinctrl-0 = <&qup_i2c5_default>;
1122 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1126 #size-cells = <0>;
1132 reg = <0 0x00994000 0 0x4000>;
1138 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1142 #size-cells = <0>;
1148 reg = <0 0x00998000 0 0x4000>;
1152 pinctrl-0 = <&qup_i2c6_default>;
1154 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1158 #size-cells = <0>;
1164 reg = <0 0x00998000 0 0x4000>;
1170 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1174 #size-cells = <0>;
1180 reg = <0 0x00998000 0 0x4000>;
1184 pinctrl-0 = <&qup_uart6_default>;
1193 reg = <0 0x0099c000 0 0x4000>;
1197 pinctrl-0 = <&qup_i2c7_default>;
1199 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1203 #size-cells = <0>;
1209 reg = <0 0x0099c000 0 0x4000>;
1215 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1219 #size-cells = <0>;
1226 reg = <0 0x00a00000 0 0x60000>;
1240 dma-channel-mask = <0xff>;
1241 iommus = <&apps_smmu 0x56 0x0>;
1248 reg = <0x0 0x00ac0000 0x0 0x6000>;
1252 iommus = <&apps_smmu 0x43 0>;
1260 reg = <0 0x00a80000 0 0x4000>;
1264 pinctrl-0 = <&qup_i2c8_default>;
1266 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1267 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1270 #size-cells = <0>;
1276 reg = <0 0x00a80000 0 0x4000>;
1282 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1283 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1286 #size-cells = <0>;
1292 reg = <0 0x00a84000 0 0x4000>;
1296 pinctrl-0 = <&qup_i2c9_default>;
1298 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1302 #size-cells = <0>;
1308 reg = <0 0x00a84000 0 0x4000>;
1314 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1318 #size-cells = <0>;
1324 reg = <0 0x00a88000 0 0x4000>;
1328 pinctrl-0 = <&qup_i2c10_default>;
1330 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1334 #size-cells = <0>;
1340 reg = <0 0x00a88000 0 0x4000>;
1346 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1350 #size-cells = <0>;
1356 reg = <0 0x00a8c000 0 0x4000>;
1360 pinctrl-0 = <&qup_i2c11_default>;
1362 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1366 #size-cells = <0>;
1372 reg = <0 0x00a8c000 0 0x4000>;
1378 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1382 #size-cells = <0>;
1388 reg = <0 0x00a90000 0 0x4000>;
1392 pinctrl-0 = <&qup_i2c12_default>;
1394 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1398 #size-cells = <0>;
1404 reg = <0 0x00a90000 0 0x4000>;
1410 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1414 #size-cells = <0>;
1420 reg = <0 0x00a94000 0 0x4000>;
1424 pinctrl-0 = <&qup_i2c13_default>;
1426 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1430 #size-cells = <0>;
1436 reg = <0 0x00a94000 0 0x4000>;
1442 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1446 #size-cells = <0>;
1453 reg = <0 0x010d3000 0 0x1000>;
1460 reg = <0 0x01500000 0 0xa580>;
1467 reg = <0 0x01580000 0 0x1000>;
1474 reg = <0 0x01680000 0 0x1c200>;
1481 reg = <0 0x016e0000 0 0x1f180>;
1488 reg = <0 0x01700000 0 0x33000>;
1495 reg = <0 0x01740000 0 0x1f080>;
1502 reg = <0 0x01c00000 0 0x3000>,
1503 <0 0x60000000 0 0xf1d>,
1504 <0 0x60000f20 0 0xa8>,
1505 <0 0x60001000 0 0x1000>,
1506 <0 0x60100000 0 0x100000>;
1509 linux,pci-domain = <0>;
1510 bus-range = <0x00 0xff>;
1516 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1517 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1530 interrupt-map-mask = <0 0 0 0x7>;
1531 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1532 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1533 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1534 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1555 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1556 <0x100 &apps_smmu 0x1c01 0x1>;
1571 reg = <0 0x01c06000 0 0x2000>;
1585 #clock-cells = <0>;
1588 #phy-cells = <0>;
1595 reg = <0 0x01c08000 0 0x3000>,
1596 <0 0x40000000 0 0xf1d>,
1597 <0 0x40000f20 0 0xa8>,
1598 <0 0x40001000 0 0x1000>,
1599 <0 0x40100000 0 0x100000>;
1603 bus-range = <0x00 0xff>;
1609 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1610 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1615 interrupt-map-mask = <0 0 0 0x7>;
1616 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1617 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1618 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1619 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1638 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1639 <0x100 &apps_smmu 0x1c81 0x1>;
1654 reg = <0 0x01c0e000 0 0x2000>;
1668 #clock-cells = <0>;
1671 #phy-cells = <0>;
1679 reg = <0 0x01d84000 0 0x3000>;
1690 iommus = <&apps_smmu 0xe0 0x0>;
1713 <0 0>,
1714 <0 0>,
1716 <0 0>,
1717 <0 0>,
1718 <0 0>,
1719 <0 0>;
1725 reg = <0 0x01d87000 0 0x1c4>;
1736 resets = <&ufs_mem_hc 0>;
1741 reg = <0 0x01d87400 0 0x188>,
1742 <0 0x01d87600 0 0x200>,
1743 <0 0x01d87c00 0 0x200>,
1744 <0 0x01d87800 0 0x188>,
1745 <0 0x01d87a00 0 0x200>;
1747 #phy-cells = <0>;
1753 reg = <0 0x01dc4000 0 0x24000>;
1756 qcom,ee = <0>;
1758 iommus = <&apps_smmu 0x594 0x0011>,
1759 <&apps_smmu 0x596 0x0011>;
1766 reg = <0 0x01dfa000 0 0x6000>;
1769 iommus = <&apps_smmu 0x594 0x0011>,
1770 <&apps_smmu 0x596 0x0011>;
1771 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1780 iommus = <&apps_smmu 0x5c0 0x0>,
1781 <&apps_smmu 0x5c2 0x0>;
1782 reg = <0 0x01e40000 0 0x8000>,
1783 <0 0x01e50000 0 0x4b20>,
1784 <0 0x01e04000 0 0x23000>;
1791 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1801 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1802 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1808 qcom,smem-states = <&ipa_smp2p_out 0>,
1818 reg = <0x0 0x01f40000 0x0 0x40000>;
1824 reg = <0 0x033c0000 0 0x20000>,
1825 <0 0x03550000 0 0x10000>;
1833 gpio-ranges = <&lpass_tlmm 0 0 15>;
1839 reg = <0 0x03d00000 0 0x40000>,
1840 <0 0x03d9e000 0 0x1000>,
1841 <0 0x03d61000 0 0x800>;
1848 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
1919 reg = <0 0x03d6a000 0 0x34000>,
1920 <0 0x03de0000 0 0x10000>,
1921 <0 0x0b290000 0 0x10000>;
1948 iommus = <&adreno_smmu 5 0x400>;
1964 reg = <0 0x03d90000 0 0x9000>;
1979 reg = <0 0x03da0000 0 0x20000>;
2016 reg = <0 0x03c40000 0 0xf080>;
2023 reg = <0x0 0x04080000 0x0 0x4040>;
2026 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2041 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2047 qcom,smem-states = <&smp2p_modem_out 0>;
2065 reg = <0 0x05c00000 0 0x4000>;
2068 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2086 qcom,smem-states = <&smp2p_slpi_out 0>;
2107 #size-cells = <0>;
2112 iommus = <&apps_smmu 0x0541 0x0>;
2118 iommus = <&apps_smmu 0x0542 0x0>;
2124 iommus = <&apps_smmu 0x0543 0x0>;
2133 reg = <0 0x08804000 0 0x1000>;
2144 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2145 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2147 iommus = <&apps_smmu 0x4a0 0x0>;
2173 reg = <0 0x088e3000 0 0x400>;
2175 #phy-cells = <0>;
2186 reg = <0 0x088e4000 0 0x400>;
2188 #phy-cells = <0>;
2198 reg = <0 0x088e8000 0 0x3000>;
2217 #size-cells = <0>;
2219 port@0 {
2220 reg = <0>;
2244 reg = <0 0x088eb000 0 0x200>;
2261 reg = <0 0x088ebe00 0 0x200>,
2262 <0 0x088ec000 0 0x200>,
2263 <0 0x088eb200 0 0x1100>;
2264 #phy-cells = <0>;
2265 #clock-cells = <0>;
2274 reg = <0 0x090c0000 0 0x4200>;
2281 reg = <0 0x09100000 0 0xb4000>;
2288 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2289 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2290 <0 0x09600000 0 0x58000>;
2297 reg = <0 0x0a0c0000 0 0xa180>;
2304 reg = <0 0x0a6f8800 0 0x400>;
2338 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2339 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2344 reg = <0 0x0a600000 0 0xcd00>;
2346 iommus = <&apps_smmu 0x0 0x0>;
2354 #size-cells = <0>;
2356 port@0 {
2357 reg = <0>;
2375 reg = <0 0x0a8f8800 0 0x400>;
2411 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2412 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2417 reg = <0 0x0a800000 0 0xcd00>;
2419 iommus = <&apps_smmu 0x20 0x0>;
2429 reg = <0 0x0ae00000 0 0x1000>;
2432 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
2433 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
2449 iommus = <&apps_smmu 0x820 0x402>;
2488 reg = <0 0x0ae01000 0 0x8f000>,
2489 <0 0x0aeb0000 0 0x2008>;
2512 interrupts = <0>;
2516 #size-cells = <0>;
2518 port@0 {
2519 reg = <0>;
2543 reg = <0 0xae90000 0 0x200>,
2544 <0 0xae90200 0 0x200>,
2545 <0 0xae90400 0 0x600>,
2546 <0 0xae91000 0 0x400>,
2547 <0 0xae91400 0 0x400>;
2569 #sound-dai-cells = <0>;
2578 #size-cells = <0>;
2580 port@0 {
2581 reg = <0>;
2615 reg = <0 0x0ae94000 0 0x400>;
2636 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2645 #size-cells = <0>;
2675 #size-cells = <0>;
2677 port@0 {
2678 reg = <0>;
2694 reg = <0 0x0ae94400 0 0x200>,
2695 <0 0x0ae94600 0 0x280>,
2696 <0 0x0ae94900 0 0x27c>;
2702 #phy-cells = <0>;
2713 reg = <0 0x0ae96000 0 0x400>;
2734 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2743 #size-cells = <0>;
2773 #size-cells = <0>;
2775 port@0 {
2776 reg = <0>;
2792 reg = <0 0x0ae96400 0 0x200>,
2793 <0 0x0ae96600 0 0x280>,
2794 <0 0x0ae96900 0 0x27c>;
2800 #phy-cells = <0>;
2812 reg = <0 0x0af00000 0 0x10000>;
2814 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2815 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2834 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2835 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2846 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2847 <0 0x0c222000 0 0x8>; /* SROT */
2857 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2858 <0 0x0c223000 0 0x8>; /* SROT */
2868 reg = <0 0x0c300000 0 0x400>;
2873 #clock-cells = <0>;
2878 reg = <0 0x0c3f0000 0 0x400>;
2883 reg = <0x0 0x0c440000 0x0 0x1100>,
2884 <0x0 0x0c600000 0x0 0x2000000>,
2885 <0x0 0x0e600000 0x0 0x100000>,
2886 <0x0 0x0e700000 0x0 0xa0000>,
2887 <0x0 0x0c40a000 0x0 0x26000>;
2891 qcom,ee = <0>;
2892 qcom,channel = <0>;
2894 #size-cells = <0>;
2901 reg = <0 0x0f100000 0 0x300000>;
2907 gpio-ranges = <&tlmm 0 0 204>;
3104 reg = <0 0x15000000 0 0x100000>;
3209 reg = <0 0x17300000 0 0x100>;
3212 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3230 qcom,smem-states = <&smp2p_adsp_out 0>;
3250 #size-cells = <0>;
3266 #size-cells = <0>;
3284 #size-cells = <0>;
3286 iommus = <&apps_smmu 0x1801 0x0>;
3288 dai@0 {
3289 reg = <0>;
3309 #sound-dai-cells = <0>;
3320 #size-cells = <0>;
3325 iommus = <&apps_smmu 0x1803 0x0>;
3331 iommus = <&apps_smmu 0x1804 0x0>;
3337 iommus = <&apps_smmu 0x1805 0x0>;
3348 redistributor-stride = <0 0x20000>;
3349 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3350 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3358 ranges = <0 0 0 0x20000000>;
3359 reg = <0x0 0x17c20000 0x0 0x1000>;
3363 frame-number = <0>;
3366 reg = <0x17c21000 0x1000>,
3367 <0x17c22000 0x1000>;
3373 reg = <0x17c23000 0x1000>;
3380 reg = <0x17c25000 0x1000>;
3387 reg = <0x17c27000 0x1000>;
3394 reg = <0x17c29000 0x1000>;
3401 reg = <0x17c2b000 0x1000>;
3408 reg = <0x17c2d000 0x1000>;
3416 reg = <0x0 0x18200000 0x0 0x10000>,
3417 <0x0 0x18210000 0x0 0x10000>,
3418 <0x0 0x18220000 0x0 0x10000>;
3419 reg-names = "drv-0", "drv-1", "drv-2";
3423 qcom,tcs-offset = <0xd00>;
3426 <WAKE_TCS 3>, <CONTROL_TCS 0>;
3493 reg = <0 0x18591000 0 0x1000>,
3494 <0 0x18592000 0 0x1000>,
3495 <0 0x18593000 0 0x1000>;
3501 interrupt-names = "dcvsh-irq-0",
3514 reg = <0 0x98900000 0 0x1400000>;
3517 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3531 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3537 qcom,smem-states = <&smp2p_cdsp_out 0>;
3558 #size-cells = <0>;
3563 iommus = <&apps_smmu 0x2161 0x0400>,
3564 <&apps_smmu 0x1181 0x0420>;
3570 iommus = <&apps_smmu 0x2162 0x0400>,
3571 <&apps_smmu 0x1182 0x0420>;
3577 iommus = <&apps_smmu 0x2163 0x0400>,
3578 <&apps_smmu 0x1183 0x0420>;
3584 iommus = <&apps_smmu 0x2164 0x0400>,
3585 <&apps_smmu 0x1184 0x0420>;
3591 iommus = <&apps_smmu 0x2165 0x0400>,
3592 <&apps_smmu 0x1185 0x0420>;
3598 iommus = <&apps_smmu 0x2166 0x0400>,
3599 <&apps_smmu 0x1186 0x0420>;
3605 iommus = <&apps_smmu 0x2167 0x0400>,
3606 <&apps_smmu 0x1187 0x0420>;
3612 iommus = <&apps_smmu 0x2168 0x0400>,
3613 <&apps_smmu 0x1188 0x0420>;
4155 thermal-sensors = <&tsens0 0>;
4210 thermal-sensors = <&tsens1 0>;