Lines Matching +full:sdm845 +full:- +full:dispcc
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sm8250.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/power/qcom,rpmhpd.h>
20 #include <dt-bindings/soc/qcom,apr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6afe.h>
23 #include <dt-bindings/thermal/thermal.h>
24 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
25 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
28 interrupt-parent = <&intc>;
30 #address-cells = <2>;
31 #size-cells = <2>;
79 xo_board: xo-board {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <38400000>;
83 clock-output-names = "xo_board";
86 sleep_clk: sleep-clk {
87 compatible = "fixed-clock";
88 clock-frequency = <32768>;
89 #clock-cells = <0>;
94 #address-cells = <2>;
95 #size-cells = <0>;
102 enable-method = "psci";
103 capacity-dmips-mhz = <448>;
104 dynamic-power-coefficient = <105>;
105 next-level-cache = <&L2_0>;
106 power-domains = <&CPU_PD0>;
107 power-domain-names = "psci";
108 qcom,freq-domain = <&cpufreq_hw 0>;
109 operating-points-v2 = <&cpu0_opp_table>;
112 #cooling-cells = <2>;
113 L2_0: l2-cache {
115 cache-level = <2>;
116 cache-size = <0x20000>;
117 cache-unified;
118 next-level-cache = <&L3_0>;
119 L3_0: l3-cache {
121 cache-level = <3>;
122 cache-size = <0x400000>;
123 cache-unified;
133 enable-method = "psci";
134 capacity-dmips-mhz = <448>;
135 dynamic-power-coefficient = <105>;
136 next-level-cache = <&L2_100>;
137 power-domains = <&CPU_PD1>;
138 power-domain-names = "psci";
139 qcom,freq-domain = <&cpufreq_hw 0>;
140 operating-points-v2 = <&cpu0_opp_table>;
143 #cooling-cells = <2>;
144 L2_100: l2-cache {
146 cache-level = <2>;
147 cache-size = <0x20000>;
148 cache-unified;
149 next-level-cache = <&L3_0>;
158 enable-method = "psci";
159 capacity-dmips-mhz = <448>;
160 dynamic-power-coefficient = <105>;
161 next-level-cache = <&L2_200>;
162 power-domains = <&CPU_PD2>;
163 power-domain-names = "psci";
164 qcom,freq-domain = <&cpufreq_hw 0>;
165 operating-points-v2 = <&cpu0_opp_table>;
168 #cooling-cells = <2>;
169 L2_200: l2-cache {
171 cache-level = <2>;
172 cache-size = <0x20000>;
173 cache-unified;
174 next-level-cache = <&L3_0>;
183 enable-method = "psci";
184 capacity-dmips-mhz = <448>;
185 dynamic-power-coefficient = <105>;
186 next-level-cache = <&L2_300>;
187 power-domains = <&CPU_PD3>;
188 power-domain-names = "psci";
189 qcom,freq-domain = <&cpufreq_hw 0>;
190 operating-points-v2 = <&cpu0_opp_table>;
193 #cooling-cells = <2>;
194 L2_300: l2-cache {
196 cache-level = <2>;
197 cache-size = <0x20000>;
198 cache-unified;
199 next-level-cache = <&L3_0>;
208 enable-method = "psci";
209 capacity-dmips-mhz = <1024>;
210 dynamic-power-coefficient = <379>;
211 next-level-cache = <&L2_400>;
212 power-domains = <&CPU_PD4>;
213 power-domain-names = "psci";
214 qcom,freq-domain = <&cpufreq_hw 1>;
215 operating-points-v2 = <&cpu4_opp_table>;
218 #cooling-cells = <2>;
219 L2_400: l2-cache {
221 cache-level = <2>;
222 cache-size = <0x40000>;
223 cache-unified;
224 next-level-cache = <&L3_0>;
233 enable-method = "psci";
234 capacity-dmips-mhz = <1024>;
235 dynamic-power-coefficient = <379>;
236 next-level-cache = <&L2_500>;
237 power-domains = <&CPU_PD5>;
238 power-domain-names = "psci";
239 qcom,freq-domain = <&cpufreq_hw 1>;
240 operating-points-v2 = <&cpu4_opp_table>;
243 #cooling-cells = <2>;
244 L2_500: l2-cache {
246 cache-level = <2>;
247 cache-size = <0x40000>;
248 cache-unified;
249 next-level-cache = <&L3_0>;
258 enable-method = "psci";
259 capacity-dmips-mhz = <1024>;
260 dynamic-power-coefficient = <379>;
261 next-level-cache = <&L2_600>;
262 power-domains = <&CPU_PD6>;
263 power-domain-names = "psci";
264 qcom,freq-domain = <&cpufreq_hw 1>;
265 operating-points-v2 = <&cpu4_opp_table>;
268 #cooling-cells = <2>;
269 L2_600: l2-cache {
271 cache-level = <2>;
272 cache-size = <0x40000>;
273 cache-unified;
274 next-level-cache = <&L3_0>;
283 enable-method = "psci";
284 capacity-dmips-mhz = <1024>;
285 dynamic-power-coefficient = <444>;
286 next-level-cache = <&L2_700>;
287 power-domains = <&CPU_PD7>;
288 power-domain-names = "psci";
289 qcom,freq-domain = <&cpufreq_hw 2>;
290 operating-points-v2 = <&cpu7_opp_table>;
293 #cooling-cells = <2>;
294 L2_700: l2-cache {
296 cache-level = <2>;
297 cache-size = <0x80000>;
298 cache-unified;
299 next-level-cache = <&L3_0>;
303 cpu-map {
339 idle-states {
340 entry-method = "psci";
342 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
343 compatible = "arm,idle-state";
344 idle-state-name = "silver-rail-power-collapse";
345 arm,psci-suspend-param = <0x40000004>;
346 entry-latency-us = <360>;
347 exit-latency-us = <531>;
348 min-residency-us = <3934>;
349 local-timer-stop;
352 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
353 compatible = "arm,idle-state";
354 idle-state-name = "gold-rail-power-collapse";
355 arm,psci-suspend-param = <0x40000004>;
356 entry-latency-us = <702>;
357 exit-latency-us = <1061>;
358 min-residency-us = <4488>;
359 local-timer-stop;
363 domain-idle-states {
364 CLUSTER_SLEEP_0: cluster-sleep-0 {
365 compatible = "domain-idle-state";
366 arm,psci-suspend-param = <0x4100c244>;
367 entry-latency-us = <3264>;
368 exit-latency-us = <6562>;
369 min-residency-us = <9987>;
374 cpu0_opp_table: opp-table-cpu0 {
375 compatible = "operating-points-v2";
376 opp-shared;
378 cpu0_opp1: opp-300000000 {
379 opp-hz = /bits/ 64 <300000000>;
380 opp-peak-kBps = <800000 9600000>;
383 cpu0_opp2: opp-403200000 {
384 opp-hz = /bits/ 64 <403200000>;
385 opp-peak-kBps = <800000 9600000>;
388 cpu0_opp3: opp-518400000 {
389 opp-hz = /bits/ 64 <518400000>;
390 opp-peak-kBps = <800000 16588800>;
393 cpu0_opp4: opp-614400000 {
394 opp-hz = /bits/ 64 <614400000>;
395 opp-peak-kBps = <800000 16588800>;
398 cpu0_opp5: opp-691200000 {
399 opp-hz = /bits/ 64 <691200000>;
400 opp-peak-kBps = <800000 19660800>;
403 cpu0_opp6: opp-787200000 {
404 opp-hz = /bits/ 64 <787200000>;
405 opp-peak-kBps = <1804000 19660800>;
408 cpu0_opp7: opp-883200000 {
409 opp-hz = /bits/ 64 <883200000>;
410 opp-peak-kBps = <1804000 23347200>;
413 cpu0_opp8: opp-979200000 {
414 opp-hz = /bits/ 64 <979200000>;
415 opp-peak-kBps = <1804000 26419200>;
418 cpu0_opp9: opp-1075200000 {
419 opp-hz = /bits/ 64 <1075200000>;
420 opp-peak-kBps = <1804000 29491200>;
423 cpu0_opp10: opp-1171200000 {
424 opp-hz = /bits/ 64 <1171200000>;
425 opp-peak-kBps = <1804000 32563200>;
428 cpu0_opp11: opp-1248000000 {
429 opp-hz = /bits/ 64 <1248000000>;
430 opp-peak-kBps = <1804000 36249600>;
433 cpu0_opp12: opp-1344000000 {
434 opp-hz = /bits/ 64 <1344000000>;
435 opp-peak-kBps = <2188000 36249600>;
438 cpu0_opp13: opp-1420800000 {
439 opp-hz = /bits/ 64 <1420800000>;
440 opp-peak-kBps = <2188000 39321600>;
443 cpu0_opp14: opp-1516800000 {
444 opp-hz = /bits/ 64 <1516800000>;
445 opp-peak-kBps = <3072000 42393600>;
448 cpu0_opp15: opp-1612800000 {
449 opp-hz = /bits/ 64 <1612800000>;
450 opp-peak-kBps = <3072000 42393600>;
453 cpu0_opp16: opp-1708800000 {
454 opp-hz = /bits/ 64 <1708800000>;
455 opp-peak-kBps = <4068000 42393600>;
458 cpu0_opp17: opp-1804800000 {
459 opp-hz = /bits/ 64 <1804800000>;
460 opp-peak-kBps = <4068000 42393600>;
464 cpu4_opp_table: opp-table-cpu4 {
465 compatible = "operating-points-v2";
466 opp-shared;
468 cpu4_opp1: opp-710400000 {
469 opp-hz = /bits/ 64 <710400000>;
470 opp-peak-kBps = <1804000 19660800>;
473 cpu4_opp2: opp-825600000 {
474 opp-hz = /bits/ 64 <825600000>;
475 opp-peak-kBps = <2188000 23347200>;
478 cpu4_opp3: opp-940800000 {
479 opp-hz = /bits/ 64 <940800000>;
480 opp-peak-kBps = <2188000 26419200>;
483 cpu4_opp4: opp-1056000000 {
484 opp-hz = /bits/ 64 <1056000000>;
485 opp-peak-kBps = <3072000 26419200>;
488 cpu4_opp5: opp-1171200000 {
489 opp-hz = /bits/ 64 <1171200000>;
490 opp-peak-kBps = <3072000 29491200>;
493 cpu4_opp6: opp-1286400000 {
494 opp-hz = /bits/ 64 <1286400000>;
495 opp-peak-kBps = <4068000 29491200>;
498 cpu4_opp7: opp-1382400000 {
499 opp-hz = /bits/ 64 <1382400000>;
500 opp-peak-kBps = <4068000 32563200>;
503 cpu4_opp8: opp-1478400000 {
504 opp-hz = /bits/ 64 <1478400000>;
505 opp-peak-kBps = <4068000 32563200>;
508 cpu4_opp9: opp-1574400000 {
509 opp-hz = /bits/ 64 <1574400000>;
510 opp-peak-kBps = <5412000 39321600>;
513 cpu4_opp10: opp-1670400000 {
514 opp-hz = /bits/ 64 <1670400000>;
515 opp-peak-kBps = <5412000 42393600>;
518 cpu4_opp11: opp-1766400000 {
519 opp-hz = /bits/ 64 <1766400000>;
520 opp-peak-kBps = <5412000 45465600>;
523 cpu4_opp12: opp-1862400000 {
524 opp-hz = /bits/ 64 <1862400000>;
525 opp-peak-kBps = <6220000 45465600>;
528 cpu4_opp13: opp-1958400000 {
529 opp-hz = /bits/ 64 <1958400000>;
530 opp-peak-kBps = <6220000 48537600>;
533 cpu4_opp14: opp-2054400000 {
534 opp-hz = /bits/ 64 <2054400000>;
535 opp-peak-kBps = <7216000 48537600>;
538 cpu4_opp15: opp-2150400000 {
539 opp-hz = /bits/ 64 <2150400000>;
540 opp-peak-kBps = <7216000 51609600>;
543 cpu4_opp16: opp-2246400000 {
544 opp-hz = /bits/ 64 <2246400000>;
545 opp-peak-kBps = <7216000 51609600>;
548 cpu4_opp17: opp-2342400000 {
549 opp-hz = /bits/ 64 <2342400000>;
550 opp-peak-kBps = <8368000 51609600>;
553 cpu4_opp18: opp-2419200000 {
554 opp-hz = /bits/ 64 <2419200000>;
555 opp-peak-kBps = <8368000 51609600>;
559 cpu7_opp_table: opp-table-cpu7 {
560 compatible = "operating-points-v2";
561 opp-shared;
563 cpu7_opp1: opp-844800000 {
564 opp-hz = /bits/ 64 <844800000>;
565 opp-peak-kBps = <2188000 19660800>;
568 cpu7_opp2: opp-960000000 {
569 opp-hz = /bits/ 64 <960000000>;
570 opp-peak-kBps = <2188000 26419200>;
573 cpu7_opp3: opp-1075200000 {
574 opp-hz = /bits/ 64 <1075200000>;
575 opp-peak-kBps = <3072000 26419200>;
578 cpu7_opp4: opp-1190400000 {
579 opp-hz = /bits/ 64 <1190400000>;
580 opp-peak-kBps = <3072000 29491200>;
583 cpu7_opp5: opp-1305600000 {
584 opp-hz = /bits/ 64 <1305600000>;
585 opp-peak-kBps = <4068000 32563200>;
588 cpu7_opp6: opp-1401600000 {
589 opp-hz = /bits/ 64 <1401600000>;
590 opp-peak-kBps = <4068000 32563200>;
593 cpu7_opp7: opp-1516800000 {
594 opp-hz = /bits/ 64 <1516800000>;
595 opp-peak-kBps = <4068000 36249600>;
598 cpu7_opp8: opp-1632000000 {
599 opp-hz = /bits/ 64 <1632000000>;
600 opp-peak-kBps = <5412000 39321600>;
603 cpu7_opp9: opp-1747200000 {
604 opp-hz = /bits/ 64 <1708800000>;
605 opp-peak-kBps = <5412000 42393600>;
608 cpu7_opp10: opp-1862400000 {
609 opp-hz = /bits/ 64 <1862400000>;
610 opp-peak-kBps = <6220000 45465600>;
613 cpu7_opp11: opp-1977600000 {
614 opp-hz = /bits/ 64 <1977600000>;
615 opp-peak-kBps = <6220000 48537600>;
618 cpu7_opp12: opp-2073600000 {
619 opp-hz = /bits/ 64 <2073600000>;
620 opp-peak-kBps = <7216000 48537600>;
623 cpu7_opp13: opp-2169600000 {
624 opp-hz = /bits/ 64 <2169600000>;
625 opp-peak-kBps = <7216000 51609600>;
628 cpu7_opp14: opp-2265600000 {
629 opp-hz = /bits/ 64 <2265600000>;
630 opp-peak-kBps = <7216000 51609600>;
633 cpu7_opp15: opp-2361600000 {
634 opp-hz = /bits/ 64 <2361600000>;
635 opp-peak-kBps = <8368000 51609600>;
638 cpu7_opp16: opp-2457600000 {
639 opp-hz = /bits/ 64 <2457600000>;
640 opp-peak-kBps = <8368000 51609600>;
643 cpu7_opp17: opp-2553600000 {
644 opp-hz = /bits/ 64 <2553600000>;
645 opp-peak-kBps = <8368000 51609600>;
648 cpu7_opp18: opp-2649600000 {
649 opp-hz = /bits/ 64 <2649600000>;
650 opp-peak-kBps = <8368000 51609600>;
653 cpu7_opp19: opp-2745600000 {
654 opp-hz = /bits/ 64 <2745600000>;
655 opp-peak-kBps = <8368000 51609600>;
658 cpu7_opp20: opp-2841600000 {
659 opp-hz = /bits/ 64 <2841600000>;
660 opp-peak-kBps = <8368000 51609600>;
666 compatible = "qcom,scm-sm8250", "qcom,scm";
667 #reset-cells = <1>;
678 compatible = "arm,armv8-pmuv3";
683 compatible = "arm,psci-1.0";
686 CPU_PD0: power-domain-cpu0 {
687 #power-domain-cells = <0>;
688 power-domains = <&CLUSTER_PD>;
689 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
692 CPU_PD1: power-domain-cpu1 {
693 #power-domain-cells = <0>;
694 power-domains = <&CLUSTER_PD>;
695 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
698 CPU_PD2: power-domain-cpu2 {
699 #power-domain-cells = <0>;
700 power-domains = <&CLUSTER_PD>;
701 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
704 CPU_PD3: power-domain-cpu3 {
705 #power-domain-cells = <0>;
706 power-domains = <&CLUSTER_PD>;
707 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
710 CPU_PD4: power-domain-cpu4 {
711 #power-domain-cells = <0>;
712 power-domains = <&CLUSTER_PD>;
713 domain-idle-states = <&BIG_CPU_SLEEP_0>;
716 CPU_PD5: power-domain-cpu5 {
717 #power-domain-cells = <0>;
718 power-domains = <&CLUSTER_PD>;
719 domain-idle-states = <&BIG_CPU_SLEEP_0>;
722 CPU_PD6: power-domain-cpu6 {
723 #power-domain-cells = <0>;
724 power-domains = <&CLUSTER_PD>;
725 domain-idle-states = <&BIG_CPU_SLEEP_0>;
728 CPU_PD7: power-domain-cpu7 {
729 #power-domain-cells = <0>;
730 power-domains = <&CLUSTER_PD>;
731 domain-idle-states = <&BIG_CPU_SLEEP_0>;
734 CLUSTER_PD: power-domain-cpu-cluster0 {
735 #power-domain-cells = <0>;
736 domain-idle-states = <&CLUSTER_SLEEP_0>;
740 qup_opp_table: opp-table-qup {
741 compatible = "operating-points-v2";
743 opp-50000000 {
744 opp-hz = /bits/ 64 <50000000>;
745 required-opps = <&rpmhpd_opp_min_svs>;
748 opp-75000000 {
749 opp-hz = /bits/ 64 <75000000>;
750 required-opps = <&rpmhpd_opp_low_svs>;
753 opp-120000000 {
754 opp-hz = /bits/ 64 <120000000>;
755 required-opps = <&rpmhpd_opp_svs>;
759 reserved-memory {
760 #address-cells = <2>;
761 #size-cells = <2>;
766 no-map;
771 no-map;
775 compatible = "qcom,cmd-db";
777 no-map;
782 no-map;
787 no-map;
792 no-map;
797 no-map;
802 no-map;
807 no-map;
812 no-map;
817 no-map;
822 no-map;
827 no-map;
832 no-map;
837 no-map;
842 no-map;
847 no-map;
852 no-map;
858 memory-region = <&smem_mem>;
862 smp2p-adsp {
865 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
871 qcom,local-pid = <0>;
872 qcom,remote-pid = <2>;
874 smp2p_adsp_out: master-kernel {
875 qcom,entry-name = "master-kernel";
876 #qcom,smem-state-cells = <1>;
879 smp2p_adsp_in: slave-kernel {
880 qcom,entry-name = "slave-kernel";
881 interrupt-controller;
882 #interrupt-cells = <2>;
886 smp2p-cdsp {
889 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
895 qcom,local-pid = <0>;
896 qcom,remote-pid = <5>;
898 smp2p_cdsp_out: master-kernel {
899 qcom,entry-name = "master-kernel";
900 #qcom,smem-state-cells = <1>;
903 smp2p_cdsp_in: slave-kernel {
904 qcom,entry-name = "slave-kernel";
905 interrupt-controller;
906 #interrupt-cells = <2>;
910 smp2p-slpi {
913 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
919 qcom,local-pid = <0>;
920 qcom,remote-pid = <3>;
922 smp2p_slpi_out: master-kernel {
923 qcom,entry-name = "master-kernel";
924 #qcom,smem-state-cells = <1>;
927 smp2p_slpi_in: slave-kernel {
928 qcom,entry-name = "slave-kernel";
929 interrupt-controller;
930 #interrupt-cells = <2>;
935 #address-cells = <2>;
936 #size-cells = <2>;
938 dma-ranges = <0 0 0 0 0x10 0>;
939 compatible = "simple-bus";
941 gcc: clock-controller@100000 {
942 compatible = "qcom,gcc-sm8250";
944 #clock-cells = <1>;
945 #reset-cells = <1>;
946 #power-domain-cells = <1>;
947 clock-names = "bi_tcxo",
956 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
959 interrupt-controller;
960 #interrupt-cells = <3>;
961 #mbox-cells = <2>;
965 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
967 #address-cells = <1>;
968 #size-cells = <1>;
977 compatible = "qcom,prng-ee";
980 clock-names = "core";
983 gpi_dma2: dma-controller@800000 {
984 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
996 dma-channels = <10>;
997 dma-channel-mask = <0x3f>;
999 #dma-cells = <3>;
1004 compatible = "qcom,geni-se-qup";
1006 clock-names = "m-ahb", "s-ahb";
1009 #address-cells = <2>;
1010 #size-cells = <2>;
1016 compatible = "qcom,geni-i2c";
1018 clock-names = "se";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&qup_i2c14_default>;
1025 dma-names = "tx", "rx";
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1032 compatible = "qcom,geni-spi";
1034 clock-names = "se";
1039 dma-names = "tx", "rx";
1040 power-domains = <&rpmhpd RPMHPD_CX>;
1041 operating-points-v2 = <&qup_opp_table>;
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1048 compatible = "qcom,geni-i2c";
1050 clock-names = "se";
1052 pinctrl-names = "default";
1053 pinctrl-0 = <&qup_i2c15_default>;
1057 dma-names = "tx", "rx";
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1064 compatible = "qcom,geni-spi";
1066 clock-names = "se";
1071 dma-names = "tx", "rx";
1072 power-domains = <&rpmhpd RPMHPD_CX>;
1073 operating-points-v2 = <&qup_opp_table>;
1074 #address-cells = <1>;
1075 #size-cells = <0>;
1080 compatible = "qcom,geni-i2c";
1082 clock-names = "se";
1084 pinctrl-names = "default";
1085 pinctrl-0 = <&qup_i2c16_default>;
1089 dma-names = "tx", "rx";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1096 compatible = "qcom,geni-spi";
1098 clock-names = "se";
1103 dma-names = "tx", "rx";
1104 power-domains = <&rpmhpd RPMHPD_CX>;
1105 operating-points-v2 = <&qup_opp_table>;
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1112 compatible = "qcom,geni-i2c";
1114 clock-names = "se";
1116 pinctrl-names = "default";
1117 pinctrl-0 = <&qup_i2c17_default>;
1121 dma-names = "tx", "rx";
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1128 compatible = "qcom,geni-spi";
1130 clock-names = "se";
1135 dma-names = "tx", "rx";
1136 power-domains = <&rpmhpd RPMHPD_CX>;
1137 operating-points-v2 = <&qup_opp_table>;
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1144 compatible = "qcom,geni-uart";
1146 clock-names = "se";
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&qup_uart17_default>;
1151 power-domains = <&rpmhpd RPMHPD_CX>;
1152 operating-points-v2 = <&qup_opp_table>;
1157 compatible = "qcom,geni-i2c";
1159 clock-names = "se";
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&qup_i2c18_default>;
1166 dma-names = "tx", "rx";
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1173 compatible = "qcom,geni-spi";
1175 clock-names = "se";
1180 dma-names = "tx", "rx";
1181 power-domains = <&rpmhpd RPMHPD_CX>;
1182 operating-points-v2 = <&qup_opp_table>;
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1189 compatible = "qcom,geni-uart";
1191 clock-names = "se";
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&qup_uart18_default>;
1196 power-domains = <&rpmhpd RPMHPD_CX>;
1197 operating-points-v2 = <&qup_opp_table>;
1202 compatible = "qcom,geni-i2c";
1204 clock-names = "se";
1206 pinctrl-names = "default";
1207 pinctrl-0 = <&qup_i2c19_default>;
1211 dma-names = "tx", "rx";
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1218 compatible = "qcom,geni-spi";
1220 clock-names = "se";
1225 dma-names = "tx", "rx";
1226 power-domains = <&rpmhpd RPMHPD_CX>;
1227 operating-points-v2 = <&qup_opp_table>;
1228 #address-cells = <1>;
1229 #size-cells = <0>;
1234 gpi_dma0: dma-controller@900000 {
1235 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1250 dma-channels = <15>;
1251 dma-channel-mask = <0x7ff>;
1253 #dma-cells = <3>;
1258 compatible = "qcom,geni-se-qup";
1260 clock-names = "m-ahb", "s-ahb";
1263 #address-cells = <2>;
1264 #size-cells = <2>;
1270 compatible = "qcom,geni-i2c";
1272 clock-names = "se";
1274 pinctrl-names = "default";
1275 pinctrl-0 = <&qup_i2c0_default>;
1279 dma-names = "tx", "rx";
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1286 compatible = "qcom,geni-spi";
1288 clock-names = "se";
1293 dma-names = "tx", "rx";
1294 power-domains = <&rpmhpd RPMHPD_CX>;
1295 operating-points-v2 = <&qup_opp_table>;
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1302 compatible = "qcom,geni-i2c";
1304 clock-names = "se";
1306 pinctrl-names = "default";
1307 pinctrl-0 = <&qup_i2c1_default>;
1311 dma-names = "tx", "rx";
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1318 compatible = "qcom,geni-spi";
1320 clock-names = "se";
1325 dma-names = "tx", "rx";
1326 power-domains = <&rpmhpd RPMHPD_CX>;
1327 operating-points-v2 = <&qup_opp_table>;
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1334 compatible = "qcom,geni-i2c";
1336 clock-names = "se";
1338 pinctrl-names = "default";
1339 pinctrl-0 = <&qup_i2c2_default>;
1343 dma-names = "tx", "rx";
1344 #address-cells = <1>;
1345 #size-cells = <0>;
1350 compatible = "qcom,geni-spi";
1352 clock-names = "se";
1357 dma-names = "tx", "rx";
1358 power-domains = <&rpmhpd RPMHPD_CX>;
1359 operating-points-v2 = <&qup_opp_table>;
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1366 compatible = "qcom,geni-debug-uart";
1368 clock-names = "se";
1370 pinctrl-names = "default";
1371 pinctrl-0 = <&qup_uart2_default>;
1373 power-domains = <&rpmhpd RPMHPD_CX>;
1374 operating-points-v2 = <&qup_opp_table>;
1379 compatible = "qcom,geni-i2c";
1381 clock-names = "se";
1383 pinctrl-names = "default";
1384 pinctrl-0 = <&qup_i2c3_default>;
1388 dma-names = "tx", "rx";
1389 #address-cells = <1>;
1390 #size-cells = <0>;
1395 compatible = "qcom,geni-spi";
1397 clock-names = "se";
1402 dma-names = "tx", "rx";
1403 power-domains = <&rpmhpd RPMHPD_CX>;
1404 operating-points-v2 = <&qup_opp_table>;
1405 #address-cells = <1>;
1406 #size-cells = <0>;
1411 compatible = "qcom,geni-i2c";
1413 clock-names = "se";
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&qup_i2c4_default>;
1420 dma-names = "tx", "rx";
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1427 compatible = "qcom,geni-spi";
1429 clock-names = "se";
1434 dma-names = "tx", "rx";
1435 power-domains = <&rpmhpd RPMHPD_CX>;
1436 operating-points-v2 = <&qup_opp_table>;
1437 #address-cells = <1>;
1438 #size-cells = <0>;
1443 compatible = "qcom,geni-i2c";
1445 clock-names = "se";
1447 pinctrl-names = "default";
1448 pinctrl-0 = <&qup_i2c5_default>;
1452 dma-names = "tx", "rx";
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1459 compatible = "qcom,geni-spi";
1461 clock-names = "se";
1466 dma-names = "tx", "rx";
1467 power-domains = <&rpmhpd RPMHPD_CX>;
1468 operating-points-v2 = <&qup_opp_table>;
1469 #address-cells = <1>;
1470 #size-cells = <0>;
1475 compatible = "qcom,geni-i2c";
1477 clock-names = "se";
1479 pinctrl-names = "default";
1480 pinctrl-0 = <&qup_i2c6_default>;
1484 dma-names = "tx", "rx";
1485 #address-cells = <1>;
1486 #size-cells = <0>;
1491 compatible = "qcom,geni-spi";
1493 clock-names = "se";
1498 dma-names = "tx", "rx";
1499 power-domains = <&rpmhpd RPMHPD_CX>;
1500 operating-points-v2 = <&qup_opp_table>;
1501 #address-cells = <1>;
1502 #size-cells = <0>;
1507 compatible = "qcom,geni-uart";
1509 clock-names = "se";
1511 pinctrl-names = "default";
1512 pinctrl-0 = <&qup_uart6_default>;
1514 power-domains = <&rpmhpd RPMHPD_CX>;
1515 operating-points-v2 = <&qup_opp_table>;
1520 compatible = "qcom,geni-i2c";
1522 clock-names = "se";
1524 pinctrl-names = "default";
1525 pinctrl-0 = <&qup_i2c7_default>;
1529 dma-names = "tx", "rx";
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1536 compatible = "qcom,geni-spi";
1538 clock-names = "se";
1543 dma-names = "tx", "rx";
1544 power-domains = <&rpmhpd RPMHPD_CX>;
1545 operating-points-v2 = <&qup_opp_table>;
1546 #address-cells = <1>;
1547 #size-cells = <0>;
1552 gpi_dma1: dma-controller@a00000 {
1553 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1565 dma-channels = <10>;
1566 dma-channel-mask = <0x3f>;
1568 #dma-cells = <3>;
1573 compatible = "qcom,geni-se-qup";
1575 clock-names = "m-ahb", "s-ahb";
1578 #address-cells = <2>;
1579 #size-cells = <2>;
1585 compatible = "qcom,geni-i2c";
1587 clock-names = "se";
1589 pinctrl-names = "default";
1590 pinctrl-0 = <&qup_i2c8_default>;
1594 dma-names = "tx", "rx";
1595 #address-cells = <1>;
1596 #size-cells = <0>;
1601 compatible = "qcom,geni-spi";
1603 clock-names = "se";
1608 dma-names = "tx", "rx";
1609 power-domains = <&rpmhpd RPMHPD_CX>;
1610 operating-points-v2 = <&qup_opp_table>;
1611 #address-cells = <1>;
1612 #size-cells = <0>;
1617 compatible = "qcom,geni-i2c";
1619 clock-names = "se";
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&qup_i2c9_default>;
1626 dma-names = "tx", "rx";
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1633 compatible = "qcom,geni-spi";
1635 clock-names = "se";
1640 dma-names = "tx", "rx";
1641 power-domains = <&rpmhpd RPMHPD_CX>;
1642 operating-points-v2 = <&qup_opp_table>;
1643 #address-cells = <1>;
1644 #size-cells = <0>;
1649 compatible = "qcom,geni-i2c";
1651 clock-names = "se";
1653 pinctrl-names = "default";
1654 pinctrl-0 = <&qup_i2c10_default>;
1658 dma-names = "tx", "rx";
1659 #address-cells = <1>;
1660 #size-cells = <0>;
1665 compatible = "qcom,geni-spi";
1667 clock-names = "se";
1672 dma-names = "tx", "rx";
1673 power-domains = <&rpmhpd RPMHPD_CX>;
1674 operating-points-v2 = <&qup_opp_table>;
1675 #address-cells = <1>;
1676 #size-cells = <0>;
1681 compatible = "qcom,geni-i2c";
1683 clock-names = "se";
1685 pinctrl-names = "default";
1686 pinctrl-0 = <&qup_i2c11_default>;
1690 dma-names = "tx", "rx";
1691 #address-cells = <1>;
1692 #size-cells = <0>;
1697 compatible = "qcom,geni-spi";
1699 clock-names = "se";
1704 dma-names = "tx", "rx";
1705 power-domains = <&rpmhpd RPMHPD_CX>;
1706 operating-points-v2 = <&qup_opp_table>;
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1713 compatible = "qcom,geni-i2c";
1715 clock-names = "se";
1717 pinctrl-names = "default";
1718 pinctrl-0 = <&qup_i2c12_default>;
1722 dma-names = "tx", "rx";
1723 #address-cells = <1>;
1724 #size-cells = <0>;
1729 compatible = "qcom,geni-spi";
1731 clock-names = "se";
1736 dma-names = "tx", "rx";
1737 power-domains = <&rpmhpd RPMHPD_CX>;
1738 operating-points-v2 = <&qup_opp_table>;
1739 #address-cells = <1>;
1740 #size-cells = <0>;
1745 compatible = "qcom,geni-debug-uart";
1747 clock-names = "se";
1749 pinctrl-names = "default";
1750 pinctrl-0 = <&qup_uart12_default>;
1752 power-domains = <&rpmhpd RPMHPD_CX>;
1753 operating-points-v2 = <&qup_opp_table>;
1758 compatible = "qcom,geni-i2c";
1760 clock-names = "se";
1762 pinctrl-names = "default";
1763 pinctrl-0 = <&qup_i2c13_default>;
1767 dma-names = "tx", "rx";
1768 #address-cells = <1>;
1769 #size-cells = <0>;
1774 compatible = "qcom,geni-spi";
1776 clock-names = "se";
1781 dma-names = "tx", "rx";
1782 power-domains = <&rpmhpd RPMHPD_CX>;
1783 operating-points-v2 = <&qup_opp_table>;
1784 #address-cells = <1>;
1785 #size-cells = <0>;
1791 compatible = "qcom,sm8250-config-noc";
1793 #interconnect-cells = <2>;
1794 qcom,bcm-voters = <&apps_bcm_voter>;
1798 compatible = "qcom,sm8250-system-noc";
1800 #interconnect-cells = <2>;
1801 qcom,bcm-voters = <&apps_bcm_voter>;
1805 compatible = "qcom,sm8250-mc-virt";
1807 #interconnect-cells = <2>;
1808 qcom,bcm-voters = <&apps_bcm_voter>;
1812 compatible = "qcom,sm8250-aggre1-noc";
1814 #interconnect-cells = <2>;
1815 qcom,bcm-voters = <&apps_bcm_voter>;
1819 compatible = "qcom,sm8250-aggre2-noc";
1821 #interconnect-cells = <2>;
1822 qcom,bcm-voters = <&apps_bcm_voter>;
1826 compatible = "qcom,sm8250-compute-noc";
1828 #interconnect-cells = <2>;
1829 qcom,bcm-voters = <&apps_bcm_voter>;
1833 compatible = "qcom,sm8250-mmss-noc";
1835 #interconnect-cells = <2>;
1836 qcom,bcm-voters = <&apps_bcm_voter>;
1840 compatible = "qcom,pcie-sm8250";
1847 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1849 linux,pci-domain = <0>;
1850 bus-range = <0x00 0xff>;
1851 num-lanes = <1>;
1853 #address-cells = <3>;
1854 #size-cells = <2>;
1867 interrupt-names = "msi0", "msi1", "msi2", "msi3",
1869 #interrupt-cells = <1>;
1870 interrupt-map-mask = <0 0 0 0x7>;
1871 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1884 clock-names = "pipe",
1893 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1897 reset-names = "pci";
1899 power-domains = <&gcc PCIE_0_GDSC>;
1902 phy-names = "pciephy";
1904 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
1905 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1907 pinctrl-names = "default";
1908 pinctrl-0 = <&pcie0_default_state>;
1909 dma-coherent;
1915 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1917 #address-cells = <2>;
1918 #size-cells = <2>;
1924 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1927 reset-names = "phy";
1929 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1930 assigned-clock-rates = <100000000>;
1940 clock-names = "pipe0";
1942 #phy-cells = <0>;
1944 #clock-cells = <0>;
1945 clock-output-names = "pcie_0_pipe_clk";
1950 compatible = "qcom,pcie-sm8250";
1957 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1959 linux,pci-domain = <1>;
1960 bus-range = <0x00 0xff>;
1961 num-lanes = <2>;
1963 #address-cells = <3>;
1964 #size-cells = <2>;
1970 interrupt-names = "msi";
1971 #interrupt-cells = <1>;
1972 interrupt-map-mask = <0 0 0 0x7>;
1973 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1987 clock-names = "pipe",
1997 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1998 assigned-clock-rates = <19200000>;
2000 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2004 reset-names = "pci";
2006 power-domains = <&gcc PCIE_1_GDSC>;
2009 phy-names = "pciephy";
2011 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2012 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2014 pinctrl-names = "default";
2015 pinctrl-0 = <&pcie1_default_state>;
2016 dma-coherent;
2022 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2024 #address-cells = <2>;
2025 #size-cells = <2>;
2031 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2034 reset-names = "phy";
2036 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2037 assigned-clock-rates = <100000000>;
2049 clock-names = "pipe0";
2051 #phy-cells = <0>;
2053 #clock-cells = <0>;
2054 clock-output-names = "pcie_1_pipe_clk";
2059 compatible = "qcom,pcie-sm8250";
2066 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2068 linux,pci-domain = <2>;
2069 bus-range = <0x00 0xff>;
2070 num-lanes = <2>;
2072 #address-cells = <3>;
2073 #size-cells = <2>;
2079 interrupt-names = "msi";
2080 #interrupt-cells = <1>;
2081 interrupt-map-mask = <0 0 0 0x7>;
2082 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2096 clock-names = "pipe",
2106 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2107 assigned-clock-rates = <19200000>;
2109 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2113 reset-names = "pci";
2115 power-domains = <&gcc PCIE_2_GDSC>;
2118 phy-names = "pciephy";
2120 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2121 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2123 pinctrl-names = "default";
2124 pinctrl-0 = <&pcie2_default_state>;
2125 dma-coherent;
2131 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2133 #address-cells = <2>;
2134 #size-cells = <2>;
2140 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2143 reset-names = "phy";
2145 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2146 assigned-clock-rates = <100000000>;
2158 clock-names = "pipe0";
2160 #phy-cells = <0>;
2162 #clock-cells = <0>;
2163 clock-output-names = "pcie_2_pipe_clk";
2168 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2169 "jedec,ufs-2.0";
2173 phy-names = "ufsphy";
2174 lanes-per-direction = <2>;
2175 #reset-cells = <1>;
2177 reset-names = "rst";
2179 power-domains = <&gcc UFS_PHY_GDSC>;
2183 clock-names =
2201 freq-table-hz =
2213 interconnect-names = "ufs-ddr", "cpu-ufs";
2219 compatible = "qcom,sm8250-qmp-ufs-phy";
2222 clock-names = "ref",
2228 reset-names = "ufsphy";
2230 power-domains = <&gcc UFS_PHY_GDSC>;
2232 #phy-cells = <0>;
2237 cryptobam: dma-controller@1dc4000 {
2238 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2241 #dma-cells = <1>;
2243 qcom,controlled-remotely;
2244 num-channels = <8>;
2245 qcom,num-ees = <2>;
2255 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2258 dma-names = "rx", "tx";
2266 interconnect-names = "memory";
2270 compatible = "qcom,tcsr-mutex";
2272 #hwlock-cells = <1>;
2276 compatible = "qcom,sm8250-lpass-wsa-macro";
2285 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2287 #clock-cells = <0>;
2288 clock-output-names = "mclk";
2289 #sound-dai-cells = <1>;
2291 pinctrl-names = "default";
2292 pinctrl-0 = <&wsa_swr_active>;
2297 swr0: soundwire-controller@3250000 {
2299 compatible = "qcom,soundwire-v1.5.1";
2302 clock-names = "iface";
2304 qcom,din-ports = <2>;
2305 qcom,dout-ports = <6>;
2307 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2308 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2309 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2310 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2312 #sound-dai-cells = <1>;
2313 #address-cells = <2>;
2314 #size-cells = <0>;
2319 audiocc: clock-controller@3300000 {
2320 compatible = "qcom,sm8250-lpass-audiocc";
2322 #clock-cells = <1>;
2326 clock-names = "core", "audio", "bus";
2330 compatible = "qcom,sm8250-lpass-va-macro";
2336 clock-names = "mclk", "macro", "dcodec";
2338 #clock-cells = <0>;
2339 clock-output-names = "fsgen";
2340 #sound-dai-cells = <1>;
2344 pinctrl-names = "default";
2345 pinctrl-0 = <&rx_swr_active>;
2346 compatible = "qcom,sm8250-lpass-rx-macro";
2356 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2358 #clock-cells = <0>;
2359 clock-output-names = "mclk";
2360 #sound-dai-cells = <1>;
2363 swr1: soundwire-controller@3210000 {
2365 compatible = "qcom,soundwire-v1.5.1";
2369 clock-names = "iface";
2371 qcom,din-ports = <0>;
2372 qcom,dout-ports = <5>;
2374 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2375 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2376 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2377 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2378 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2379 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2380 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2381 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2382 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2384 #sound-dai-cells = <1>;
2385 #address-cells = <2>;
2386 #size-cells = <0>;
2390 pinctrl-names = "default";
2391 pinctrl-0 = <&tx_swr_active>;
2392 compatible = "qcom,sm8250-lpass-tx-macro";
2402 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2404 #clock-cells = <0>;
2405 clock-output-names = "mclk";
2406 #sound-dai-cells = <1>;
2410 swr2: soundwire-controller@3230000 {
2412 compatible = "qcom,soundwire-v1.5.1";
2414 interrupt-names = "core";
2418 clock-names = "iface";
2421 qcom,din-ports = <5>;
2422 qcom,dout-ports = <0>;
2423 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2424 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2425 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2426 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2427 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2428 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2429 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2430 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2431 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2432 #sound-dai-cells = <1>;
2433 #address-cells = <2>;
2434 #size-cells = <0>;
2437 aoncc: clock-controller@3380000 {
2438 compatible = "qcom,sm8250-lpass-aoncc";
2440 #clock-cells = <1>;
2444 clock-names = "core", "audio", "bus";
2448 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2451 gpio-controller;
2452 #gpio-cells = <2>;
2453 gpio-ranges = <&lpass_tlmm 0 0 14>;
2457 clock-names = "core", "audio";
2459 wsa_swr_active: wsa-swr-active-state {
2460 clk-pins {
2463 drive-strength = <2>;
2464 slew-rate = <1>;
2465 bias-disable;
2468 data-pins {
2471 drive-strength = <2>;
2472 slew-rate = <1>;
2473 bias-bus-hold;
2477 wsa_swr_sleep: wsa-swr-sleep-state {
2478 clk-pins {
2481 drive-strength = <2>;
2482 bias-pull-down;
2485 data-pins {
2488 drive-strength = <2>;
2489 bias-pull-down;
2493 dmic01_active: dmic01-active-state {
2494 clk-pins {
2497 drive-strength = <8>;
2498 output-high;
2500 data-pins {
2503 drive-strength = <8>;
2507 dmic01_sleep: dmic01-sleep-state {
2508 clk-pins {
2511 drive-strength = <2>;
2512 bias-disable;
2513 output-low;
2516 data-pins {
2519 drive-strength = <2>;
2520 bias-pull-down;
2524 rx_swr_active: rx-swr-active-state {
2525 clk-pins {
2528 drive-strength = <2>;
2529 slew-rate = <1>;
2530 bias-disable;
2533 data-pins {
2536 drive-strength = <2>;
2537 slew-rate = <1>;
2538 bias-bus-hold;
2542 tx_swr_active: tx-swr-active-state {
2543 clk-pins {
2546 drive-strength = <2>;
2547 slew-rate = <1>;
2548 bias-disable;
2551 data-pins {
2554 drive-strength = <2>;
2555 slew-rate = <1>;
2556 bias-bus-hold;
2560 tx_swr_sleep: tx-swr-sleep-state {
2561 clk-pins {
2564 drive-strength = <2>;
2565 bias-pull-down;
2568 data1-pins {
2571 drive-strength = <2>;
2572 bias-bus-hold;
2575 data2-pins {
2578 drive-strength = <2>;
2579 bias-pull-down;
2585 compatible = "qcom,adreno-650.2",
2589 reg-names = "kgsl_3d0_reg_memory";
2595 operating-points-v2 = <&gpu_opp_table>;
2599 nvmem-cells = <&gpu_speed_bin>;
2600 nvmem-cell-names = "speed_bin";
2604 zap-shader {
2605 memory-region = <&gpu_mem>;
2608 gpu_opp_table: opp-table {
2609 compatible = "operating-points-v2";
2611 opp-670000000 {
2612 opp-hz = /bits/ 64 <670000000>;
2613 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2614 opp-supported-hw = <0xa>;
2617 opp-587000000 {
2618 opp-hz = /bits/ 64 <587000000>;
2619 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2620 opp-supported-hw = <0xb>;
2623 opp-525000000 {
2624 opp-hz = /bits/ 64 <525000000>;
2625 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2626 opp-supported-hw = <0xf>;
2629 opp-490000000 {
2630 opp-hz = /bits/ 64 <490000000>;
2631 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2632 opp-supported-hw = <0xf>;
2635 opp-441600000 {
2636 opp-hz = /bits/ 64 <441600000>;
2637 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2638 opp-supported-hw = <0xf>;
2641 opp-400000000 {
2642 opp-hz = /bits/ 64 <400000000>;
2643 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2644 opp-supported-hw = <0xf>;
2647 opp-305000000 {
2648 opp-hz = /bits/ 64 <305000000>;
2649 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2650 opp-supported-hw = <0xf>;
2656 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2662 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2666 interrupt-names = "hfi", "gmu";
2673 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2675 power-domains = <&gpucc GPU_CX_GDSC>,
2677 power-domain-names = "cx", "gx";
2681 operating-points-v2 = <&gmu_opp_table>;
2685 gmu_opp_table: opp-table {
2686 compatible = "operating-points-v2";
2688 opp-200000000 {
2689 opp-hz = /bits/ 64 <200000000>;
2690 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2695 gpucc: clock-controller@3d90000 {
2696 compatible = "qcom,sm8250-gpucc";
2701 clock-names = "bi_tcxo",
2704 #clock-cells = <1>;
2705 #reset-cells = <1>;
2706 #power-domain-cells = <1>;
2710 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
2711 "qcom,smmu-500", "arm,mmu-500";
2713 #iommu-cells = <2>;
2714 #global-interrupts = <2>;
2728 clock-names = "ahb", "bus", "iface";
2730 power-domains = <&gpucc GPU_CX_GDSC>;
2731 dma-coherent;
2735 compatible = "qcom,sm8250-slpi-pas";
2738 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2743 interrupt-names = "wdog", "fatal", "ready",
2744 "handover", "stop-ack";
2747 clock-names = "xo";
2749 power-domains = <&rpmhpd RPMHPD_LCX>,
2751 power-domain-names = "lcx", "lmx";
2753 memory-region = <&slpi_mem>;
2757 qcom,smem-states = <&smp2p_slpi_out 0>;
2758 qcom,smem-state-names = "stop";
2762 glink-edge {
2763 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2770 qcom,remote-pid = <3>;
2774 qcom,glink-channels = "fastrpcglink-apps-dsp";
2776 qcom,non-secure-domain;
2777 #address-cells = <1>;
2778 #size-cells = <0>;
2780 compute-cb@1 {
2781 compatible = "qcom,fastrpc-compute-cb";
2786 compute-cb@2 {
2787 compatible = "qcom,fastrpc-compute-cb";
2792 compute-cb@3 {
2793 compatible = "qcom,fastrpc-compute-cb";
2796 /* note: shared-cb = <4> in downstream */
2803 compatible = "arm,coresight-stm", "arm,primecell";
2805 reg-names = "stm-base", "stm-stimulus-base";
2808 clock-names = "apb_pclk";
2810 out-ports {
2813 remote-endpoint = <&funnel0_in7>;
2820 compatible = "qcom,coresight-tpda", "arm,primecell";
2824 clock-names = "apb_pclk";
2826 out-ports {
2830 remote-endpoint = <&funnel_qatb_in_tpda>;
2835 in-ports {
2836 #address-cells = <1>;
2837 #size-cells = <0>;
2842 remote-endpoint = <&tpdm_mm_out_tpda9>;
2849 remote-endpoint = <&tpdm_prng_out_tpda_23>;
2856 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2860 clock-names = "apb_pclk";
2862 out-ports {
2865 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
2870 in-ports {
2873 remote-endpoint = <&tpda_out_funnel_qatb>;
2880 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2884 clock-names = "apb_pclk";
2886 out-ports {
2889 remote-endpoint = <&funnel_merg_in_funnel_in0>;
2894 in-ports {
2895 #address-cells = <1>;
2896 #size-cells = <0>;
2901 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
2908 remote-endpoint = <&stm_out>;
2915 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2919 clock-names = "apb_pclk";
2921 out-ports {
2924 remote-endpoint = <&funnel_merg_in_funnel_in1>;
2929 in-ports {
2930 #address-cells = <1>;
2931 #size-cells = <0>;
2936 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
2943 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2947 clock-names = "apb_pclk";
2949 out-ports {
2952 remote-endpoint = <&funnel_swao_in_funnel_merg>;
2957 in-ports {
2958 #address-cells = <1>;
2959 #size-cells = <0>;
2964 remote-endpoint = <&funnel_in0_out_funnel_merg>;
2971 remote-endpoint = <&funnel_in1_out_funnel_merg>;
2978 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2982 clock-names = "apb_pclk";
2984 out-ports {
2987 remote-endpoint = <&etr_in>;
2992 in-ports {
2995 remote-endpoint = <&replicator_swao_out_cx_in>;
3002 compatible = "arm,coresight-tmc", "arm,primecell";
3006 clock-names = "apb_pclk";
3007 arm,scatter-gather;
3009 in-ports {
3012 remote-endpoint = <&replicator_out>;
3019 compatible = "qcom,coresight-tpdm", "arm,primecell";
3023 clock-names = "apb_pclk";
3025 out-ports {
3028 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3035 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3036 arm,primecell-periphid = <0x000bb908>;
3041 clock-names = "apb_pclk";
3043 out-ports {
3046 remote-endpoint = <&etf_in_funnel_swao_out>;
3051 in-ports {
3052 #address-cells = <1>;
3053 #size-cells = <0>;
3058 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3065 compatible = "arm,coresight-tmc", "arm,primecell";
3069 clock-names = "apb_pclk";
3071 out-ports {
3074 remote-endpoint = <&replicator_in>;
3079 in-ports {
3083 remote-endpoint = <&funnel_swao_out_etf>;
3090 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3094 clock-names = "apb_pclk";
3096 out-ports {
3099 remote-endpoint = <&replicator_cx_in_swao_out>;
3104 in-ports {
3107 remote-endpoint = <&etf_out>;
3114 compatible = "qcom,coresight-tpdm", "arm,primecell";
3118 clock-names = "apb_pclk";
3120 out-ports {
3123 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3130 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3134 clock-names = "apb_pclk";
3136 out-ports {
3139 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3144 in-ports {
3145 #address-cells = <1>;
3146 #size-cells = <0>;
3151 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3158 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3162 clock-names = "apb_pclk";
3164 out-ports {
3167 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3172 in-ports {
3173 #address-cells = <1>;
3174 #size-cells = <0>;
3179 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3186 compatible = "arm,coresight-etm4x", "arm,primecell";
3192 clock-names = "apb_pclk";
3193 arm,coresight-loses-context-with-cpu;
3195 out-ports {
3198 remote-endpoint = <&apss_funnel_in0>;
3205 compatible = "arm,coresight-etm4x", "arm,primecell";
3211 clock-names = "apb_pclk";
3212 arm,coresight-loses-context-with-cpu;
3214 out-ports {
3217 remote-endpoint = <&apss_funnel_in1>;
3224 compatible = "arm,coresight-etm4x", "arm,primecell";
3230 clock-names = "apb_pclk";
3231 arm,coresight-loses-context-with-cpu;
3233 out-ports {
3236 remote-endpoint = <&apss_funnel_in2>;
3243 compatible = "arm,coresight-etm4x", "arm,primecell";
3249 clock-names = "apb_pclk";
3250 arm,coresight-loses-context-with-cpu;
3252 out-ports {
3255 remote-endpoint = <&apss_funnel_in3>;
3262 compatible = "arm,coresight-etm4x", "arm,primecell";
3268 clock-names = "apb_pclk";
3269 arm,coresight-loses-context-with-cpu;
3271 out-ports {
3274 remote-endpoint = <&apss_funnel_in4>;
3281 compatible = "arm,coresight-etm4x", "arm,primecell";
3287 clock-names = "apb_pclk";
3288 arm,coresight-loses-context-with-cpu;
3290 out-ports {
3293 remote-endpoint = <&apss_funnel_in5>;
3300 compatible = "arm,coresight-etm4x", "arm,primecell";
3306 clock-names = "apb_pclk";
3307 arm,coresight-loses-context-with-cpu;
3309 out-ports {
3312 remote-endpoint = <&apss_funnel_in6>;
3319 compatible = "arm,coresight-etm4x", "arm,primecell";
3325 clock-names = "apb_pclk";
3326 arm,coresight-loses-context-with-cpu;
3328 out-ports {
3331 remote-endpoint = <&apss_funnel_in7>;
3338 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3342 clock-names = "apb_pclk";
3344 out-ports {
3347 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3352 in-ports {
3353 #address-cells = <1>;
3354 #size-cells = <0>;
3359 remote-endpoint = <&etm0_out>;
3366 remote-endpoint = <&etm1_out>;
3373 remote-endpoint = <&etm2_out>;
3380 remote-endpoint = <&etm3_out>;
3387 remote-endpoint = <&etm4_out>;
3394 remote-endpoint = <&etm5_out>;
3401 remote-endpoint = <&etm6_out>;
3408 remote-endpoint = <&etm7_out>;
3415 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3419 clock-names = "apb_pclk";
3421 out-ports {
3424 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3429 in-ports {
3432 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3439 compatible = "qcom,sm8250-cdsp-pas";
3442 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3447 interrupt-names = "wdog", "fatal", "ready",
3448 "handover", "stop-ack";
3451 clock-names = "xo";
3453 power-domains = <&rpmhpd RPMHPD_CX>;
3455 memory-region = <&cdsp_mem>;
3459 qcom,smem-states = <&smp2p_cdsp_out 0>;
3460 qcom,smem-state-names = "stop";
3464 glink-edge {
3465 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3472 qcom,remote-pid = <5>;
3476 qcom,glink-channels = "fastrpcglink-apps-dsp";
3478 qcom,non-secure-domain;
3479 #address-cells = <1>;
3480 #size-cells = <0>;
3482 compute-cb@1 {
3483 compatible = "qcom,fastrpc-compute-cb";
3488 compute-cb@2 {
3489 compatible = "qcom,fastrpc-compute-cb";
3494 compute-cb@3 {
3495 compatible = "qcom,fastrpc-compute-cb";
3500 compute-cb@4 {
3501 compatible = "qcom,fastrpc-compute-cb";
3506 compute-cb@5 {
3507 compatible = "qcom,fastrpc-compute-cb";
3512 compute-cb@6 {
3513 compatible = "qcom,fastrpc-compute-cb";
3518 compute-cb@7 {
3519 compatible = "qcom,fastrpc-compute-cb";
3524 compute-cb@8 {
3525 compatible = "qcom,fastrpc-compute-cb";
3536 compatible = "qcom,sm8250-usb-hs-phy",
3537 "qcom,usb-snps-hs-7nm-phy";
3540 #phy-cells = <0>;
3543 clock-names = "ref";
3549 compatible = "qcom,sm8250-usb-hs-phy",
3550 "qcom,usb-snps-hs-7nm-phy";
3553 #phy-cells = <0>;
3556 clock-names = "ref";
3562 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3567 #address-cells = <2>;
3568 #size-cells = <2>;
3574 clock-names = "aux", "ref_clk_src", "com_aux";
3578 reset-names = "phy", "common";
3580 usb_1_ssphy: usb3-phy@88e9200 {
3587 #clock-cells = <0>;
3588 #phy-cells = <0>;
3590 clock-names = "pipe0";
3591 clock-output-names = "usb3_phy_pipe_clk_src";
3594 dp_phy: dp-phy@88ea200 {
3600 #phy-cells = <0>;
3601 #clock-cells = <1>;
3606 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3609 #address-cells = <2>;
3610 #size-cells = <2>;
3617 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3621 reset-names = "phy", "common";
3627 #clock-cells = <0>;
3628 #phy-cells = <0>;
3630 clock-names = "pipe0";
3631 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3636 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3641 interrupt-names = "hc_irq", "pwr_irq";
3646 clock-names = "iface", "core", "xo";
3648 qcom,dll-config = <0x0007642c>;
3649 qcom,ddr-config = <0x80040868>;
3650 power-domains = <&rpmhpd RPMHPD_CX>;
3651 operating-points-v2 = <&sdhc2_opp_table>;
3655 sdhc2_opp_table: opp-table {
3656 compatible = "operating-points-v2";
3658 opp-19200000 {
3659 opp-hz = /bits/ 64 <19200000>;
3660 required-opps = <&rpmhpd_opp_min_svs>;
3663 opp-50000000 {
3664 opp-hz = /bits/ 64 <50000000>;
3665 required-opps = <&rpmhpd_opp_low_svs>;
3668 opp-100000000 {
3669 opp-hz = /bits/ 64 <100000000>;
3670 required-opps = <&rpmhpd_opp_svs>;
3673 opp-202000000 {
3674 opp-hz = /bits/ 64 <202000000>;
3675 required-opps = <&rpmhpd_opp_svs_l1>;
3681 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3688 operating-points-v2 = <&llcc_bwmon_opp_table>;
3690 llcc_bwmon_opp_table: opp-table {
3691 compatible = "operating-points-v2";
3693 opp-800000 {
3694 opp-peak-kBps = <(200 * 4 * 1000)>;
3697 opp-1200000 {
3698 opp-peak-kBps = <(300 * 4 * 1000)>;
3701 opp-1804000 {
3702 opp-peak-kBps = <(451 * 4 * 1000)>;
3705 opp-2188000 {
3706 opp-peak-kBps = <(547 * 4 * 1000)>;
3709 opp-2724000 {
3710 opp-peak-kBps = <(681 * 4 * 1000)>;
3713 opp-3072000 {
3714 opp-peak-kBps = <(768 * 4 * 1000)>;
3717 opp-4068000 {
3718 opp-peak-kBps = <(1017 * 4 * 1000)>;
3723 opp-6220000 {
3724 opp-peak-kBps = <(1555 * 4 * 1000)>;
3727 opp-7216000 {
3728 opp-peak-kBps = <(1804 * 4 * 1000)>;
3731 opp-8368000 {
3732 opp-peak-kBps = <(2092 * 4 * 1000)>;
3736 opp-10944000 {
3737 opp-peak-kBps = <(2736 * 4 * 1000)>;
3743 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
3749 operating-points-v2 = <&cpu_bwmon_opp_table>;
3751 cpu_bwmon_opp_table: opp-table {
3752 compatible = "operating-points-v2";
3754 opp-800000 {
3755 opp-peak-kBps = <(200 * 4 * 1000)>;
3758 opp-1804000 {
3759 opp-peak-kBps = <(451 * 4 * 1000)>;
3762 opp-2188000 {
3763 opp-peak-kBps = <(547 * 4 * 1000)>;
3766 opp-2724000 {
3767 opp-peak-kBps = <(681 * 4 * 1000)>;
3770 opp-3072000 {
3771 opp-peak-kBps = <(768 * 4 * 1000)>;
3776 opp-6220000 {
3777 opp-peak-kBps = <(1555 * 4 * 1000)>;
3780 opp-6832000 {
3781 opp-peak-kBps = <(1708 * 4 * 1000)>;
3784 opp-8368000 {
3785 opp-peak-kBps = <(2092 * 4 * 1000)>;
3791 opp-10944000 {
3792 opp-peak-kBps = <(2736 * 4 * 1000)>;
3796 opp-12784000 {
3797 opp-peak-kBps = <(3196 * 4 * 1000)>;
3803 compatible = "qcom,sm8250-dc-noc";
3805 #interconnect-cells = <2>;
3806 qcom,bcm-voters = <&apps_bcm_voter>;
3810 compatible = "qcom,sm8250-gem-noc";
3812 #interconnect-cells = <2>;
3813 qcom,bcm-voters = <&apps_bcm_voter>;
3817 compatible = "qcom,sm8250-npu-noc";
3819 #interconnect-cells = <2>;
3820 qcom,bcm-voters = <&apps_bcm_voter>;
3824 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3827 #address-cells = <2>;
3828 #size-cells = <2>;
3830 dma-ranges;
3838 clock-names = "cfg_noc",
3845 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3847 assigned-clock-rates = <19200000>, <200000000>;
3849 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3853 interrupt-names = "hs_phy_irq",
3858 power-domains = <&gcc USB30_PRIM_GDSC>;
3864 interconnect-names = "usb-ddr", "apps-usb";
3874 phy-names = "usb2-phy", "usb3-phy";
3878 system-cache-controller@9200000 {
3879 compatible = "qcom,sm8250-llcc";
3883 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3888 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3891 #address-cells = <2>;
3892 #size-cells = <2>;
3894 dma-ranges;
3902 clock-names = "cfg_noc",
3909 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3911 assigned-clock-rates = <19200000>, <200000000>;
3913 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3917 interrupt-names = "hs_phy_irq",
3922 power-domains = <&gcc USB30_SEC_GDSC>;
3928 interconnect-names = "usb-ddr", "apps-usb";
3938 phy-names = "usb2-phy", "usb3-phy";
3942 venus: video-codec@aa00000 {
3943 compatible = "qcom,sm8250-venus";
3946 power-domains = <&videocc MVS0C_GDSC>,
3949 power-domain-names = "venus", "vcodec0", "mx";
3950 operating-points-v2 = <&venus_opp_table>;
3955 clock-names = "iface", "core", "vcodec0_core";
3959 interconnect-names = "cpu-cfg", "video-mem";
3962 memory-region = <&video_mem>;
3966 reset-names = "bus", "core";
3970 video-decoder {
3971 compatible = "venus-decoder";
3974 video-encoder {
3975 compatible = "venus-encoder";
3978 venus_opp_table: opp-table {
3979 compatible = "operating-points-v2";
3981 opp-720000000 {
3982 opp-hz = /bits/ 64 <720000000>;
3983 required-opps = <&rpmhpd_opp_low_svs>;
3986 opp-1014000000 {
3987 opp-hz = /bits/ 64 <1014000000>;
3988 required-opps = <&rpmhpd_opp_svs>;
3991 opp-1098000000 {
3992 opp-hz = /bits/ 64 <1098000000>;
3993 required-opps = <&rpmhpd_opp_svs_l1>;
3996 opp-1332000000 {
3997 opp-hz = /bits/ 64 <1332000000>;
3998 required-opps = <&rpmhpd_opp_nom>;
4003 videocc: clock-controller@abf0000 {
4004 compatible = "qcom,sm8250-videocc";
4009 power-domains = <&rpmhpd RPMHPD_MMCX>;
4010 required-opps = <&rpmhpd_opp_low_svs>;
4011 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4012 #clock-cells = <1>;
4013 #reset-cells = <1>;
4014 #power-domain-cells = <1>;
4018 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4019 #address-cells = <1>;
4020 #size-cells = <0>;
4024 power-domains = <&camcc TITAN_TOP_GDSC>;
4031 clock-names = "camnoc_axi",
4037 pinctrl-0 = <&cci0_default>;
4038 pinctrl-1 = <&cci0_sleep>;
4039 pinctrl-names = "default", "sleep";
4043 cci0_i2c0: i2c-bus@0 {
4045 clock-frequency = <1000000>;
4046 #address-cells = <1>;
4047 #size-cells = <0>;
4050 cci0_i2c1: i2c-bus@1 {
4052 clock-frequency = <1000000>;
4053 #address-cells = <1>;
4054 #size-cells = <0>;
4059 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4060 #address-cells = <1>;
4061 #size-cells = <0>;
4065 power-domains = <&camcc TITAN_TOP_GDSC>;
4072 clock-names = "camnoc_axi",
4078 pinctrl-0 = <&cci1_default>;
4079 pinctrl-1 = <&cci1_sleep>;
4080 pinctrl-names = "default", "sleep";
4084 cci1_i2c0: i2c-bus@0 {
4086 clock-frequency = <1000000>;
4087 #address-cells = <1>;
4088 #size-cells = <0>;
4091 cci1_i2c1: i2c-bus@1 {
4093 clock-frequency = <1000000>;
4094 #address-cells = <1>;
4095 #size-cells = <0>;
4100 compatible = "qcom,sm8250-camss";
4113 reg-names = "csiphy0",
4138 interrupt-names = "csiphy0",
4153 power-domains = <&camcc IFE_0_GDSC>,
4195 clock-names = "cam_ahb_clk",
4246 interconnect-names = "cam_ahb",
4252 #address-cells = <1>;
4253 #size-cells = <0>;
4281 camcc: clock-controller@ad00000 {
4282 compatible = "qcom,sm8250-camcc";
4288 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4289 power-domains = <&rpmhpd RPMHPD_MMCX>;
4290 required-opps = <&rpmhpd_opp_low_svs>;
4292 #clock-cells = <1>;
4293 #reset-cells = <1>;
4294 #power-domain-cells = <1>;
4297 mdss: display-subsystem@ae00000 {
4298 compatible = "qcom,sm8250-mdss";
4300 reg-names = "mdss";
4304 interconnect-names = "mdp0-mem", "mdp1-mem";
4306 power-domains = <&dispcc MDSS_GDSC>;
4308 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4311 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4312 clock-names = "iface", "bus", "nrt_bus", "core";
4315 interrupt-controller;
4316 #interrupt-cells = <1>;
4322 #address-cells = <2>;
4323 #size-cells = <2>;
4326 mdss_mdp: display-controller@ae01000 {
4327 compatible = "qcom,sm8250-dpu";
4330 reg-names = "mdp", "vbif";
4332 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4334 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4335 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4336 clock-names = "iface", "bus", "core", "vsync";
4338 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4339 assigned-clock-rates = <19200000>;
4341 operating-points-v2 = <&mdp_opp_table>;
4342 power-domains = <&rpmhpd RPMHPD_MMCX>;
4344 interrupt-parent = <&mdss>;
4348 #address-cells = <1>;
4349 #size-cells = <0>;
4354 remote-endpoint = <&mdss_dsi0_in>;
4361 remote-endpoint = <&mdss_dsi1_in>;
4366 mdp_opp_table: opp-table {
4367 compatible = "operating-points-v2";
4369 opp-200000000 {
4370 opp-hz = /bits/ 64 <200000000>;
4371 required-opps = <&rpmhpd_opp_low_svs>;
4374 opp-300000000 {
4375 opp-hz = /bits/ 64 <300000000>;
4376 required-opps = <&rpmhpd_opp_svs>;
4379 opp-345000000 {
4380 opp-hz = /bits/ 64 <345000000>;
4381 required-opps = <&rpmhpd_opp_svs_l1>;
4384 opp-460000000 {
4385 opp-hz = /bits/ 64 <460000000>;
4386 required-opps = <&rpmhpd_opp_nom>;
4392 compatible = "qcom,sm8250-dsi-ctrl",
4393 "qcom,mdss-dsi-ctrl";
4395 reg-names = "dsi_ctrl";
4397 interrupt-parent = <&mdss>;
4400 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4401 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4402 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4403 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4404 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4406 clock-names = "byte",
4413 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4414 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4416 operating-points-v2 = <&dsi_opp_table>;
4417 power-domains = <&rpmhpd RPMHPD_MMCX>;
4423 #address-cells = <1>;
4424 #size-cells = <0>;
4427 #address-cells = <1>;
4428 #size-cells = <0>;
4433 remote-endpoint = <&dpu_intf1_out>;
4444 dsi_opp_table: opp-table {
4445 compatible = "operating-points-v2";
4447 opp-187500000 {
4448 opp-hz = /bits/ 64 <187500000>;
4449 required-opps = <&rpmhpd_opp_low_svs>;
4452 opp-300000000 {
4453 opp-hz = /bits/ 64 <300000000>;
4454 required-opps = <&rpmhpd_opp_svs>;
4457 opp-358000000 {
4458 opp-hz = /bits/ 64 <358000000>;
4459 required-opps = <&rpmhpd_opp_svs_l1>;
4465 compatible = "qcom,dsi-phy-7nm";
4469 reg-names = "dsi_phy",
4473 #clock-cells = <1>;
4474 #phy-cells = <0>;
4476 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4478 clock-names = "iface", "ref";
4484 compatible = "qcom,sm8250-dsi-ctrl",
4485 "qcom,mdss-dsi-ctrl";
4487 reg-names = "dsi_ctrl";
4489 interrupt-parent = <&mdss>;
4492 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4493 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4494 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4495 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4496 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4498 clock-names = "byte",
4505 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4506 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4508 operating-points-v2 = <&dsi_opp_table>;
4509 power-domains = <&rpmhpd RPMHPD_MMCX>;
4515 #address-cells = <1>;
4516 #size-cells = <0>;
4519 #address-cells = <1>;
4520 #size-cells = <0>;
4525 remote-endpoint = <&dpu_intf2_out>;
4538 compatible = "qcom,dsi-phy-7nm";
4542 reg-names = "dsi_phy",
4546 #clock-cells = <1>;
4547 #phy-cells = <0>;
4549 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4551 clock-names = "iface", "ref";
4557 dispcc: clock-controller@af00000 { label
4558 compatible = "qcom,sm8250-dispcc";
4560 power-domains = <&rpmhpd RPMHPD_MMCX>;
4561 required-opps = <&rpmhpd_opp_low_svs>;
4569 clock-names = "bi_tcxo",
4576 #clock-cells = <1>;
4577 #reset-cells = <1>;
4578 #power-domain-cells = <1>;
4581 pdc: interrupt-controller@b220000 {
4582 compatible = "qcom,sm8250-pdc", "qcom,pdc";
4584 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4586 #interrupt-cells = <2>;
4587 interrupt-parent = <&intc>;
4588 interrupt-controller;
4591 tsens0: thermal-sensor@c263000 {
4592 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4598 interrupt-names = "uplow", "critical";
4599 #thermal-sensor-cells = <1>;
4602 tsens1: thermal-sensor@c265000 {
4603 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4609 interrupt-names = "uplow", "critical";
4610 #thermal-sensor-cells = <1>;
4613 aoss_qmp: power-management@c300000 {
4614 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
4616 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4622 #clock-cells = <0>;
4626 compatible = "qcom,rpmh-stats";
4631 compatible = "qcom,spmi-pmic-arb";
4637 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4638 interrupt-names = "periph_irq";
4639 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4642 #address-cells = <2>;
4643 #size-cells = <0>;
4644 interrupt-controller;
4645 #interrupt-cells = <4>;
4649 compatible = "qcom,sm8250-pinctrl";
4653 reg-names = "west", "south", "north";
4655 gpio-controller;
4656 #gpio-cells = <2>;
4657 interrupt-controller;
4658 #interrupt-cells = <2>;
4659 gpio-ranges = <&tlmm 0 0 181>;
4660 wakeup-parent = <&pdc>;
4662 cam2_default: cam2-default-state {
4663 rst-pins {
4666 drive-strength = <2>;
4667 bias-disable;
4670 mclk-pins {
4673 drive-strength = <16>;
4674 bias-disable;
4678 cam2_suspend: cam2-suspend-state {
4679 rst-pins {
4682 drive-strength = <2>;
4683 bias-pull-down;
4684 output-low;
4687 mclk-pins {
4690 drive-strength = <2>;
4691 bias-disable;
4695 cci0_default: cci0-default-state {
4696 cci0_i2c0_default: cci0-i2c0-default-pins {
4701 bias-pull-up;
4702 drive-strength = <2>; /* 2 mA */
4705 cci0_i2c1_default: cci0-i2c1-default-pins {
4710 bias-pull-up;
4711 drive-strength = <2>; /* 2 mA */
4715 cci0_sleep: cci0-sleep-state {
4716 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
4721 drive-strength = <2>; /* 2 mA */
4722 bias-pull-down;
4725 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
4730 drive-strength = <2>; /* 2 mA */
4731 bias-pull-down;
4735 cci1_default: cci1-default-state {
4736 cci1_i2c0_default: cci1-i2c0-default-pins {
4741 bias-pull-up;
4742 drive-strength = <2>; /* 2 mA */
4745 cci1_i2c1_default: cci1-i2c1-default-pins {
4750 bias-pull-up;
4751 drive-strength = <2>; /* 2 mA */
4755 cci1_sleep: cci1-sleep-state {
4756 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
4761 bias-pull-down;
4762 drive-strength = <2>; /* 2 mA */
4765 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
4770 bias-pull-down;
4771 drive-strength = <2>; /* 2 mA */
4775 pri_mi2s_active: pri-mi2s-active-state {
4776 sclk-pins {
4779 drive-strength = <8>;
4780 bias-disable;
4783 ws-pins {
4786 drive-strength = <8>;
4787 output-high;
4790 data0-pins {
4793 drive-strength = <8>;
4794 bias-disable;
4795 output-high;
4798 data1-pins {
4801 drive-strength = <8>;
4802 output-high;
4806 qup_i2c0_default: qup-i2c0-default-state {
4809 drive-strength = <2>;
4810 bias-disable;
4813 qup_i2c1_default: qup-i2c1-default-state {
4816 drive-strength = <2>;
4817 bias-disable;
4820 qup_i2c2_default: qup-i2c2-default-state {
4823 drive-strength = <2>;
4824 bias-disable;
4827 qup_i2c3_default: qup-i2c3-default-state {
4830 drive-strength = <2>;
4831 bias-disable;
4834 qup_i2c4_default: qup-i2c4-default-state {
4837 drive-strength = <2>;
4838 bias-disable;
4841 qup_i2c5_default: qup-i2c5-default-state {
4844 drive-strength = <2>;
4845 bias-disable;
4848 qup_i2c6_default: qup-i2c6-default-state {
4851 drive-strength = <2>;
4852 bias-disable;
4855 qup_i2c7_default: qup-i2c7-default-state {
4858 drive-strength = <2>;
4859 bias-disable;
4862 qup_i2c8_default: qup-i2c8-default-state {
4865 drive-strength = <2>;
4866 bias-disable;
4869 qup_i2c9_default: qup-i2c9-default-state {
4872 drive-strength = <2>;
4873 bias-disable;
4876 qup_i2c10_default: qup-i2c10-default-state {
4879 drive-strength = <2>;
4880 bias-disable;
4883 qup_i2c11_default: qup-i2c11-default-state {
4886 drive-strength = <2>;
4887 bias-disable;
4890 qup_i2c12_default: qup-i2c12-default-state {
4893 drive-strength = <2>;
4894 bias-disable;
4897 qup_i2c13_default: qup-i2c13-default-state {
4900 drive-strength = <2>;
4901 bias-disable;
4904 qup_i2c14_default: qup-i2c14-default-state {
4907 drive-strength = <2>;
4908 bias-disable;
4911 qup_i2c15_default: qup-i2c15-default-state {
4914 drive-strength = <2>;
4915 bias-disable;
4918 qup_i2c16_default: qup-i2c16-default-state {
4921 drive-strength = <2>;
4922 bias-disable;
4925 qup_i2c17_default: qup-i2c17-default-state {
4928 drive-strength = <2>;
4929 bias-disable;
4932 qup_i2c18_default: qup-i2c18-default-state {
4935 drive-strength = <2>;
4936 bias-disable;
4939 qup_i2c19_default: qup-i2c19-default-state {
4942 drive-strength = <2>;
4943 bias-disable;
4946 qup_spi0_cs: qup-spi0-cs-state {
4951 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
4956 qup_spi0_data_clk: qup-spi0-data-clk-state {
4962 qup_spi1_cs: qup-spi1-cs-state {
4967 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
4972 qup_spi1_data_clk: qup-spi1-data-clk-state {
4978 qup_spi2_cs: qup-spi2-cs-state {
4983 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
4988 qup_spi2_data_clk: qup-spi2-data-clk-state {
4994 qup_spi3_cs: qup-spi3-cs-state {
4999 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5004 qup_spi3_data_clk: qup-spi3-data-clk-state {
5010 qup_spi4_cs: qup-spi4-cs-state {
5015 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5020 qup_spi4_data_clk: qup-spi4-data-clk-state {
5026 qup_spi5_cs: qup-spi5-cs-state {
5031 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5036 qup_spi5_data_clk: qup-spi5-data-clk-state {
5042 qup_spi6_cs: qup-spi6-cs-state {
5047 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5052 qup_spi6_data_clk: qup-spi6-data-clk-state {
5058 qup_spi7_cs: qup-spi7-cs-state {
5063 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5068 qup_spi7_data_clk: qup-spi7-data-clk-state {
5074 qup_spi8_cs: qup-spi8-cs-state {
5079 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5084 qup_spi8_data_clk: qup-spi8-data-clk-state {
5090 qup_spi9_cs: qup-spi9-cs-state {
5095 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5100 qup_spi9_data_clk: qup-spi9-data-clk-state {
5106 qup_spi10_cs: qup-spi10-cs-state {
5111 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5116 qup_spi10_data_clk: qup-spi10-data-clk-state {
5122 qup_spi11_cs: qup-spi11-cs-state {
5127 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5132 qup_spi11_data_clk: qup-spi11-data-clk-state {
5138 qup_spi12_cs: qup-spi12-cs-state {
5143 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5148 qup_spi12_data_clk: qup-spi12-data-clk-state {
5154 qup_spi13_cs: qup-spi13-cs-state {
5159 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5164 qup_spi13_data_clk: qup-spi13-data-clk-state {
5170 qup_spi14_cs: qup-spi14-cs-state {
5175 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5180 qup_spi14_data_clk: qup-spi14-data-clk-state {
5186 qup_spi15_cs: qup-spi15-cs-state {
5191 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5196 qup_spi15_data_clk: qup-spi15-data-clk-state {
5202 qup_spi16_cs: qup-spi16-cs-state {
5207 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5212 qup_spi16_data_clk: qup-spi16-data-clk-state {
5218 qup_spi17_cs: qup-spi17-cs-state {
5223 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5228 qup_spi17_data_clk: qup-spi17-data-clk-state {
5234 qup_spi18_cs: qup-spi18-cs-state {
5239 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5244 qup_spi18_data_clk: qup-spi18-data-clk-state {
5250 qup_spi19_cs: qup-spi19-cs-state {
5255 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5260 qup_spi19_data_clk: qup-spi19-data-clk-state {
5266 qup_uart2_default: qup-uart2-default-state {
5271 qup_uart6_default: qup-uart6-default-state {
5276 qup_uart12_default: qup-uart12-default-state {
5281 qup_uart17_default: qup-uart17-default-state {
5286 qup_uart18_default: qup-uart18-default-state {
5291 tert_mi2s_active: tert-mi2s-active-state {
5292 sck-pins {
5295 drive-strength = <8>;
5296 bias-disable;
5299 data0-pins {
5302 drive-strength = <8>;
5303 bias-disable;
5304 output-high;
5307 ws-pins {
5310 drive-strength = <8>;
5311 output-high;
5315 sdc2_sleep_state: sdc2-sleep-state {
5316 clk-pins {
5318 drive-strength = <2>;
5319 bias-disable;
5322 cmd-pins {
5324 drive-strength = <2>;
5325 bias-pull-up;
5328 data-pins {
5330 drive-strength = <2>;
5331 bias-pull-up;
5335 pcie0_default_state: pcie0-default-state {
5336 perst-pins {
5339 drive-strength = <2>;
5340 bias-pull-down;
5343 clkreq-pins {
5346 drive-strength = <2>;
5347 bias-pull-up;
5350 wake-pins {
5353 drive-strength = <2>;
5354 bias-pull-up;
5358 pcie1_default_state: pcie1-default-state {
5359 perst-pins {
5362 drive-strength = <2>;
5363 bias-pull-down;
5366 clkreq-pins {
5369 drive-strength = <2>;
5370 bias-pull-up;
5373 wake-pins {
5376 drive-strength = <2>;
5377 bias-pull-up;
5381 pcie2_default_state: pcie2-default-state {
5382 perst-pins {
5385 drive-strength = <2>;
5386 bias-pull-down;
5389 clkreq-pins {
5392 drive-strength = <2>;
5393 bias-pull-up;
5396 wake-pins {
5399 drive-strength = <2>;
5400 bias-pull-up;
5406 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5408 #iommu-cells = <2>;
5409 #global-interrupts = <2>;
5508 dma-coherent;
5512 compatible = "qcom,sm8250-adsp-pas";
5515 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5520 interrupt-names = "wdog", "fatal", "ready",
5521 "handover", "stop-ack";
5524 clock-names = "xo";
5526 power-domains = <&rpmhpd RPMHPD_LCX>,
5528 power-domain-names = "lcx", "lmx";
5530 memory-region = <&adsp_mem>;
5534 qcom,smem-states = <&smp2p_adsp_out 0>;
5535 qcom,smem-state-names = "stop";
5539 glink-edge {
5540 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5547 qcom,remote-pid = <2>;
5550 compatible = "qcom,apr-v2";
5551 qcom,glink-channels = "apr_audio_svc";
5553 #address-cells = <1>;
5554 #size-cells = <0>;
5559 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5565 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5567 compatible = "qcom,q6afe-dais";
5568 #address-cells = <1>;
5569 #size-cells = <0>;
5570 #sound-dai-cells = <1>;
5573 q6afecc: clock-controller {
5574 compatible = "qcom,q6afe-clocks";
5575 #clock-cells = <2>;
5582 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5584 compatible = "qcom,q6asm-dais";
5585 #address-cells = <1>;
5586 #size-cells = <0>;
5587 #sound-dai-cells = <1>;
5595 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5597 compatible = "qcom,q6adm-routing";
5598 #sound-dai-cells = <0>;
5605 qcom,glink-channels = "fastrpcglink-apps-dsp";
5607 qcom,non-secure-domain;
5608 #address-cells = <1>;
5609 #size-cells = <0>;
5611 compute-cb@3 {
5612 compatible = "qcom,fastrpc-compute-cb";
5617 compute-cb@4 {
5618 compatible = "qcom,fastrpc-compute-cb";
5623 compute-cb@5 {
5624 compatible = "qcom,fastrpc-compute-cb";
5632 intc: interrupt-controller@17a00000 {
5633 compatible = "arm,gic-v3";
5634 #interrupt-cells = <3>;
5635 interrupt-controller;
5642 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
5649 #address-cells = <1>;
5650 #size-cells = <1>;
5652 compatible = "arm,armv7-timer-mem";
5654 clock-frequency = <19200000>;
5657 frame-number = <0>;
5665 frame-number = <1>;
5672 frame-number = <2>;
5679 frame-number = <3>;
5686 frame-number = <4>;
5693 frame-number = <5>;
5700 frame-number = <6>;
5709 compatible = "qcom,rpmh-rsc";
5713 reg-names = "drv-0", "drv-1", "drv-2";
5717 qcom,tcs-offset = <0xd00>;
5718 qcom,drv-id = <2>;
5719 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
5721 power-domains = <&CLUSTER_PD>;
5723 rpmhcc: clock-controller {
5724 compatible = "qcom,sm8250-rpmh-clk";
5725 #clock-cells = <1>;
5726 clock-names = "xo";
5730 rpmhpd: power-controller {
5731 compatible = "qcom,sm8250-rpmhpd";
5732 #power-domain-cells = <1>;
5733 operating-points-v2 = <&rpmhpd_opp_table>;
5735 rpmhpd_opp_table: opp-table {
5736 compatible = "operating-points-v2";
5739 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5743 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5747 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5751 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5755 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5759 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5763 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5767 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5771 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5775 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5780 apps_bcm_voter: bcm-voter {
5781 compatible = "qcom,bcm-voter";
5786 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
5790 clock-names = "xo", "alternate";
5792 #interconnect-cells = <1>;
5796 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
5800 reg-names = "freq-domain0", "freq-domain1",
5801 "freq-domain2";
5804 clock-names = "xo", "alternate";
5808 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5809 #freq-domain-cells = <1>;
5810 #clock-cells = <1>;
5818 compatible = "arm,armv8-timer";
5829 thermal-zones {
5830 cpu0-thermal {
5831 polling-delay-passive = <250>;
5832 polling-delay = <1000>;
5834 thermal-sensors = <&tsens0 1>;
5837 cpu0_alert0: trip-point0 {
5843 cpu0_alert1: trip-point1 {
5849 cpu0_crit: cpu-crit {
5856 cooling-maps {
5859 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5866 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5874 cpu1-thermal {
5875 polling-delay-passive = <250>;
5876 polling-delay = <1000>;
5878 thermal-sensors = <&tsens0 2>;
5881 cpu1_alert0: trip-point0 {
5887 cpu1_alert1: trip-point1 {
5893 cpu1_crit: cpu-crit {
5900 cooling-maps {
5903 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5910 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5918 cpu2-thermal {
5919 polling-delay-passive = <250>;
5920 polling-delay = <1000>;
5922 thermal-sensors = <&tsens0 3>;
5925 cpu2_alert0: trip-point0 {
5931 cpu2_alert1: trip-point1 {
5937 cpu2_crit: cpu-crit {
5944 cooling-maps {
5947 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5954 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5962 cpu3-thermal {
5963 polling-delay-passive = <250>;
5964 polling-delay = <1000>;
5966 thermal-sensors = <&tsens0 4>;
5969 cpu3_alert0: trip-point0 {
5975 cpu3_alert1: trip-point1 {
5981 cpu3_crit: cpu-crit {
5988 cooling-maps {
5991 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5998 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6006 cpu4-top-thermal {
6007 polling-delay-passive = <250>;
6008 polling-delay = <1000>;
6010 thermal-sensors = <&tsens0 7>;
6013 cpu4_top_alert0: trip-point0 {
6019 cpu4_top_alert1: trip-point1 {
6025 cpu4_top_crit: cpu-crit {
6032 cooling-maps {
6035 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6042 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6050 cpu5-top-thermal {
6051 polling-delay-passive = <250>;
6052 polling-delay = <1000>;
6054 thermal-sensors = <&tsens0 8>;
6057 cpu5_top_alert0: trip-point0 {
6063 cpu5_top_alert1: trip-point1 {
6069 cpu5_top_crit: cpu-crit {
6076 cooling-maps {
6079 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6086 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6094 cpu6-top-thermal {
6095 polling-delay-passive = <250>;
6096 polling-delay = <1000>;
6098 thermal-sensors = <&tsens0 9>;
6101 cpu6_top_alert0: trip-point0 {
6107 cpu6_top_alert1: trip-point1 {
6113 cpu6_top_crit: cpu-crit {
6120 cooling-maps {
6123 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6130 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6138 cpu7-top-thermal {
6139 polling-delay-passive = <250>;
6140 polling-delay = <1000>;
6142 thermal-sensors = <&tsens0 10>;
6145 cpu7_top_alert0: trip-point0 {
6151 cpu7_top_alert1: trip-point1 {
6157 cpu7_top_crit: cpu-crit {
6164 cooling-maps {
6167 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6174 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6182 cpu4-bottom-thermal {
6183 polling-delay-passive = <250>;
6184 polling-delay = <1000>;
6186 thermal-sensors = <&tsens0 11>;
6189 cpu4_bottom_alert0: trip-point0 {
6195 cpu4_bottom_alert1: trip-point1 {
6201 cpu4_bottom_crit: cpu-crit {
6208 cooling-maps {
6211 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6218 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6226 cpu5-bottom-thermal {
6227 polling-delay-passive = <250>;
6228 polling-delay = <1000>;
6230 thermal-sensors = <&tsens0 12>;
6233 cpu5_bottom_alert0: trip-point0 {
6239 cpu5_bottom_alert1: trip-point1 {
6245 cpu5_bottom_crit: cpu-crit {
6252 cooling-maps {
6255 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6262 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6270 cpu6-bottom-thermal {
6271 polling-delay-passive = <250>;
6272 polling-delay = <1000>;
6274 thermal-sensors = <&tsens0 13>;
6277 cpu6_bottom_alert0: trip-point0 {
6283 cpu6_bottom_alert1: trip-point1 {
6289 cpu6_bottom_crit: cpu-crit {
6296 cooling-maps {
6299 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 cpu7-bottom-thermal {
6315 polling-delay-passive = <250>;
6316 polling-delay = <1000>;
6318 thermal-sensors = <&tsens0 14>;
6321 cpu7_bottom_alert0: trip-point0 {
6327 cpu7_bottom_alert1: trip-point1 {
6333 cpu7_bottom_crit: cpu-crit {
6340 cooling-maps {
6343 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 aoss0-thermal {
6359 polling-delay-passive = <250>;
6360 polling-delay = <1000>;
6362 thermal-sensors = <&tsens0 0>;
6365 aoss0_alert0: trip-point0 {
6373 cluster0-thermal {
6374 polling-delay-passive = <250>;
6375 polling-delay = <1000>;
6377 thermal-sensors = <&tsens0 5>;
6380 cluster0_alert0: trip-point0 {
6393 cluster1-thermal {
6394 polling-delay-passive = <250>;
6395 polling-delay = <1000>;
6397 thermal-sensors = <&tsens0 6>;
6400 cluster1_alert0: trip-point0 {
6413 gpu-top-thermal {
6414 polling-delay-passive = <250>;
6415 polling-delay = <1000>;
6417 thermal-sensors = <&tsens0 15>;
6420 gpu1_alert0: trip-point0 {
6428 aoss1-thermal {
6429 polling-delay-passive = <250>;
6430 polling-delay = <1000>;
6432 thermal-sensors = <&tsens1 0>;
6435 aoss1_alert0: trip-point0 {
6443 wlan-thermal {
6444 polling-delay-passive = <250>;
6445 polling-delay = <1000>;
6447 thermal-sensors = <&tsens1 1>;
6450 wlan_alert0: trip-point0 {
6458 video-thermal {
6459 polling-delay-passive = <250>;
6460 polling-delay = <1000>;
6462 thermal-sensors = <&tsens1 2>;
6465 video_alert0: trip-point0 {
6473 mem-thermal {
6474 polling-delay-passive = <250>;
6475 polling-delay = <1000>;
6477 thermal-sensors = <&tsens1 3>;
6480 mem_alert0: trip-point0 {
6488 q6-hvx-thermal {
6489 polling-delay-passive = <250>;
6490 polling-delay = <1000>;
6492 thermal-sensors = <&tsens1 4>;
6495 q6_hvx_alert0: trip-point0 {
6503 camera-thermal {
6504 polling-delay-passive = <250>;
6505 polling-delay = <1000>;
6507 thermal-sensors = <&tsens1 5>;
6510 camera_alert0: trip-point0 {
6518 compute-thermal {
6519 polling-delay-passive = <250>;
6520 polling-delay = <1000>;
6522 thermal-sensors = <&tsens1 6>;
6525 compute_alert0: trip-point0 {
6533 npu-thermal {
6534 polling-delay-passive = <250>;
6535 polling-delay = <1000>;
6537 thermal-sensors = <&tsens1 7>;
6540 npu_alert0: trip-point0 {
6548 gpu-bottom-thermal {
6549 polling-delay-passive = <250>;
6550 polling-delay = <1000>;
6552 thermal-sensors = <&tsens1 8>;
6555 gpu2_alert0: trip-point0 {